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Clock Tree Synthesis Techniques

Clock tree synthesis optimizes the distribution of clock signals in a design. It involves defining clock sources, specifying timing constraints, inserting clock drivers, building global and local clock trees, and optimizing skew. Automated techniques are used to route clocks, assign taps, and balance the clock network.

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mani krishna yakkati
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441 views22 pages

Clock Tree Synthesis Techniques

Clock tree synthesis optimizes the distribution of clock signals in a design. It involves defining clock sources, specifying timing constraints, inserting clock drivers, building global and local clock trees, and optimizing skew. Automated techniques are used to route clocks, assign taps, and balance the clock network.

Uploaded by

mani krishna yakkati
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
  • Introduction to Clock Tree Synthesis
  • Prerequisites for Clock Tree Synthesis
  • Specifying Clock Root Timing Characteristics
  • Defining Clock Tree Exceptions
  • Handling Endpoints With Balancing Conflicts
  • Specifying Clock Tree References
  • Setting Skew and Latency Targets
  • Balancing Skew Between Different Clock Trees
  • Implementing Multisource Clock Trees
  • Implementing Regular Multisource Clock Trees
  • Inserting Clock Drivers
  • Synthesizing the Global Clock Trees
  • Creating Clock Straps
  • Routing to Clock Straps
  • Performing Tap Assignment
  • Building the Local Clock Subtree Structures
  • Analyzing the Clock Tree Result
  • Conclusion

CLOCK TREE SYNTHESIS

Prerequisites for Clock Tree Synthesis


• create_clock or create_generated_clock
• check_legality -verbose
• Congestion
• Timing
• Maximum capacitance
• Maximum transition time
• The power and ground nets are prerouted.
• optimizes all clocks in all active scenarios that are enabled for setup or
hold analysis.
Specifying the Clock Root Timing
Characteristics
• set_driving_cell -lib_cell mylib/CLKBUF [get_ports CLK1]
• set_input_transition -rise 0.3 [get_ports CLK1]
• set_input_transition -fall 0.2 [get_ports CLK1]
Defining Clock Tree Exceptions
Defining Sink Pins
>> set_clock_balance_points -clock [get_clocks CLK] \
-consider_for_balancing true -balance_points [get_pins U2/A]

Defining Ignore Pins


>> set_clock_balance_points -clock [get_clocks CLK] \
-consider_for_balancing false -balance_points [get_pins U2/CLK]
Handling Endpoints With Balancing Conflicts
IC Compiler II tool can automatically detect endpoints with balancing conflicts
and derive an ignore pin to resolve the conflict.
Specifying the Clock Tree References
• set_lib_cell_purpose -include cts
• derive_clock_cell_references.
Restricting the Target Libraries Used
We can restrict the libraries used during clock tree synthesis for the top
level or a lower level of the logical hierarchy of a design by using the
set_target_library_subset -clock -object
command. To enable the use of the target library subset, you must set
the
[Link].enable_target_library_subset_opt application option to
1.
Setting Skew and Latency Targets
• To specify a skew target, use
set_clock_tree_options -target_skew command.
• To specify a latency target, use
set_clock_tree_options -target_latency command.
Enabling Local Skew Optimization
• set_app_options -list {[Link].enable_local_skew true}
• set_app_options -list {[Link].enable_local_skew true}
• set_app_options -list
{[Link].enable_auto_skew_target_for_local_skew false}
Balancing Skew Between Different Clock
Trees
• create_clock_balance_group -name group1 -objects
[get_clocks {clk1 clk2}]
• create_clock_balance_group -name group3 \
-objects [get_clocks {clk1 clk2 clk3}] \
-offset_latencies {0 0 -100}
Implementing Multisource Clock Trees
• A multisource clock tree is a custom clock structure that has
more tolerance to on-chip variation and has better performance
across corners than traditional clock tree structures.
These custom clock trees consist of
• A global clock structure, which includes
 The clock root
 A global clock tree, which is usually an H-tree structure
 Clock mesh drivers
 A clock mesh
• Local subtrees that are driven
Regular Multisource Clock Tree
Structural Multisource Clock Tree
Implementing Regular Multisource Clock
Trees
1. Inserting Clock Drivers.
2. Creating Clock Straps.
3. Synthesizing the Global Clock Trees.
4. Routing to Clock Straps.
5. Analyzing Clock Mesh.
6. Performing Tap Assignment.
7. Synthesizing and Routing Clock Trees, and Optimizing the Design.
8. Analyzing the Clock Tree Results.
Inserting Clock Drivers
• Insert mesh drivers for both regular or structural multisource clock trees.
• Tap drivers for regular multisource clock trees.
• create_clock_drivers -loads [get_net clk] \
-boxes {8 8} -lib_cells [get_lib_cells my_lib/CKBUF8X] \
-short_outputs -output_net_name clk_mesh \
-transfer_wires_from [get_nets clk]
• create_clock_drivers -loads [get_nets clk] \
-configuration [list \
[list -level 1 -boxes {1 1} –lib_cells buf32x ] \
[list -level 2 -boxes {2 2} –lib_cells inv16x ] \
[list -level 3 -boxes {4 4} –lib_cells inv8x ]]
The create_clock_drivers command does not legalize the design. To do so, run the
legalize_placement command.
Synthesizing the Global Clock Trees

• To perform clock tree synthesis and detail routing to build an H-tree style global
clock tree, use the synthesize_multisource_global_clock_trees command.
• synthesize_multisource_global_clock_trees \
-nets [get_net clkA] -lib_cells [get_lib_cells my_lib/CKBUF8X] \
-use_zroute_for_pin_connections
Creating Clock Straps
• create_clock_straps -nets
[get_net clk1_mesh] \
-layers {M7 M8} -widths {2.4 2.4}
-type {stripe stripe} \
-grids {{20 1200 100} {60 980
150}} -boundary {{0 0} {1200 980}}
Routing to Clock Straps
• After creating clock straps for a clock
net by using the create_clock_straps
command, you can route the drivers
and loads of the clock net to the clock
straps by using the
route_clock_straps.
• The command supports a comb or
fishbone topology for connecting the
clock drivers and sinks to the clock
straps. -topology comb
• If you are using a fishbone topology, you
can specify
-fishbone_fanout
-fishbone_span
-fishbone_sub_span
-fishbone_layers
• For comb routing, you can specify that
the tool stops after global routing by
using the
• -stop_after_global_route true option.
By default, the tool global and detail
routes the nets for comb routing.
• For fishbone routing, it is not possible to
limit the routing to only the global
routing stage
Performing Tap Assignment
• We can perform automated tap assignment during multisource clock tree
synthesis by sing the synthesize_multisource_clock_taps command.
• Before performing automated tap assignment, you must perform the following:
Build global clock distribution structure.
 Insert the tap drivers by using the create_clock_drivers command.
Specify settings for automated tap assignment by using the
set_multisource_clock_tap_options command.
-clock
-driver_objects
-num_taps
Building the Local Clock Subtree Structures
• In a structural multisource clock tree, the local subtrees are directly driven by the
clock mesh. We can synthesize these local subtrees by using the
synthesize_multisource_clock_subtrees command.
• Before you synthesize the local subtrees, you must
 Build the global clock distribution structure.
Model the clock mesh net with a realistic annotated delay and transition values
using the set_annotated_delay and set_annotated_transition commands.
Specify settings for local subtree synthesis by using the
set_multisource_clock_subtree_options command.
-clock
-driver_objects
Analyzing the Clock Tree Result

• Generating Clock Tree QoR Reports


• Analyzing Clock Timing
THANK YOU

CLOCK TREE SYNTHESIS
Prerequisites for Clock Tree Synthesis • create_clock or create_generated_clock • check_legality -verbose • Congestion • Timi
Specifying the Clock Root Timing Characteristics • set_driving_cell -lib_cell mylib/CLKBUF [get_ports CLK1] • set_input_tran
Defining Clock Tree Exceptions Defining Sink Pins >> set_clock_balance_points -clock [get_clocks CLK] -consider_for_balanci
Handling Endpoints With Balancing Conflicts IC Compiler II tool can automatically detect endpoints with balancing conflicts
Specifying the Clock Tree References • set_lib_cell_purpose -include cts • derive_clock_cell_references. Restricting the Tar
Setting Skew and Latency Targets • To specify a skew target, use set_clock_tree_options -target_skew command. • To specify
Balancing Skew Between Different Clock Trees • create_clock_balance_group -name group1 -objects [get_clocks {clk1 clk2}] •
Implementing Multisource Clock Trees • A multisource clock tree is a custom clock structure that has more tolerance to on-ch
Regular Multisource Clock Tree

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