Modeling and Simulation ITWG

Jürgen Lorenz – Fraunhofer IISB – Chairperson M&S ITWG

ITWG/TWG Members
H. Jaouen, STM-F W. Trybula, Trybula Foundation
W. Molzer, Infineon V. Singh, INTEL
B. Huizing, NXP C. Mouli, Micron
J. Lorenz, Fraunhofer IISB V. Moroz, SNPS
+ 8 more TWG members + 2 more TWG members

T. Kunikiyo, RENESAS T.C. Lu, Macronix

M. Kimura, SONY C.S. Yeh, UMC
Japanese TWG 14 industrial + 2 more TWG members
+ 4 academic members
J. Choi, Hynix
K. Lee, Samsung
W.-Y. Jung, Dongbu
+ 2 more TWG members
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 2008 Modeling & Simulation SCOPE & SCALES
Modeling Overall Goal
• Support technology development and optimization
• Reduce development times and costs

Equipment related IC-scale

• Equipment/Feature scale Modeling • Circuit Elements Modeling
• Lithography Modeling • Package Simulation

• Numerical Methods
• TCAD for Design, Manufacturing and Yield
• Materials Modeling

Feature scale
• Front End Process • Interconnects and Integrated
Modeling Passives Modeling
• Device Modeling ITRS Winter Public Conference, December 9, Seoul, Korea 2
 Key Messages (I)
• Mission of Modeling and Simulation as cross-cut topic:
Support areas covered by other ITWGs
 Continued in-depth analysis of M&S needs of other ITWGs, based on
documents + inter-ITWG discussions – holds also for 2008
 Strong links with ALL ITWGs – see also crosscut texts in 2007 ITRS
• Modeling and simulation provides an ‘embodiment of knowledge and
understanding’. It is a tool for technology/device development and
optimization and also for training/education
• Technology modeling and simulation is one of a few methods that can
reduce development times and costs:
- 2008 major action on assessment of industrial use of TCAD and
reduction of development times and costs in best-practice cases

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 Key Messages (II)
• Art of modeling:
- Combine dedicated experiments & theory to reveal physical mechanisms
& extract parameters
- Find appropriate trade-off between detailed physical simulation (CPU
and
memory costly) and simplified but physically appropriate approaches
• Accurate experimental characterization methods are essential
• Reliable experimental reference data required on all levels – profiles,
electrical data, ….. – must partly be provided e.g. by device makers!
• Further growing importance of atomistic/materials/hierarchical/multilevel
simulation - appropriate treatment of nanostructures
• Ongoing invitation for extended participation
- also include suppliers (equipment and software)

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 Example for Success Cases (I)
NOR Flash Reliability: Contact-Gate Leakage

Requirements met during simulation:

• Accurate 3D description of memory cell
morphology
• Leakage through non-planar multi-layer
dielectric stack
• 3D non-local tunneling model to account
for local curvature radii
• Floating Gate charging during measurement
Source: STMicroelectronics Agrate
(IRPS 2007)
Main results: 1,E-10

• Sound interpretation of physical 1,E-11 exp_-30nm

1,E-12 exp_standard
mechanisms involved 1,E-13
sim_-30nm
sim_standard
• Lateral trap-assisted conduction dominates for 1,E-14

aggressively scaled contact-gate distance Ig(A)

1,E-15 `

1,E-16
• Guidelines for reliable scaling of NOR cell 1,E-17

1,E-18

1,E-19
-30,0 -25,0 -20,0 -15,0 -10,0 -5,0 0,0
Vg(V)

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 Examples for Success Cases (II)
SRAM critical yield evaluation based on comprehensive physical / statistical
modeling, considering anomalous non-Gaussian intrinsic transistor fluctuations

VLSI2007, 3A-1 M. Miyamura et. al.,NEC

Typical atomistic process simulation incorporating random discrete
dopant atoms and LWR as the source of intrinsic fluctuation

Typical examples of large-Vth- Vth distribution Vth distribution

deviation with almost identical Ion DIBL degradation for shorter Lg showing non-Gaussian tail

Atomistic-3D-TCAD predicts the non-Gaussian Vth-distribution

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 Basic Approach and Focus of 2008 Work
1) Detailed cross-cuts worked out since 2003 – regularly updated together
with other ITWGs – continued in 2008 as input to table update and
preparatiom for 2009
2) Detailed revision of M&S tables based on state-of-the-art & cross-cut
requirements – several details traced but shifted to 2009 text
3) Major action on assessment of use of TCAD in companies:
• WWW questionnaire worked out and distributed to industrial TCAD
users (NOT to developers!)
• About 140 replies received
• Results has been used for update of cost reduction estimate & as input
to 2009 work

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 Development Time and Cost Reduction Estimate
Answers on question for average reduction of development time and costs in
success case of simulation which occurred in environment of TCAD users:

Definition different from estimate of preceding years which referred to

cost reduction potential and was based on earlier survey

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 Main Changes in 2008 Challenges
Short-term challenges:
• In challenge “Ultimate nanoscale device simulation capability”:
• New item “Treatment of individual dopant atoms and traps in (commercial)
continuum and MC device simulation”
• Item “Models for device impact of statistical fluctuations in structures and
dopant distribution” skipped because quite similar to another item
• New item “Thermal modeling for 3D ICs and assessment of modeling tools capable
of supporting 3D designs. Thermo-mechanical modeling of Through Silicon Vias
and thin stacked dies, and their impact on active device properties (stress,
expansion, keepout regions, …). “ in challenge “Thermal-mechanical-electrical
modeling for interconnects and packaging”
Long-term challenges:
• Challenge “Nano-scale modeling for Emerging Research Devices including
Emerging Research Materials” extended to also include interconnects. Additional
item added on “Modeling impact of geometry, interfaces and bias on transport for
carbon-based nanoelectronics” to second item.
General: Some changes in the details of the issues (blue/red in viewfoils)

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 2008 Short-Term Difficult Challenges- so far no changes compared to 2007
Lithography Simulation including EUV
Needs
• Experimental verification and simulation of ultra-high NA vector
models, including polarization effects from the mask and the Example (Fraunhofer IISB): Large-area
imaging system rigorous simulation of optical lithography
• Models and experimental verification of non-optical immersion
lithography effects (e.g. topography and change of refractive index Mask layout
(dark-blue = Cr
distribution) absorber)
• Simulation of multiple exposure/patterning
• Multi-generation lithography system models Mask scale
• Simulation of defect influences / defect printing = 4 times
• Optical simulation of resolution enhancement techniques including wafer scale

combined mask/source optimization (OPC, PSM) and including

extensions for inverse lithography
• Models that bridge requirements of OPC (speed) and process
development (predictive) including EMF effects and ultra-high NA
500 1000 1500 2000 2500
effects (oblique illumination) (nm) High resolution
aerial image
• Predictive resist models (e.g. mesoscale models) incl. line-edge 500 computed with
roughness, etch resistance, adhesion, mechanical stability, and 1000
[Link]
(Waveguide +
time-dependent effects in multiple exposure new Imaging: 5.4
• Resist model parameter calibration methodology (including kinetic 1500
h on one CPU
and transport parameters) 2000
with 2.8 GHz.
Additionally,
• Simulation of e-beam mask making 2500 efficient
• Simulation of direct self-assembly of sublitho patterns (nm) parallelization
• Modeling lifetime effects of equipment and masks possible ).

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 2008 Short-Term Difficult Challenges – changes from 2007 in blue
Front-End Process Modeling for Nanometer Structures
Needs
• Coupled diffusion/activation/damage/stress models
and parameters incl. SPER and millisecond
processes in Si-based substrate, that is, Si, SiGe:C,
Ge, GaAs, SOI, epilayers and ultra-thin body
devices, taking into account possible anisotropy in
thin layers
• Modeling of epitaxially grown layers: Shape,
morphology, stress
• Modeling of stress memorization (SMT) during
process sequences
• Characterization tools/methodologies for ultra-
shallow geometries/junctions, 2D low dopant level,
and stress
• Modeling hierarchy from atomistic to continuum
for dopants and defects in bulk and at interfaces
• Efficient and robust 3D meshing for moving
boundaries
• Front-end processing impact on reliability
Source: P. Pichler et al. (FhG-IISB), Defect and
Diffusion Forum 258-260, 510 (2006)
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 2008 Short-Term Difficult Challenges
Integrated Modeling of Equipment, Materials, Feature Scale Processes
and Influences on Devices – no changes compared to 2007
Needs
• Fundamental physical data ( e.g. rate constants, cross
sections, surface chemistry for ULK, photoresists and
high-k metal gate); reaction mechanisms (reaction
paths and (by-)products, rates ...) , and simplified but
physical models for complex chemistry and plasma
reaction Feature scale
simulation of
• Linked equipment/feature scale models (including
sputter etching:
high-k metal gate integration, damage prediction)
Initial geometry
• Removal processes: CMP, etch, electrochemical (top),
polishing (ECP) (full wafer and chip level, pattern simulation for
dependent effects) 300 mTorr
• Deposition processes: MOCVD, PECVD and ALD, (middle) and 3
electroplating and electroless deposition modeling mTorr (bottom).
• Efficient extraction of impact of equipment- and/or
process induced variations on devices and circuits,
(From Fraunhofer
using process and device simulation IISB)

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 2008 Short-Term Difficult Challenges
Ultimate Nanoscale Device Simulation Capability – changes from 2007 in blue/red
Needs
• Methods, models and algorithms that contribute to
prediction of CMOS limits
• General, accurate, computationally efficient and robust
quantum based simulators incl. fundamental parameters
linked to electronic band structure and phonon spectra
• Models and analysis to enable design and evaluation of
devices and architectures beyond traditional planar CMOS
• Models (incl. material models) to investigate new
memory devices like MRAM, PCRAM/PRAM, etc
• Gate stack models for ultra-thin dielectrics
• SKIPPED (because quite similar to next item): Models for device
impact of statistical fluctuations in structures and dopant distributions
• Efficient device simulation models for statistical
fluctuations of structure and dopant variations and efficient
r ain
use of numerical device simulation to assess the impact of d
variations statistics on statistics of device performance
• Physical models for novel materials, e.g. high-k stacks, Ge
and compound III/V channels ….: Morphology, band
structure, defects/traps, …. u rce
• Treatment of individual dopant atoms and traps in so courtesy
courtesy Infineon / TU Munich
Infineon / TU Munich
(commercial) continuum and MC device simulation
• Reliability modeling for ultimate CMOS
• Physical models for stress induced device performance
Lattice temperatures in device
Source: Infineon / ESSDERC 2006

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 2008 Short-Term Difficult Challenges
Thermal-Mechanical-Electrical Modeling for
Interconnects and Packaging – changes from 2007 in blue/red
Needs
• Model thermal-mechanical, thermodynamic and electrical
properties of low-k, high-k and conductors for efficient on-chip and
off-chip incl. SIP layout and and wafer level packages, including
power management, and the impact of processing on these
properties especially for interfaces and films under 1 micron
• Thermal modeling for 3D ICs and assessment of modeling
tools capable of supporting 3D designs. Thermo-mechanical
modeling of Through Silicon Vias and thin stacked dies, and
their impact on active device properties (stress, expansion,
keepout regions, …).
• Model effects which influence reliability of packages and courtesy TU Vienna / IST project MULSIC

interconnects incl. 3D integration (e.g. stress voiding,

Temperature distribution in
electromigration, fracture, dielectric breakdown, piezoelectric
effects) an interconnect structure
• Models to predict adhesion on interconnect-relavant interfaces
(homogeneous and heterogeneous)
• Simulation of adhesion and fracture toughness characteristics for
packaging and die interfaces
• Models for electron transport in ultra fine patterned interconnects

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 2008 Short-term Difficult Challenges
Circuit Element and System Modeling for High Frequency (up to 160 Ghz) Applications
- No change from 2007
R gate

g1
gate

Needs No series resistance

No DIBL, +
V T1
• Supporting heterogeneous integration (SoC+SiP) by enhancing
C gso
No static feedback
_
C gdo

No overlap capacitance
CAD-tools to simulate mutual interactions of building blocks, source
g2
drain
interconnect, dies and package: s1 s2 s3 s4 s8 s9 s10 d1

R source R drain
- possibly consisting of different technologies, C jun,s
b1
C jun,d
R bulk, central
- covering and combining different modelling and simulation
levels as well as different simulation domains R bulk, source bulk R bulk, drain

• Scalable active component circuit models including non-quasi-

static effects, substrate noise, high-frequency and 1/f noise,
temperature and stress layout dependence and parasitic coupling
• Scalable passive component models for compact circuit simulation,
including interconnect, transmission lines, RF MEMS switches, …
• Physical circuit element models for III/V devices
• Computer-efficient inclusion of variability including its statistics
(including correlations) before process freeze into circuit modeling,
treating local and global variations consistently
• Efficient building block/circuit-level assessment using
process/device/circuit simulation, including process variations
(From Philips)

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2008 Difficult Challenges < 22 nm

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 2008 Requirement Tables
Only some general remarks here:
• Continued trend to delay items: Necessary research could not be done due to lack of
resources (research funding)
• Many changes in technical details included
• Table continues to contain some items in “zebra” colour - according to ITRS guidelines:
“Limitations of available solutions will not delay the start of production. In some cases,
work-arounds will be initially employed. Subsequent improvement is expected to close
any gaps for production performance in areas such as process control, yield, and
productivity.“
 This means for simulation: It can be used, but with more calibration,
larger CPU time/memory, less generality than in the end required ...
• Red here means “Solution not known, but this does not stop manufacturing”

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2008 Short-Term Requirements

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2008 Short-Term Requirements (cont.)

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More details given in tables & ITRS text

Thank you

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