Chapter 2_Lecture 6
RISC Vs. CISC
Processor design
The time taken by a processor to complete
a program can be determined by three
factors:
• The number of instructions in the
program,
• The average number of clock cycles
required to execute an instruction, and
• The clock cycle time
RISC vs. CISC
RISC CISC
Reduced Instruction Set Computer Complex Instruction set
Computer
Uses simple instruction Uses complex instruction
Operands are assumed to be in Operands can be in registers or
processor registers i.e. Not in memory
memory
Only load/store instructions can
access memory
Simple to design Complex to design
Fixed instruction size Variable instruction size
Usually doesn’t use micro- Typically uses a micro-program
program
Long program length Fewer instructions needed to
specify the algorithm
Lower power consumption Higher power consumption
Cont…
Examples
Intl:80x86 CISC Machines
Motorola: 680x0
Sun: Sparc
Silicon Graphics: MIPS
HP: PA-RISC
RISC Machines
IBM: PowerPC
Compaq: Alpha
Hybrid CISC-RISC
• Up until the mid 1990s, processor designers
were split into two opposing camps
• One side supporting CISC designs due to its
low burden on compiler developers and wide
availability of existing software
• The other camp supported RISC designs
because of its simplicity and efficiency
• However, the CISC vs. RISC debate has now
died down as contemporary processor
designers realize that RISC designs might
benefit from the addition of some CISC
characteristics and vice-versa
CISC-RISC hybrid
• Today, most CISC processors are based on hybrid
CISC-RISC architectures
• These designs use a decoder to convert CISC
instructions into RISC instructions before
execution. They are then processed by a RISC
core, which performs a few basic instructions very
quickly
• Having a RISC core is advantageous because it
allows performance enhancing features, such as
pipelining and branch prediction
• Popular examples of hybrid designs include the
Pentium and Athlon family of processors. These
processors are compatible with software written for
their CISC predecessors yet perform competitively
against processors based on RISC designs