ELE5PRB
Adam Console
Department of Engineering
SEMS
2015
Revised and Presented by Quang Vu
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Altium Designer
Topics (week 5)
Schematics
̶ Drawing
̶ Flow direction
̶ Net list generation
̶ Lab Test (12%) (September 7 to 12 - week 7)
o You will be given a printout of a generic circuit that you will have to draw
schematic for in Altium and submit via LMS.
o 1hr exam conditions.
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Topics (week 6)
PCB
̶ Design for production
o Minimum track widths
o Annulus width and hole sizes
o Component spacing
̶ 2 layer PCB
o Top bottom layer
o Keep out layer
o Polygon pour
o Mechanical mounting holes
̶ Multi layer PCB Assignment
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(10%) (Due Monday 2pm September 21 - week 9)
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Topics (week 7)
PCB (cont.)
̶ Track thickness calculations
̶ 2 layer PCB
o Polygon pour
» Ground layer
» VCC + signal layer
̶ Work on your multi layer PCB Assignment
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Basic components
̶ Resistors
̶ Capacitors
̶ Inductors
̶ Diodes
̶ Transistors (NPN, PNP)
̶ Opamps
̶ Logic gates
̶ Speakers
̶ Connectors (plugs, sockets)
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Good schematic habits
Circuit Flow
̶ Signals progress left to right (where possible)
Good Bad
Repeating or large circuits
̶ Use “sheet symbols” and
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“sheet entries” to simplify
Your circuits.
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Netlist
Is a list of components and their footprints, value….
Pins/ports interconnections
Bullet level 3
Body text
[ [
C1 Q1
TO-92A ( (
RAD-0.3
2N3904 VCC NetC2_1
Cap
] Q1-3 C2-1
]
R1-2 Q1-1
[ [ Designator ) R3-2
R1 )
C2
RAD-0.3
Cap
AXIAL-0.3
Res1 Footprint
(
NetC1_1 ( Net Connection
] C1-1 NetC2_2
]
[ [ Component
J1-1
)
C2-2
LS1-1 Component(s) in the above Net
R2 )
J1
JACK/6-V2 AXIAL-0.3
Res1
Description (
NetC1_2 (
Phonejack2
] C1-2 GND
]
Q1-2 J1-5
R1-1
[ [ CRICOS Provider 00115M LS1-2
R3 R2-2 R2-1
LS1
AXIAL-0.3 ) R3-1
PIN2
Res1 )
Speaker
] ]
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Schematic design demonstration in Altium Designer (15mins)
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(Pay attention and take notes because we will do this in the LAB!)
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Preview of next week:
PCB design demonstration in Altium Designer (15mins)
Convert the circuit schematic below into a 2 Layer PCB with:
GND plane on the top layer,
Tracks on the bottom layer,
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(Pay attention because we will do this in the lab next week!)
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PCB design procedure
IPC 2221
Import for beginners:
Track thickness calculation (Section 6.2)
Board layout design (Section 3.6)
Track lengths (Section 6.1)
Component placement and orientation (Section 8.1)
Electrical clearance (Table 6-1)
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PCB design procedure for your Lab and Assignment.
̶ Generate a Netlist and check it!
o Footprints
o Values
o Designators
o Connections
̶ Limit your board size to A1 (IPC 2221 table 5-1) (60mm x 80mm)
o Hint: work in landscape (80mm x 60mm) because it better fills your screen
̶ Import changes from your project
o Delete the Room (you will use the room function in later years)
̶ Move and rotate your components
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PCB design procedure for your Lab and Assignment.
̶ Move and rotate your components
o Limit the number of nets/tracks that cross over each other
o Place your components close to each other,
» Remember you should leave enough space between components so
that they can be easily soldered.
o For big circuits:
» Section off blocks of your circuit and work on them individually eg.
Power supplies, comms, µC, sensors…
̶ Location, Location, Location
o Component to component
o Component to board
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o Power supply to circuit
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Track thickness equation
I=kΔT0.44A0.725
Where:
I = Current (Amps)
A = Cross sectional area (mils2)
ΔT = Temperature rise above ambient (⁰C)
K = 0.048 of outside layers (0.024 for inner layers)
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(Images: IPC2221 )
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Track thickness equation
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(Images: IPC2221 )
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Track thickness example
Calculate the external layer track width in mm for the following conditions:
I=kΔT0.44A0.725 , I = 3A, ΔT = 20⁰C, 2oz copper
A = 48.695mil2 (0.0314mm2)
Width = 17.4mil (0.442mm)
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(Images: IPC2221 )
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Track resistance
Calculate the resistance of the track with a length of 100mm
pcopper= 1.6x10-8Ωm (1.6x10-5Ωmm) @20⁰C
A = 48.695mil2 (0.0314mm2)
Width = 17.4mil (0.442mm)
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Thank you
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