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ARM Assembly Registers Overview

The document contains 28 figures and 9 tables describing ARM architecture concepts such as registers, memory allocation, instruction execution, addressing modes, and the Keil uVision integrated development environment. It provides information on data types, general purpose registers, the arithmetic logic unit, load and store instructions, the current program status register, directives, and big and little endian conventions.

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Pepe Campos
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0% found this document useful (0 votes)
102 views37 pages

ARM Assembly Registers Overview

The document contains 28 figures and 9 tables describing ARM architecture concepts such as registers, memory allocation, instruction execution, addressing modes, and the Keil uVision integrated development environment. It provides information on data types, general purpose registers, the arithmetic logic unit, load and store instructions, the current program status register, directives, and big and little endian conventions.

Uploaded by

Pepe Campos
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

Figure 2- 1: ARM Registers Data Size

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 2: ARM Registers

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 3: ARM Registers and ALU

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Table 2- 1: ALU Instructions Using GPRs

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Table 2- 2: On-chip Memory Size for some ARM Chips

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 4: An Example of ARM Memory Allocation

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2-5: Executing the LDR Instruction

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2-6: Executing the STR Instruction

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 7: Executing the LDRB Instruction

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 8: Executing the STRB Instruction

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 9: Executing the LDRH Instruction

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Table 2- 3: Unsigned Data Range in ARM and associated Load Instructions

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 10: Executing the STRH Instruction

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Table 2-4: Unsigned Data Range in ARM and associated Store Instructions

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 11: CPSR (Current Program Status Register)

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Table 2- 5: Flag Bits Affected by Different Instructions

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Table 2- 6: ARM Branch (Jump) Instructions Using Flag Bits

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Table 2- 7: Some Widely Used ARM Directive

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Table 2- 8: Some Widely Used ARM Memory Allocation Directives

ARM Assembly Language Programming & Architecture by Mazidi, et al.


 
Table 2- 9: Unsigned Data Range in ARM and associated Instructions

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 12: Memory Dump for Program 2-3A

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 13: Steps to Create a Program

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 14: Sample of an Error Message

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 15: Sample of a Map File

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 16: Sample of a List File for ARM

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 17: ADD Instruction Formation

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 18: SUB Instruction Formation

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 19: General Formation of Data Processing Instructions

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 20: Branch Instruction Formation

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 21: Harvard vs. Von Neumann Architecture

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 22: ARM Program Memory Contents for Program 2-4 List File (Little Endian)

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 23: Big Endian Convention

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 24: Register Addressing Mode

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 25: Immediate Addressing Mode

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 26: Register Indirect Addressing Mode

ARM Assembly Language Programming & Architecture by Mazidi, et al.


Figure 2- 27: Keil uVision Screenshot
ARM Assembly Language Programming & Architecture by Mazidi, et al.
Figure 2- 28: Keil uVision Screenshot

ARM Assembly Language Programming & Architecture by Mazidi, et al.

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