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Dataflow Modeling in Verilog

The document discusses dataflow modeling in Verilog. It explains that dataflow modeling uses continuous assignment statements to describe architectures where changing the value of one data item automatically triggers recalculation of dependent data items. Signals are continuously assigned values using the assign keyword. Delays can be specified to simulate real-world circuit behavior more accurately. Common examples like multiplexers and decoders are demonstrated using dataflow modeling concepts.

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Himanshu Meena
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29 views10 pages

Dataflow Modeling in Verilog

The document discusses dataflow modeling in Verilog. It explains that dataflow modeling uses continuous assignment statements to describe architectures where changing the value of one data item automatically triggers recalculation of dependent data items. Signals are continuously assigned values using the assign keyword. Delays can be specified to simulate real-world circuit behavior more accurately. Common examples like multiplexers and decoders are demonstrated using dataflow modeling concepts.

Uploaded by

Himanshu Meena
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

Dataflow Modelling

1
Dataflow Verilog Modeling
 A dataflow description is based on function rather than structure.

 Describes an architecture where a change in value of a data item


automatically triggers the recalculation of all other data dependent
upon it.

 A dataflow uses a number of operators that act on operands to


produce the desired function
 Boolean equations are used in place of logic schematics.

In dataflow models, signals are continuously assigned values using


the assign keyword.
Dataflow Modeling

 Uses continuous assignment statement


 Format: assign [ delay ] net = expression;
 Example: assign sum = a ^ b;

 Delay: Time duration between assignment from RHS to LHS


 To simulate a circuits real world behavior it is important
that propagation delays are included.
 All continuous assignment statements execute concurrently
 Order of the statement does not impact the design

3
Continuous Assignment

4
Rules
 The left hand side of an assignment must always be a scalar or vector net
 It cannot be a scalar or vector register.

 The operands on the right-hand side can be registers or nets.

 Continuous assignments are always active.

 The assignment expression is evaluated as soon as one of the right-hand-side


operands changes and the value is assigned to the left-hand-side net.

 Delay values can be specified for assignments in terms of time units. Delay values
are used to control the time when a net is assigned the evaluated value

5
Dataflow Modeling (cont.)
 Delay can be introduced
 Example: assign #2 sum = a ^ b;
 “#2” indicates 2 time-units
 No delay specified : 0 (default)

 Associate time-unit with physical time


 `timescale time-unit/time-precision
 Example: `timescale 1ns/100 ps
 Timescale
`timescale 1ns/100ps
 1 Time unit = 1 ns
 Time precision is 100ps (0.1 ns)
 10.512ns is interpreted as 10.5ns 6
2x1 MUX example
module generate_mux (data,select,out)
input [0:7] data;
input [0:2] select;
output out;
asssign out=data[select];
endmodule 1 bit Mux

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4-1 Multiplexer
// 4-to-1 Line Multiplexer: Dataflow Verilog Description (Boolean)
module multiplexer_4_to_1_df_v(S, I, Y);
input [1:0] S;
input [3:0] I;
output Y;

assign Y = (~ S[1] & ~ S[0] & I[0])| (~ S[1] & S[0] & I[1])
| (S[1] & ~ S[0] & I[2]) | (S[1] & S[0] & I[3]);
endmodule
Decoder example
module dec2_4 (a,b,en,y0,y1,y2,y3) 
input a, b, en;
output y0,y1,y2,y3;
assign y0= (~a) & (~b) & en;
assign y1= (~a) & b & en;
assign y2= a & (~ b) & en;
assign y3= a & b & en;
end module

9
“
Thankyou

10

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