ATPG OBSERVATION
ATPG OBSERVATION
Coverage analysis
Pattern counts
Cycle counts
Type of patterns
Hierarchical reports
Statistical reports
Scan chain and clk to q interconnection information
COVERAGE ANALYSIS
[Link] COVERAGE : Test coverage is a measure of test quality . It is the percentage of
faults detected from among all testable faults.
Test coverage = Detectable fault
Testable faults
2. FAULT COVERAGE : Fault coverage consists of the percentage of faults detected from
among all faults that the test pattern set tests it treats untestable faults the same as undetected
faults.
Fault coverage = Detectable fault
Testable faults + Untestable faults
PATTERN COUNTS
The additional information that is difficult to access in the Verilog (or VHDL)
testbenches can be found in other pattern formats. When comparing different pattern
formats, it is useful to know that the pattern numbering is the same in all formats.
Different types of format include :
[Link] : The ASCII pattern format is the most readable of the pattern format The values
in the ASCII patterns are the values that are shifted through the scan in and scan out pins
of the design.
[Link](Waveform generation language) : The WGL patterns is particularly useful when
analysing how the timeplates are applied into the test pattern set.
[Link] : The Verilog patterns uses the timeplates described in the Enhanced Procedure
File. The pattern type and time plate type used for a specific cycle is indicated by some of
the bits in the vectors.
4 : STIL
5 : BD
CYCLE COUNTS
• Chain clock balancing
• Shift cycles
• SI counts, shift counts
HIERARICAL REPORTS
• Chain blockage reports.
STATISTICAL REPORTS
• It is similar to coverage reports
• It contains DI, DS, unused, TE, RE, blocked, ATPG un-testable
TYPES OF PATTERNS
1. BASIC PATTERNS /SCAN PATTERNS : The tool generates basic scan patterns by
default. A scan pattern contains the events that force a single set of values to all scan
cells and primary inputs (force_pi), followed by observation of the resulting responses
at all primary outputs and scan cells (measure_po).
2. SEQUENTIAL PATTERNS : The ATPG tool’s clock sequential pattern type handles
limited sequential circuitry, and can also help in testing designs with RAM.
[Link] SEQUENTIALL PATTERNS : To propagate fault effects through RAM, and to
thoroughly test the circuitry associated with a RAM, the tool generates a special type of
pattern called RAM sequential. RAM sequential patterns are single patterns with multiple
loads, which model some sequential events necessary to test RAM operations.
CHAIN BLOCKAGE
ATPG issue 1:
• If clock is not pulsing at one flop the will not pass to the rest of the flops causes
violation. Tool shows T3 violation
To Overcome
add_0/1 clocks_(path cell instance name) -internal
ATPG issue 2:
• LIB file missing,
• The module present in the netlist but missing in library cause library missing tool
through error
To Overcome:
Define proper library file to the module.
ATPG issue 3 :
• Tool might miss some of the flops, when scan chain is not chained properly.
• Its our mistake chain blockage will [Link], for this warning, errors will be in
scan insertion, we should fix properly, it should not have any warnings or errors.
To Overcome:
Check Pin like SE,CLK,RESET and fix it.
ATPG issue 4 :
• Here, some of the clocks is not known, where to feed the data, so this cause chain
blockage.
To Overcome:
Should check with RTL.
TETRAMAX FLOW
Unix> tmax-shell-64
This will invoke Tetramax ATPG tool in shell mode
BUILD-T>set_messages -log logs/[Link] –replace
Write out a log file using the above command
BUILD-T>set_build -black_box adc0808
Defile the module adco808 as black box
BUILD-T> read_netlist /tools/libraries/28nm/SAED32_EDK/lib/pll/verilog/PLL.v-library
Read all libraries needed to run ATPG
BUILD-T>read_netlist inputs/dig_top_scan_inserted.v
Read Scan inserted netlist Build fault model using
BUILD-T>run_build_model ABC
Run build for the particular model
DRC-T>run_drc input/ABC_scan_inserted.spf
Read SPF file
TEST-T>set_faults-model Stuck
Set fault model to stuck
TEST-T>add_faults -all
Reports fault summary
TEST-T>report_faults –summary
Gives the all AU fault list
TEST-T> set_atpg-patterns 100
Tool generate only 100 patterns
TEST-T> run_atpg
Tool will generate the patterns
Writing out the generated patterns in STIL format
TEST-T> write_patterns outputs/ABC_parallel.stil -format stil -parallel
Writing out serial patterns
TEST-T> write_patterns outputs/[Link] -format stil –serial
Writing out chain patterns
THANK YOU
