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ARM Coprocessor Interface Overview

The document discusses the ARM coprocessor interface. It aims to help students understand the coprocessor architecture, handshake outcomes, and ARM7TDMI coprocessor interface. Key points include that coprocessors use a load-store architecture and can have up to 16 private registers, the ARM and coprocessor use handshake signals like CPI, CPA, and CPB to coordinate instruction execution, and data transfers are controlled through these signals with the ARM providing the initial address and coprocessor determining transfer length.

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darshan gopal
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152 views8 pages

ARM Coprocessor Interface Overview

The document discusses the ARM coprocessor interface. It aims to help students understand the coprocessor architecture, handshake outcomes, and ARM7TDMI coprocessor interface. Key points include that coprocessors use a load-store architecture and can have up to 16 private registers, the ARM and coprocessor use handshake signals like CPI, CPA, and CPB to coordinate instruction execution, and data transfers are controlled through these signals with the ARM providing the initial address and coprocessor determining transfer length.

Uploaded by

darshan gopal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

EMBEDDED SYSTEMS (15EC503)

– UNIT 3
BY
J P SHRI THARANYAA M.E,(Ph.D)
AP(Sr.G)/ECE
General Objective:

• The students will be able to understand the ARM coprocessor


interface.

Specific Objectives:

The students will be able to

1. Understand the coprocessor architecture. (R,C)

2. Determine the handshake outcomes. (E,C)

3. Explain the ARM7TDMI coprocessor interface. (U,P)

4. Determine the data transfers and pre-emptive execution in


coprocessor. (E,C)
ARM CO-PROCESSOR INTERFACE
COPROCESSOR ARCHITECTURE
• The important features of coprocessor architecture are:
– Support up to 16 logical coprocessor.
– Each coprocessor can have up to 16 private registers of any
reasonable size; they are not limited to 32 bits.
– Coprocessors use load- store architecture.
• In simpler ARM cores, the coprocessors are introduced as a
separate component since it is interfaced in board level.
• For higher performance ARM restrict coprocessor interface
since board level interfacing is very difficult.
ARM7TDMI COPROCESSOR INTERFACE
• Interfacing is based on “bus watching” technique.

• As each coprocessor instruction begins execution there is a hand-shake between the

ARM & coprocessor to confirm that they both are ready to execute it.

• The handshaking signals are:

– CoProcessor Instruction(cpi): (ARM to all coprocessor)

It indicates that ARM has identified a coprocessor instruction and wishes to

execute it.

– CoProcessor Absent(cpa):(coprocessor to ARM)

It tells the ARM that there no coprocessor present that is able to execute the

current instruction.

– CoProcessor Busy(cpb):(coprocessor to ARM)

It tells the ARM that the coprocessor cannot begin executing the instruction yet.
HANDSHAKE OUTCOMES
• ARM may decide not to execute it, either because it fails in the branch

shadow or because it fails its condition code test. ARM will not assert

cpi’, and the instruction will be discarded.

• ARM may decide to execute it, but no coprocessor is present(cpa

active). ARM will take undefined instruction trap & use software to

recover.

• ARM decides to execute it and coprocessor accept it, but cannot

execute it yet.(cpa- low & cpb - high). ARM will be in “busy-wait” and

stalling the instruction at this point.

• ARM decides to execute it and coprocessor accept it for immediate

execution.
DATA TRANSFER
• The ARM is responsible for generating an initial
memory address but coprocessor determines
the length of the transfer.
• ARM will continue incrementing the address
until the coprocessor signals completion.
• The cpa and cpb handshaking signals are used for
this purpose.
MIND MAP

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