DESIGN OF 16 BIT RISC
PROCESSOR
USING VERILOG HDL
MENTOR- PRESENTED BY-MUDIT KAPOOR(1609131084)
AAYUSHI VAISH(1609131004)
KEERTI RAJ(1609131067)
CONTENTS
[Link]
[Link] TO RISC
3. FEATURES OF RISC PROCESSOR
4. BLOCK DIAGRAM
5. MODULES
[Link] PERFORMED
OBJECTIVE
OUR OBJECTIVE IS TO DESIGN 16 BIT RISC PROCESSOR
USING VERILOG HDL
WE WILL IMPLEMENT-
1. DATA TRANSFER OPERATIONS
2. ARITHMETIC OPERATIONS
3. LOGICAL OPERATIONS
4. SHIFT OPERATIONS
INTRODUCTION OF RISC
The reduced instruction set computer, or RISC, is a
microprocessor CPU design philosophy that favors a smaller
and simpler set of instructions that all take about the same
amount of time to execute.
RISC Processor is based on LOAD AND STORE ARCHITECTURE
In RISC,the complexity of controller design has been overcome
with the help of operands and Opcode bits fixed in instruction
register.
FEATURES OF RISC PROCESSOR
Uniform Instruction Encoding (the op-code is always in the same bit
position in each instruction, which is always one word long), which allows
faster decoding.
A Homogeneous Register Set, allowing any register to be used in any
context and simplifying compiler design.
Simple Addressing Modes
Few Data Types supported in hardware. Some CISC machines have
instructions for dealing with byte strings. Others have support for
polynomials and complex numbers. Such instructions are unlikely to be
found on a RISC machine.
BLOCK DIAGRAM OF PROCESSOR
PROCESSOR CONSIST OF-
[Link] Logical Unit (ALU)
[Link] Unit (CU)
[Link]
MODULES
16 BIT ALU
Control Unit
16 BIT 8 Registers (Register File)
5 BIT Program Counter
16 BIT Instruction Register
16X32 Data Memory
16X32 Instruction Memory
16 BIT Data Bus
5 BIT Address Bus
HARDWARE AND SOFTWARE
REQUIREMENT
SOFTWARE:-1)XILINX 14.2
Operations Performed
1. Arithmetic (Two’s Complement) ALU operation
ADD: Rd = Rs + Rt
Operands A and B stored in register locations Rs and Rt are added and written to the
destination register specified by Rd.
SUB: Rd = Rs - Rt
Operand B (Rt) is subtracted from Operand A (Rs) and written to Rd.
2. Logical ALU operation
AND: Rd = Rs & Rt
Operand A (Rs) is bitwise anded with Operand B (Rt) and written into Rd.
OR: Rd = Rs | Rt
Operand A (Rs) is bitwise ored with Operand B (Rt) and written into Rd.
Operand A (Rs) is bitwise ored with Operand B (Rt) and written into Rd.
XOR: Rd = Rs ^ Rt
Operand A (Rs) is bitwise Xored with Operand B (Rt) and written into Rd.
NOT: Rd = ~Rs
Operand A (Rs) is bitwise inverted and written into Rd.
SLA: Rd = Rs << 1
Operand A (Rs) is arithmetically shifted to the left by one bit and written into
Rd.
SRA: Rd = Rs >> 1
Operand A (Rs) is arithmetically shifted to the right by one bit and written into
Rd. The MSB (sign bit) will be preserved for this operation.
3. Memory operations
LW: Rd = Mem[Rs]
The memory word specified by the address in register Rs is loaded into register
Rd.
SW: Mem[Rs] = Rt
The data in register Rt is stored into the memory location specified
CONCLUSION
RISC architectures are now used across a wide range of platforms, from
cellular telephones and tablet computers to some of the world's fastest
supercomputers such as the K computer, the fastest on the TOP500 list
in 2011.
.The purpose of this project was to learn digital designing using XILINX
software
and designing of RISC architecture.
REFRENCES
[1] S. Palnitkar , ‘VERILOG HDL: A Guide to Design And Synthesis’,
Sunsoft Press,Prentice Hall, 1996. [2] [Link], ‘Computer System
Architecture’, Third Edition, Thompson Press(India), Prentice Hall,2013.
[2] IIT Kharagpur,2004, Lectures on Verilog.[ONLINE] available at:
[Link]/courses/106105083/
THANK YOU !