Electronic Devices and Circuit Theory
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Field Effect Transistor (FET)
Chapter 5
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JFET Operating Characteristics
As VGS becomes more negative, the depletion region
increases.
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JFET Operating Characteristics
As VGS becomes more negative:
• The JFET experiences pinch-off at a
lower voltage (VP).
• ID decreases (ID < IDSS) even though VDS is
increased.
• Eventually ID reaches 0 A. VGS at this
point
is called Vp or VGS(off)..
Also note that at high levels of VDS the JFET reaches a breakdown situation. ID
increases uncontrollably if VDS > VDSmax.
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where ro is the resistance with VGS =0 V and rd =the resistance at a particular level of VGS.
For an n-channel JFET with ro equal to 10 k (VGS =0 V, VP =6), will result in 40 k at VGS=3V.
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Symbols
JFET symbols: n-channel p-
channel.
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Summary:
The maximum current is defined as IDSS and
occurs when VGS =0 V and VDS >=|VP|.
For gate-to-source voltages VGS less than
(more negative than) the pinch-off level, the
drain current is 0 A (ID 0 A) .
For all levels of VGS between 0 V and the
pinch-off level, the current ID will range
between IDSS and 0 A, respectively.
For p-channel JFETs a similar list can be
developed.
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The relationship between ID and VGS is defined by Shockley’s equation:
The transfer curve can be obtained using Shockley’s equation or from
the output characteristics
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Applying Shockley’s Equation
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Depletion-type
MOSFET, which happens to
have characteristics similar to
those of a JFET between cutoff
and saturation at IDSS
but then has the added feature of
characteristics that extend into
the region of opposite polarity
for VGS.
The Drain (D) and Source (S) connect to the to n-doped
regions. These n-doped regions are connected via an n-
channel. This n-channel is connected to the Gate (G) via
a thin insulating layer of SiO2.
The n-doped material lies on a p-doped substrate that
may have an additional terminal connection called
Substrate (SS).
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The fact that the SiO2 layer is an insulating layer reveals the following
fact:
There is no direct electrical connection between the gate terminal and
the channel of a MOSFET.
In addition:
It is the insulating layer of SiO2 in the MOSFET construction that
accounts for the very desirable high input impedance of the device.
The insulating layer between the gate and channel has resulted in another
name for the device: insulated gate FET or IGFET, although this label is
used less and less in current literature.
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Basic MOSFET Operation and Characteristics
VGS is set to zero volts and a voltage VDS is
applied across the drain-to-source
terminals. The result is an attraction for the
positive potential at the drain by the free
electrons of the n-channel and a current similar
to that established through the channel
of the JFET.
VGS has been set at a negative voltage
such as 1 V. The negative potential at the
gate will tend to pressure electrons
toward the p-type substrate (like
charges repel) and attract holes from the
p-type substrate (opposite charges
attract)
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D-Type MOSFET in Depletion Mode
Depending on the magnitude of the
negative bias established by VGS, a level
of recombination between electrons and
holes will occur that will reduce
the number of free electrons in the n-
channel available for conduction.
The more negative
the bias, the higher the rate of
recombination. The resulting level of
drain current is therefore reduced with
increasing negative bias for VGS
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D-Type MOSFET in Enhancement Mode
• For positive values of VGS, the positive gate will draw additional electrons (free
• carriers) from the p-type substrate due to the reverse leakage current and establish
• new carriers through the collisions resulting between accelerating particles.
• As the gate-to-source voltage continues to increase in the positive direction, the drain
current will increase at a rapid rate for the reasons listed above.
• Due to the rapid rise, the user must be aware of the maximum drain current rating
since it could be exceeded with a positive gate voltage.
• the application of a positive gate-to-source voltage has “enhanced” the level of free
carriers in the channel compared to that encountered with VGS =0 V.
• For this reason the region of positive gate voltages on the drain or transfer
characteristics is often referred to as the enhancement region
• region between cutoff and the saturation level of IDSS referred to as the depletion
region.
• Shockley’s equation will continue to be applicable for the depletion-type MOSFET
characteristics in both the depletion and enhancement regions.
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Enhancement-Type MOSFET
• Transfer curve is not defined by Shockley’s equation
• Drain current is now cut off until the gate-to-source voltage
reaches a specific magnitude.
• current control in an n-channel device is now effected by a
positive gate-to-source voltage rather unlike n-channel JFETs
and n-channel depletion-type MOSFETs
Basic Operation and Characteristics
If VGS is set at 0 V, the absence of an n-channel will result in a
current of effectively zero amperes
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Basic Operation and Characteristics
With VDS some positive voltage,
VGS at 0 V, two reverse-biased p-
n junctions between the n-doped
regions and the p-substrate to
oppose any significant flow
between drain and source
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Basic Operation and Characteristics
positive potential at the gate will pressure the holes (since like charges repel) in
the p-substrate along the edge of the SiO2 layer to leave the area and enter deeper regions
of the p-substrate. The result is a depletion region near the SiO2 insulating layer void of
holes.
electrons in the p-substrate (the minority carriers of the material) will be attracted to the
positive gate and accumulate in the region near the surface of the SiO2 layer. The SiO2 layer
and its insulating qualities will prevent the negative carriers from being absorbed at the gate
terminal.
The level of VGS that results in the significant increase in drain current is called the
threshold voltage and is given the symbol VT.
Since the channel is nonexistent with VGS =0 V and “enhanced” by the application of a
positive gate-to-source voltage, this type of MOSFET is called an enhancement-type
MOSFET.
Both depletion- and enhancement-type MOSFETs have enhancement-type regions, but the
label was applied to the latter since it is its only mode of operation.
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As VGS is increased beyond the threshold
level, the density of free carriers in the
induced channel will increase, resulting
in an increased level of drain current.
if VGS constant and increase the level of
VDS, the drain current will eventually
reach a saturation level as occurred for
the JFET and depletion-type MOSFET.
The leveling off of ID is due to a
pinching-off process depicted by the
narrower channel at the drain end of the
induced channel
saturation level for VDS
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For levels of VGS VT, the drain current is related to the applied gate-
to-source voltage
k term is a constant that is a
function of the construction of
the device.
ID(on) and VGS(on) are the values
for each at a particular point
on the characteristics of the device
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transfer characteristics for an n-channel enhancement type MOSFET
from the drain characteristics
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Vss
• It utilizes two MOSFETs: one, QN, with
an n channel and the other, QP, with a p
channel.
• The body of each device is connected to
its source, and thus no body effect arises.
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Vss
Vss
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Vss
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In summary:
1. The output voltage levels are 0 and VDD, and thus the signal swing is the maximum
possible.
2. The static power dissipation in the inverter is zero (neglecting the dissipation due to
leakage currents) in both of its states. This is because no dc path exists between the power
supply and ground in either state.
3. A low-resistance path exists between the output terminal and ground (in the low-output
state) or VDD (in the high-output state). These low-resistance paths ensure that the
output voltage is 0 or VDD independent of the exact values of the W/L ratios or other
device parameters. Furthermore, the low output resistance makes the inverter less sensitive
to the effects of noise and other disturbances.
4. The active pull-up and pull-down devices provide the inverter with high output-driving
capability in both directions. As will be seen, this speeds up the operation
considerably.
5. The input resistance of the inverter is infinite (because IG = 0). Thus the inverter can drive
an arbitrarily large number of similar inverters with no loss in signal level. Of course, each
additional inverter increases the load capacitance on the driving inverter and slows down the
operation.
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