FETs vs.

BJTs
Similarities:
• Amplifiers
• Switching devices
• Impedance matching circuits

1
 FETs vs. BJTs
Differences:
• FETs are voltage controlled devices. BJTs are
current (IB) controlled devices.

IC is proportional to IB ID is proportional to VGS

2
 FETs vs. BJTs
Differences:
• FETs have a higher input impedance. BJTs
have higher gains.
• FETs are less sensitive to temperature
variations and are more easily integrated on ICs.

FET is unipolar device and hence, depending solely on

either electron or hole conduction.

BJT is bipolar device.

3
 The Term FETs
In FET, the electric field is established by the
charges present, which controls the conduction
path of the output circuit without the need for
direct contact between the controlling and
controlled quantities.

4
 FET Types

•JFET: Junction FET

•MOSFET: Metal–Oxide–Semiconductor FET

D-MOSFET: Depletion MOSFET

E-MOSFET: Enhancement MOSFET

5
 JFET Construction
There are two types of JFETs

•n-channel (more widely used)

•p-channel

The top of the n-type channel is

connected through an ohmic contact to
a terminal referred to as the drain (D).
The lower end of same n-type material
is connected through an ohmic contact
to a terminal referred to as the source
(S). The two p-type materials are
connected together and to the gate (G).

There are three terminals:

•Drain (D) and Source (S) are connected to the n-channel

•Gate (G) is connected to the6 two layers of p-type material
 JFET Construction
During no-bias condition, JFET has two
p-n junctions which are same as the
region of diode under no-bias
conditions.

The depletion region at each junction

unable to support conduction.

7
 JFET Operation: The Basic Idea

The source of water pressure can

be compared to the applied drain-
to-source voltage (VDS) which
establishes a flow of electrons
from the source.

The drain of water is the electron

deficiency (or holes) at the positive
pole of the applied voltage.

The gate voltage (VGS) controls the

flow of water (electrons) by
controlling the width of n-channel.

8
 JFET Operating Characteristics

There are three basic operating conditions for a JFET:

• VGS = 0, VDS increasing to some positive value

• VGS < 0, VDS at some positive value
• Voltage-controlled resistor

9
JFET Operating Characteristics

10
 JFET Operating Characteristics
Case-1: VGS=0 V and VDS has some positive value

• G and S are shorted.

• When VDS is applied, ID flows. (ID =
I S)
• The depletion region is wider near
the top of both p-type materials.
• Upper region of p-type is more
Reverse Biased & lower region is
less RB.
• Resistance of Channel is High on
Upper Region and Low at Lower
Region.
• IG=0 as p-n junction is RB.

11
 JFET Operating Characteristics: VGS = 0 V
Three things happen when VGS = 0 and VDS is increased from 0 to a more positive voltage

• The depletion region between p-gate

and n-channel increases as electrons
from n-channel combine with holes
from p-gate.

• Increasing the depletion region,

decreases the size of the n-channel
which increases the resistance of the
n-channel.

• Even though the n-channel resistance

is increasing, the current (ID) from
source to drain through the n-
channel is increasing. This is because
VDS is increasing.

12
 JFET Operating Characteristics: Saturation

As VDS is increased from 0V to a

few volts, the current will
increase according to ohm’s law.

For the region of low values of

VDS, the resistance is
essentially constant.

Any further increase in VDS does

not produce any increase in ID.
VDS at pinch-off is denoted as Vp
(pinch-off voltage).

13
 JFET Operating Characteristics: Pinch Off

If VGS = 0 and VDS is further

increased to a more positive
voltage, then the depletion
zone gets so large that it
pinches off the n-channel.

This suggests that the current

in the n-channel (ID) would
drop to 0A, but it does just the
opposite–as VDS increases, so
does ID.

14
 JFET Operating Characteristics: Saturation
At the pinch-off point:

Any further increase in VDS

does not produce any increase in ID.

VDS at pinch-off is denoted as Vp.

ID is at saturation or maximum. It is
referred to as IDSS - Drain to Source
Current with Source Shorted with
Gate.

IDSS is the maximum drain

current for a JFET when
VGS=0 V and VDS > VP
For VDS > VP the FET is acting as
Current Source

15
 Effect on JFET Cht. due to level of VGS
Case-2: VGS< 0 V and VDS has some positive value
For n-channel device, the controlling voltage VGS is
made more and more negative from its VGS =0 V.

In other words, the gate terminal will be set at

lower and lower potential levels as compared to
source.

As VGS becomes more negative, the depletion region

increases.

The result of applying a negative bias to the gate is

to reach the saturation level at a lower level of VDS.

16
 JFET Operating Characteristics
VGS Controls ID
As VGS becomes more negative:

• The JFET experiences pinch-off

at a lower voltage (VP).
• The resulting saturation level for
ID has been reduced and in fact
will continue to decrease as VGS is
made more and more negative.

• ID decreases (ID < IDSS) even

though VDS is increased.

• Eventually ID reaches 0 A. VGS at

this point is called Vp or VGS(off).

17
 JFET Operating Characteristics
VGS Controls ID
• The level of VGS that
results in ID =0 mA is
defined by VGS = Vp with
VP being a negative
voltage for n-channel
devices and a positive
voltage for p-channel
JFETs.

• On data sheet of JFET,

the pinch-off voltage is
specified as VGS(off) rather
than VP.

18
 JFET Operating Characteristics
Also note that at high levels VGS Controls ID
of VDS the JFET reaches a
breakdown situation. ID
increases uncontrollably if
VDS > VDSmax. (Breakdown
Region)

The region to the right of the

pinch-off locus is called liner
amplification region or
constant current region or
saturation region.

19
 JFET Operating Characteristics:
Voltage-Controlled Resistor
The region to the left of the pinch-
off point is called the Ohmic region
or voltage controlled resistor region.

The JFET can be used as a variable

resistor, where VGS controls the
drain-source resistance (rd) of
JFET.

As VGS becomes more negative, the

resistance (rd) increases.

ro
rd 
2
 VGS 

 1  

 VP 
r0 is the resistance with VGS=0 V
rd is the resistance at particular VGS
20
N-Channel JFET Symbol

Arrow direction Pointing in at

Gate Terminal indicates the
Direction in which IG would
flow if the Gate to Source P-
N junction are forward-
biased.

21
 p-Channel JFETS
The p-channel JFET behaves the same as
the n-channel JFET, except the voltage
polarities and current directions are
reversed.

22
 p-Channel JFET Characteristics

As VGS increases more

positively

• The depletion zone

increases
• ID decreases (ID < IDSS)
• Eventually ID = 0 A

At high levels of VDS , the JFET reaches a breakdown situation:

ID increases uncontrollably if VDS > VDSmax.

23
 JFET Transfer Characteristics
Transfer Characteristics of FET is the Plot of Drain Current versus Gate – Source
Voltage for a fixed Drain - Source Voltage, beyond Ohmic Region.

The transfer characteristic of input-to-output is not as straightforward in a JFET as

it is in a BJT.

In a BJT,  indicates the relationship between IB (input) and IC (output). Where  is

constant, IB is control variable.
I C  I B
In a JFET, the relationship of VGS (input) and ID (output) is a little more
complicated: Here IDSS and VP are Constant and VGS is Control Variable.
Transfer Characteristics Equation is called Shockley’s Equation.
2
 
 VGS 
I D  I DSS  1  
 VP 
 

24
 JFET Transfer Curve
This graph shows the value of ID
for a given value of VGS.

For decreasing values of

VGS , Transfer Curve
Grows Exponentially.

Horizontal line from the

Right side of Y Axis drawn
on Left side, Vertical Line
for VGS drawn, the
Intersection of these two
lines gives a point for
Transfer Curve.

25
 Plotting the JFET Transfer Curve
Using IDSS and Vp (VGS(off)) values found in a specification sheet, the transfer
curve can be plotted according to these three steps:

Step 1
2
 V 
I D  I DSS  1  GS 
 VP 
Solving for VGS = 0V ID = IDSS

Step 2
2
 V 
I D  I DSS  1  GS 
 VP 
Solving for VGS = Vp (VGS(off)) ID = 0A

Step 3
2
 V 
Solving for VGS = 0V to Vp I D  I DSS  1  GS 
 VP 

26
For a given IDSS and VP in Datasheet, ID can be
found for any value of VGS
Shorthand Method: Four Points using Shockley's
equation to quickly draw the transfer characteristics
curve
2
 
I D  I DSS  1  GS 
V
 

 VP 
Common FET Biasing Circuits

• Fixed – Bias
• Self-Bias
• Voltage-Divider Bias

28
 Basic Current Relationships
For all FETs:
• Device Specific Equations.
I G  0A • Do not alter so long device
I D  IS is in Active Region
• Graphical approach will be
For JFETS and D-Type MOSFETs:
used to examine the dc
analysis for FET because it
2
 V  is most popularly used
I D  I DSS  1  GS 
 VP  rather than mathematical
approach
For E-Type MOSFETs:
I D  k ( VGS  VT ) 2

29
 Fixed Bias Configuration
The configuration includes the ac levels Vi and Vo and
the coupling capacitors.
The resistor is present to ensure that Vi appears at the
input to the FET amplifier for the AC analysis.
 Fixed Bias Configuration
For the DC analysis,
Capacitors are open circuits
IG  0A and VRG  I G RG  (0 A) RG  0V
The zero-volt drop across RG permits replacing RG by a short-circuit
 Fixed Bias Configuration

Investigating the input loop

IG=0A, therefore
VRG=IGRG=0V
Applying KVL for the input loop,
-VGG-VGS=0
VGG= -VGS
It is called fixed-bias configuration
due to VGG is a fixed power supply
so VGS is fixed.
The resulting current, by Shockley’s
Equation,

VGS 2
ID  IDSS(1 )
VP
 Fixed Bias Configuration
• Using Graphical Method Draw the Graph of
Transfer Characteristics.
• The fixed level of VGS has been
superimposed as a vertical line a VGS=-VGG
• At any point on the vertical line, the level of
VG is –VGG the level of ID must simply be
determined on this vertical line.
• The point where the two curves intersect is
the common solution to the configuration –
commonly referrers to as the quiescent or
operating point.
• The quiescent level of ID is determine by
drawing a horizontal line from the Q-point to
the vertical ID axis.

33
 Fixed-Bias Configuration
Output Loop
VDS  VDD  I D RD VDS  VD  VS
VS  0V
VD  VDS VGS  VG  VS
VG  VGS
VGS  VGG
Example: For a given Fixed Bias Configuration,
Determine VGSQ, IDQ, VDS, VD, VG and VS

Graphical Approach can be applied from transfer

curve and vertical line for fixed bias
Exercise: Determine IDQ, VGSQ, VDS, VD, VG and VS
 Self-Bias Configuration
The self-bias configuration eliminates the need for two dc
supplies.
The controlling VGS is now determined by the voltage across
the resistor RS.

37
 Self-Bias Configuration
Gate Resistor RG does not affect the bias
because it has essentially no voltage drop
across it; Hence VG = 0;

Mathematical Approach

VS = ISRS = IDRS
VGS = VG – VS = 0 – IDRS
VGS = – IDRS
VD = VDD – IDRD
VDS = VD – VS
 VGS 
2
VDS = VDD – IDRD – IDRS
ID  I DSS 1   VDS = VDD – ID (RD + RS)
 VP 
2
 I D RS 
ID  I DSS 1  
 VP 
I D  K1 I D  K 2  0
2
38
 Self-Bias Configuration –Q Point

Determine ID for a desired value of VGS or vise versa.

For a desired value of VGS , ID can be determined in either

of two ways:

- Using Transfer Characteristic Curve

2
 V 
- Using Equation I D  I DSS  1  GS 
 VP 

(VP and IDSS can be obtained from data sheet of JFET)

39
Self-Bias Configuration – Finding RS for
desired Q Point

40
Self-Bias Configuration – Finding RS for
desired Q Point

41
 Self-Bias Configuration
• Graphical approach to get Q Point for Given Value
of Rs
– Draw the device transfer characteristic
– Draw the network load line
VGS   I D RS
• Use to draw straight line.
I D  0, VGS  0
• First point,
• Second point, any pointI from ID = 0 to ID = IDSS. Choose
ID  DSS
then
2
I DSS RS
VGS  
2

– the quiescent point obtained at the intersection of the

straight line plot and the device characteristic curve.
– The quiescent value for ID and VGS can then be
determined and used to find the other quantities of
interest.
Self-Bias Configuration
• Graphical approach
 Self-Bias Calculations
For the indicated loop, VGS   I D R S

44
 Self-Bias Calculations
iD (mA)

VGS   I D R S iDSS = 10

When ID = 0
5.07

When ID = IDSS
0

So IDQ = 5.07 and

VGSQ = -4.7
45
 Self-Bias Calculations

Determine Q Point

46
Example: Determine VGSQ, IDQ,VDS,VS,VG and VD.
• Take ID = 0 mA and ID=4 mA
• Calculate VGS= - IDRS
• Draw Load Line Connecting two points.
• Use Shorthand Method and draw transfer
curve.
• Intersection of Transfer Curve and Load Line
gives the Q Point for the given network.
 Voltage-Divider Bias
• IG = 0 A
• ID responds to changes in VGS.
• The arrangement is the same as BJT but the DC analysis is different
• In BJT, IB provide link to input and output circuit, in FET VGS does the
same
 Voltage-Divider Bias Calculations
All Capacitors are replaced with open circuit for DC Analysis.
• The source VDD is separated into two
equivalent sources to permit a further
separation of the input and output regions of
the network.
• IG = 0A ,Kirchhoff's current law requires that
IR1= IR2 and the series equivalent circuit
appearing to the left of the figure can be used
to find the level of VG.
• The voltage VG, equal to the voltage across
R2, can be found using the voltage divider rule
as follows: R V
VG  2 DD
R1  R 2
Using Kirchhoff’s Law:
VG – VGS – VRS = 0 The Q point is established by plotting a line that
So, VGS = VG -VRS intersects the transfer curve.
VGS  VG  I D RS
49
 Voltage-Divider Q-point
VGS  VG  I D RS
Step 1
Plot the line by plotting two points:
•VGS = VG, ID = 0 A
•VGS = 0 V, ID = VG / RS

Step 2
Plot the transfer curve by plotting
IDSS, VP and the calculated values
of ID
Step 3
The Q-point is located where the
line intersects the transfer curve

50
 Voltage-Divider Bias Calculations

Using the value of ID at the Q-point, solve for the other variables in the voltage-
divider bias circuit:

VDS  VDD  I D (R D  R S )
VD  VDD  I D R D
VS  I D R S

VDD
I R1  I R2 
R1  R 2

51
Voltage-Divider Bias Calculations

Determine ID and VGS given that

VD = 7 V

ID = (VDD – VD) / RD
VS = ID RS
VG = VDD R2 / (R1 + R2)
VGS = VG - VS

52
Example: Determine IDQ, VGSQ, VD, VS, VDS and VDG

• Draw Transfer Curve using

Shockley’s Equation.
• Determine

R2VDD
VG 
R1  R2

VGS  VG  I D RS
• Place ID=0 and VGS=0 and get
two points.
• Draw Straight Line, which
Intersects the Transfer Curve at
• IDQ= 2.4 mA and
• VGSQ= -1.8 V
Then,
VD  VDD  I D RD  10.24
VS = ID RS = 3.6
VDS  VDD  I D (R D  R S )  6.64
 Effect of increasing values of RS
Increasing values of RS result in
• lower quiescent values of ID and
• more negative values of VGS.
 FET Amplifiers

FETs provide:

• Excellent voltage gain

• High input impedance
• Low-power consumption
• Good frequency range

56
 FET Small-Signal Model
The ac analysis of an FET configuration requires that a small-signal ac
model for the FET be developed.

Transconductance
The change in Drain current that will result from a change in gate-
to-source voltage can be determined using the transconductance
factor gm in the following manner:

ΔI D
gm 
ΔV GS

57
 Graphical Determination of gm
Slope of the characteristics at the point of operation.

58
 Mathematical Definitions of gm
Alternative Approach: The derivative of a function at a point is equal
to the slope of the tangent line drawn at that point.
I D Take Derivative of ID with respect to VGS using Shockley’s
gm 
VGS Equation,

2I DSS  VGS 
gm  1  
VP  VP 
Mathematical Definitions of gm
2I DSS  VGS 
gm  1  
VP  VP 

2I DSS
Where VGS =0V g m0 
VP
 V 
g m  g m0 1  GS 
 VP 

Where 1  VGS  ID
Shockley’s Equation
VP I DSS

 VGS  ID

g m  g m0  1    g m0
 VP  I DSS
 Plot of gm versus VGS

 VGS  ID

g m  g m0  1    g m0
 VP  I DSS

Transconductance is maximum for VGS=0

Decreases as VGS becomes more negative
 Relationship of gm and ID
 VGS  ID

g m  g m0  1    g m0
 VP  I DSS
 FET Impedance

Input impedance: Very large

Zi   Typical Value of 1000 MΩ

Output Impedance:
1
Z o  rd 
y os
where:
VDS
rd  V  constant
I D GS
yos= admittance parameter listed on FET specification sheets.
Unit : Siemens
Typical Value : 10 to 50 μS

63
 FET Impedance
The output impedance is defined on the characteristics of Fig. as the
slope of the horizontal characteristic curve at the point of operation.
• The more horizontal the curve, the greater the output impedance.
• If perfectly horizontal, the ideal situation is on hand with the output
impedance being infinite (an open circuit) an often applied
approximation.
 FET AC Equivalent Circuit

• Input Open Circuited – Manifestation of High Input Impedance

• Output is Controlled Drain Current Source, controlled by input
voltage VGS.
• Output Impedance is rd from drain to source

65
 Common-Source (CS) Fixed-Bias Circuit
• The input is on the gate and the output is on the drain.
• Capacitors Act as Short Circuit. They Also Isolates DC
Biasing from Circuit. So, VGG and VDD are Short
Circuited
• gm and rd are determined from small signal analysis.

66
 Calculations
Input impedance: Zi  RG
Output impedance:

As per definition of Zo,

Setting vi=0, gives Vgs=0
So, gmVgs = 0 mA
Then,
Zo  R D || rd

Zo  R D
rd  10R D

Voltage gain:

There is a 180 phase shift

between input and output

V Vo
A v  o  g m (rd || R D ) Av   g m R D
Vi rd  10R D
Vi
Example
For Fixed Bias Configuration
With Operating Point
• VGSQ= - 2V and IDQ= 5.625
mA,
• IDSS = 10 mA VP= - 8V
• Yos = 40 μS
 Common-Source (CS) Self-Bias Circuit
• This is a common-source amplifier
configuration, so the input is on the
gate and the output is on the drain.
• Rs can play Role in Biasing, But in AC
Analysis, Capacitor Cs Shorts Rs and
thus same circuit as in Fixed Bias.

69
 Calculations
Input impedance:
Zi  RG

Output impedance:

Zo  rd || R D

Zo  R D
rd  10R D

Voltage gain:

A v  g m (rd || R D )

A v  g m R D
rd  10R D

70
 Common-Source (CS) Voltage-Divider Bias

This is a common-source
amplifier configuration, so the
input is on the gate and the
output is on the drain.

71
 Impedances
Input impedance:

Zi  R1 || R 2

Output impedance:

Zo  rd || R D

Zo  R D
rd  10R D

Voltage gain:
A v  g m (rd || R D )

A v  g m R D
rd  10R D

72
 Source Follower (Common-Drain) Circuit
In a common-drain amplifier
configuration, the input is on the gate,
but the output is from the source.

In AC Analysis DC Voltage is Shorted,

So Drain is grounded, so Terminology
is Common Drain.

There is no phase shift between

input and output.

The controlled source and internal

output impedance of the JFET are
tied to ground at one end and RS on
the other, with Vo across RS.
Since gmVgs, rd, and RS are connected to the same
terminal and ground, they can all be placed in
parallel as shown.
 Impedances

Input impedance:
Zi  RG

Output impedance:
1
Z o  rd || R S ||
gm
1
Z o  R S || r  10R S
gm d

Voltage gain:
Vo g m (rd || R S )
Av  
Vi 1  g m (rd || R S )
Vo gm RS
Av   r  10
Vi 1  g m R S d

75
 Source Follower (Common-Drain) Circuit
To Find Zo

Setting Vi = 0, results in gate terminal being connected to ground

terminal. Hence, Vo = -Vgs

76
Source Follower (Common-Drain) Circuit

77
Source Follower (Common-Drain) Circuit

78
 Common-Gate (CG) Circuit

The input is on the source

and the output is on the
drain.

There is no phase shift

between input and output.

79
 Calculations
Input impedance:

 r  RD 
Z i  R S ||  d 
 1  g m rd 
1
Z i  R S || r  10R D
gm d

Output impedance:

Zo  R D || rd
Voltage gain:
Z o  R D rd  10
 RD 
 m D
g R  
Vo  rd  A v  g m R D rd  10R D
Av  
Vi  RD 
1  
 rd 

80
 MOSFETs
Metal Oxide Semiconductor Field Effect Transistor

There are two types of MOSFETs:

• Depletion-Type
• Enhancement-Type

84
 Depletion-Type MOSFET Construction
The Drain (D) and Source (S) connect to
the to n-doped regions. These n-doped
regions are connected via an n-channel.

This n-channel is connected to the Gate (G)

via a thin insulating layer of SiO2.

This Insulating layer of SiO2 separating

Gate from Channel provides very high
input impedance of the Device.

The n-doped material lies on a p-doped

substrate that may have an additional
terminal connection called Substrate (SS).

It is also called Insulated Gate FET

(IGFET)

85
 Basic MOSFET Operation
• Gate-to-source voltage is set to zero.
• voltage VDS is applied across the drain-
to-source terminals.
• Result is an attraction for the positive
potential at the drain by the free
electrons of the n-channel and a current
similar to that established through the
channel of the JFET.

• VGS set at a negative voltage - 1 V.

• The negative potential at the gate will
tend to pressure electrons toward the p-
type substrate and attract holes from
the p-type substrate.
• Recombination of Electron and Holes in
N-Channel increases as Gate becomes
more negative.
 D-Type MOSFET in Depletion Mode
Depletion Mode
The characteristics are similar to a JFET.

• When VGS = 0 V, ID = IDSS  

2
VGS
• When VGS < 0 V, ID < IDSS 
I D  I DSS  1  
• The formula used to plot the transfer curve still applies:  VP 
 D-Type MOSFET in Enhancement Mode
Enhancement Mode

• VGS > 0 V
• ID increases above IDSS due to collision of particles creating carriers 2
• The formula used to plot the transfer curve still applies:  VGS 
DI I 
DSS  1  
Note that VGS is now a positive polarity  VP 
 D-Type MOSFET in Enhancement Mode

• For positive VGS Voltage, Current ID increases rapidly, and

may exceed the rating of the device if further increased.
• Positive VGS has enhanced the carriers available in the
channel for conduction. So this region for D-Type MOSFET
is called Enhancement Region.
p-Channel D-Type MOSFET
D-Type MOSFET Symbols

91
 E-Type MOSFET Construction
• The Drain (D) and Source (S) connect
to the to n-doped regions.

• The Gate (G) connects to the p-doped

substrate via a thin insulating layer of
SiO2

• There is no channel

• The n-doped material lies on a p-doped

substrate that may have an additional
terminal connection called the
Substrate (SS)

94
 Basic Operation of the E-Type MOSFET
The enhancement-type MOSFET operates only in the enhancement mode.

The transfer curve is not

defined by Shockley’s
equation, and the drain current
is now cut off until the gate-to-
source voltage reaches a
specific magnitude. In
particular, current control in an
n-channel device is now
effected by a positive gate-to-
source voltage rather than the
range of negative voltages
encountered for n-channel
JFETs and n-channel
depletion-type MOSFETs.
• VGS is always positive
• As VGS increases, ID increases
Basic Operation of the E-Type MOSFET

• VDS and VGS have been set at some

positive voltage greater than 0 V, makes
the drain and gate positive with respect to
the source.
• The positive potential at the gate pressure
the holes in the p-substrate along the edge
of the SiO2 layer to leave the area and
enter deeper regions.
• Thus depletion region near the SiO2
insulating layer becomes void of holes.
Basic Operation of the E-Type MOSFET
• However, the electrons in the p-
substrate (the minority carriers) will be
attracted to the positive gate and
accumulate in the region near the
surface of the SiO2 layer.
• The SiO2 layer and its insulating
qualities will prevent the negative
carriers from being absorbed at the
gate terminal.
• As VGS increases in magnitude, the
concentration of electrons near the
SiO2 surface increases until
eventually the induced n-type region
can support a measurable flow
between drain and source.
• The level of VGS that results in the
significant increase in drain current is
called the threshold voltage and is
given the symbol VT.
 Basic Operation of the E-Type MOSFET
• If VGS is increased beyond the
threshold level, the density of free
carriers in the induced channel will
increase, resulting in an increased
level of drain current.

• However, if we hold VGS constant

and increase the level of VDS, the
drain current will eventually reach
a saturation level as occurred for
the JFET and depletion-type
MOSFET.

• The leveling off of ID is due to a

pinching-off process depicted by
the narrower channel at the drain
end of the induced channel.

Applying KVL around terminal voltages

 E-Type MOSFET Transfer Curve

To determine ID given VGS:

I D  k ( VGS  VT ) 2
Where:
VT = threshold voltage
or voltage at which the
MOSFET turns on

k, a constant depends on construction of device, can be determined by using

values at a specific point and the formula:

I D(ON) VDSsat can be calculated by:

k
(VGS(ON)  VT) 2 VDsat  VGS  VT
 Locus of VDSat

VDsat  VGS  VT
 p-Channel E-Type MOSFETs

The p-channel enhancement-type MOSFET is similar to the n-

channel, except that the voltage polarities and current directions
are reversed.

101
MOSFET Symbols

102