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8086 Microprocessor Bus Cycles & Timing

Name : CH. Rajendra Prasad Designation : Senior Lecturer in ECE Branch : Electronics & communication Engg. Institute : QQ. Govt . Polytechnic, Hyderabad Year/Semester : IV Semester Subject : Microprocessors Subject Code : CM 405 Topic : Introduction and Architecture Duration : 100Mts Sub Topic : Bus Cycle And Timing Diagram Revised by :K.Srikanth,Lecturer,GPT, Nizamabad

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Y. S.V.Ramana rao

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0% found this document useful (0 votes)

4 views10 pages

8086 Microprocessor Bus Cycles & Timing

Uploaded by

Y. S.V.Ramana rao

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PPT, PDF, TXT or read online on Scribd

DEPARTMENT OF TECHNICAL EDUCATION

ANDHRA PRADESH
Name : CH. Rajendra Prasad
Designation : Senior Lecturer in ECE
Branch : Electronics & communication Engg.
Institute : QQ. Govt . Polytechnic, Hyderabad
Year/Semester : IV Semester
Subject : Microprocessors
Subject Code : CM 405
Topic : Introduction and Architecture
Duration : 100Mts
Sub Topic : Bus Cycle And Timing Diagram
Revised by :[Link],Lecturer,GPT, Nizamabad

9CM405.9TO10 1
Objectives

On completion of this topic you would be able to

understand

• Bus cycles and timing diagram of 8086 microprocessor

9CM405.9TO10 2
Recap

In the previous class, you have studied about

• Pin diagram of 8086

• Functions of various pins

9CM405.9TO10 3
Bus cycles

• The bus cycle of 8086 contains 4T-states (T1, T2,T3,T4)

• If the clock frequency is [Link] T-state = 1/5MHz

= 0.2ms

• Each bus cycle requires 0.8ms

9CM405.9TO10 4
Bus cycles (contd.)

• If a device connected to the 8086 is slow, then wait

state(s) (Tw) are introduced between T3and T4

• Status of T3 will be maintained in Tw’s

• When the data is ready T4 is completed

9CM405.9TO10 5
Timing diagram

• It includes the following signals and their state with

respect to the bus cycle

• ALE, M/IO, A19, A0, D15-D0, RD, WR, DT/R

9CM405.9TO10 6
Timing Diagram For Read Operation

9CM405.9TO10 7
Timing Diagram for Write Operation

9CM405.9TO10 8
Summary
In this lesson we have discussed about:

• Bus cycles and timing diagram

9CM405.9TO10 9
Frequently Asked Question

1. Explain how even and odd bank addressing is used in

8086

2. Draw the timing diagram of memory read bus cycle

3. Draw the timing diagram of memory write bus cycle

9CM405.9TO10 10

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8086 Microprocessor Bus Cycles & Timing

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8086 Microprocessor Bus Cycles & Timing

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DEPARTMENT OF TECHNICAL EDUCATION

On completion of this topic you would be able to

• Bus cycles and timing diagram of 8086 microprocessor

In the previous class, you have studied about

• Pin diagram of 8086

• Functions of various pins

• The bus cycle of 8086 contains 4T-states (T1, T2,T3,T4)

• If the clock frequency is [Link] T-state = 1/5MHz

• Each bus cycle requires 0.8ms

• If a device connected to the 8086 is slow, then wait

• Status of T3 will be maintained in Tw’s

• When the data is ready T4 is completed

• It includes the following signals and their state with

• ALE, M/IO, A19, A0, D15-D0, RD, WR, DT/R

• Bus cycles and timing diagram

1. Explain how even and odd bank addressing is used in

2. Draw the timing diagram of memory read bus cycle

3. Draw the timing diagram of memory write bus cycle

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