EDA Introduction
Professor: Sci.D., Prof.
Vazgen Melikyan
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EDA Introduction
Lecture - 5
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Course Overview
Introduction
1 lecture
IC Design Data Formats and Tools
4 lectures
Electronic Design Methodology
4 lectures
IC Synthesis
2 lectures
Databases for EDA
3 lectures
IC Design Approaches and Flows
3 lectures
EDA Tools
3 lectures
Overview of Synopsys EDA Tools
3 lectures
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Databases for EDA
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Databases for EDA
Integrity of information, necessary for design automation is presented as
required.
The base of information organization is
database (DB) and its control system (DBCS). DBCS DB
DB is a group of specially organized data (files), anticipated for the use in
more than one applied program. Operation with data is provided by a
special package of applied programs called DBCS.
DB, in contrast to data file presentation, has different forms of data
presentation.
DB can contain typical technical solutions (IP-blocks, standard libraries,
etc.); normative information data (different standards; design rules, etc.);
classification and coding systems; funds of algorithms and programs;
current design solutions, etc.
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Requirements to EDA Databases
Integrity of data
Universality
Openness
Availability of languages of high level
interaction of users
Privacy
Minimization of data redundancy
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Integration of DB and EDA
Design implementation tools Verification tools
Architectural Design Verification tool 1
DB
Functional – Logic Verification tool 2
Design
Circuit Design DBCS Verification tool 3
Physical Design Verification tool 4
DFM tools
Flows & Services
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Organization of Central and
Auxiliary DB
Tool 1 Tool 2 Tool 4
Local
DB 1
Global
DB
Local
DB 2
Tool 3 Tool 5
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Data Models
Data models differ in the description form of
relation of an object and attributes.
Relational –tabular description (lines are objects,
columns are attributes)
Hierarchical – multi-level tree the nodes of which are
attributes, and vertices are relations between them.
The highest node corresponds to the object.
Netting - graph representation the nodes of which are
attributes, and the vertices – relation between them.
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Data Models (2)
Relational Model example
Attributes
Number Design step
Complexity Time
1 Mapping θ(n3) minutes
2 Partitioning θ(n2) seconds
3 Floorplanning θ(n3) minutes
4 Placement θ(n2logn) minutes
5 Routing θ(n4) minutes
6 Extraction θ(n2) minutes
Advantages – simplicity, data independence
Disadvantages – redundancy, low productivity, complexity of
software implementation
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Data Models (3)
Hierarchical Model example
Floorplan
Hierarchical Model
b5 b6 n0
b10 n7 n1
b1 b3
b4
b2
n8 n2 n5
b9
b0
n11 n9 n3 n6
b8 b11
b7 n10 n4
Advantages – convenient for constructing and using multi-level objects
Disadvantages - representation complexity of set-set ratio
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Data Models (4)
Netting Model example
Circuits
Generator Trigger
Operating Switching
conditions time
Frequency
Advantages – representation simplicity of set-set ratio
Disadvantages – representation complexity from the viewpoint of the user
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The Simple Flow of Databases
Creation of conceptual model
DBCS demand for consideration
Implementation of logic model
Creation of physical model
No
Evaluation of physical
model
Yes
Implementation
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Organization of Design Library in the
Environment of Milkyway Database
MW MW MW
The Milkyway design library connects the MW Standard Macro Pad
reference libraries with the tech file, and stores all cells cells cells
design data.
Technology File
Design Library Container for all data
design.v TLU+ RC models
design_init …unit 4
[Link]
[Link]
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Databases for EDA: Design Planning Flow in
the Environment of Synopsys EDA
The Milkyway library was
Milkyway Design Floorplan
Library Constraints created during the design
setup stage.
It contains the design
Design Prototyping
connectivity (netlist),
Analyze timing,
routability and timing/area/power constraints
power integrity & pointers to required
reference libraries, TLU+
Detailed models for process and the
Floorplanning UNIX directory structures to
hold it all.
IC Compiler / IC Compiler II
detailed Implementation
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Databases for EDA: Physical Design in the
Environment of Synopsys’ IC Compiler
Gate-Level Netlist
set link_library "* [Link]"
set target_library [Link] read_verilog/vhdl/ddc Or: import_design
Logical Library Logical Constraints
.db read_sdc .sdc
create_mw_lib –technology … IC
–mw_reference_library … Compiler
read_def
Physical Constraints
MW Reference DEF or MW library
Libraries
+ tech file check_timing
check_physical_constraints
Ready for Place and Route
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Databases for EDA: Placement Tool in
the Environment of Synopsys EDA
Gate-level netlist
Floorplanned design
Logical
Target
Placement
Libraries tool
Physical
Macro cell
Design constraints Reference
Standard cell
Technology file
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Reading Gate-Level Netlists from
Synthesis
Logical synthesis tool Physical synthesis tool
Other Verilog or VHDL
Gate-level netlists files which are included
created by logical Database in database and can be
synthesis tool needed for physical
synthesis tool.
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Logical and Physical Libraries:
Logical and Target Libraries
Logical Libraries
Provide timing and functionality
information for all standard cells Logical Libraries
(AND, OR, flip-flop, etc.)
Provide timing information for hard
macros (IP, ROM, RAM, etc.)
Target Libraries
Technological library of standard
cells, provide information about
their characteristics for concrete
foundries
Target Libraries
Provide information about level
shifters and isolation cells
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Logical and Physical Libraries:
Physical Libraries Dimension
VDD “bounding box”
Contain physical information of A B
standard and macro cells Blockage
necessary for placement Pins
(direction, layer
Define placement unit tile from Symmetry Y and shape)
the length of standard cells (X, Y, or 90º) F
NAND_1
GND
reference point Abstract View
Unit tile
(site) (typically 0,0)
BUF FF
NOR
Physical Libraries
(db)
INV
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Logical and Physical Libraries:
Resolving References
Gate-level netlists contain references to standard cells
and macros, which are stored in the logical libraries, as
well as other hierarchical logic blocks
Before placement, ensure that all references can be
resolved nand nor
inv ff
pci_core
risc_core
Checking all
Gate-Level Netlist(s) references sdram, ..
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Reference Libraries
Contain subdesigns or cells used by many other designs
Referenced by pointers in the design library for memory
efficiency
Standard Macro Pad
cells cells cells
Design Library
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Reference Libraries: Standard Cell
Library
A standard cell is a predesigned layout of one specific
basic logic gate
Each cell usually has the same standard height
A standard cell library contains a varied collection of
standard cells
Libraries are usually supplied by an IC vendor or library
group
Standard cells
libraries
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