Digital Integrated

Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic

Manufacturing
Process
July 30, 2002
1
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 CMOS Process

2
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 A Modern CMOS Process
gate-oxide

TiSi2 AlCu

SiO2
Tungsten

poly
p-well n-well SiO2
n+ p-epi p+

p+

Dual-Well Trench-Isolated CMOS Process

3
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Circuit Under Design
VDD VDD

M2
M4

Vin Vout Vout2

M1 M3

4
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Its Layout View

5
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 The Manufacturing Process

For a great tour through the IC manufacturing process

and its different steps, check
[Link]

6
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Photo-Lithographic Process
optical
mask
oxidation

photoresist photoresist coating

removal (ashing)
stepper exposure

Typical operations in a single

photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process spin, rinse, dry
step

7
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2 (d) After development and etching of resist,
chemical or plasma etch of SiO
Si-substrate 2

(b) After oxidation and deposition Hardened resist

of negative photoresist SiO
2
Si-substrate
UV-light
Patterned (e) After etching
optical mask

Exposed resist
SiO
2

Si-substrate Si-substrate

(f) Final result after removal of resist

(c) Stepper exposure

8
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 CMOS Process at a Glance
Define active areas
Etch and fill trenches

Implant well regions

Deposit and pattern

polysilicon layer

Implant source and drain

regions and substrate contacts

Create contact and via windows

Deposit and pattern metal layers

9
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 CMOS Process Walk-Through
p-epi (a) Base material: p+ substrate
with p-epi layer
p+

SiN
34
SiO (b) After deposition of gate-oxide and
p-epi 2 sacrificial nitride (acts as a
buffer layer)
p+

(c) After plasma etch of insulating

trenches using the inverse of
the active area mask
p+

10
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 CMOS Process Walk-Through
SiO
2
(d) After trench filling, CMP
planarization, and removal of
sacrificial nitride

n
(e) After n-well and
V adjust implants
Tp

p
(f) After p-well and
V adjust implants
Tn

11
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 CMOS Process Walk-Through
poly(silicon)

(g) After polysilicon deposition

and etch

n+ p+

(h) After n+ source/drain and

p+ source/drain implants. These
steps also dope the polysilicon.

SiO
2

(i) After deposition of SiO

insulator and contact hole2 etch.

12
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 CMOS Process Walk-Through
Al

(j) After deposition and

patterning of first Al layer.

Al
SiO
2
(k) After deposition of SiO
insulator, etching of via’s, 2
deposition and patterning of
second layer of Al.

13
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Advanced Metallization

14
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Advanced Metallization

15
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Design Rules

16
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 3D Perspective

Polysilicon Aluminum

17
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Design Rules

 Interface between designer and process

engineer
 Guidelines for constructing process masks
 Unit dimension: Minimum line width

 scalable design rules: lambda parameter

 absolute dimensions (micron rules)

18
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 CMOS Process Layers
Layer Color Representation

Well (p,n) Yellow

Active Area (n+,p+) Green
Select (p+,n+) Green
Polysilicon Red
Metal1 Blue
Metal2 Magenta
Contact To Poly Black
Contact To Diffusion Black
Via Black

19
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Layers in 0.25 m CMOS process

20
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Intra-Layer Design Rules
Same Potential Different Potential

9 2
0
Well or Polysilicon
6
10 2
3 3
Active Metal1
Contact
or Via 2
3 Hole 3
2 2 4
Metal2
Select

21
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Transistor Layout
Transistor

3 2

22
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Vias and Contacts
2
4
Via
1 1
5
Metal to
Metal to 1 Poly Contact
Active Contact 3 2

2
2

23
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Select Layer
2
Select
3
2

1
3 3

2 5

Well
Substrate

24
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 CMOS Inverter Layout
GND In VD D

A A’

Out

(a) Layout

A A’
n
p-substrate Field
+ + Oxide
n p
(b) Cross-Section along A-A’

25
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Layout Editor

26
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um.

27
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Sticks Diagram
V DD 3

In Out
• Dimensionless layout entities
• Only topology is important
• Final layout generated by
1 “compaction” program

GND

Stick diagram of inverter

28
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Packaging

29
© Digital
EE141 Integrated Circuits 2nd Manufacturing
 Packaging Requirements

 Electrical:
Low parasitics
 Mechanical: Reliable and robust
 Thermal: Efficient heat removal
 Economical: Cheap

30
© Digital
EE141 Integrated Circuits 2nd Manufacturing
Bonding Techniques
Wire Bonding

Substrate

Die

Pad

Lead Frame

31
© Digital
EE141 Integrated Circuits 2nd Manufacturing
Tape-Automated Bonding (TAB)

Sprocket
hole

Film + Pattern Solder Bump

Die
Test
pads
Lead
frame Substrate

(b) Die attachment using solder bumps.

Polymer film

(a) Polymer Tape with imprinted

wiring pattern.

32
© Digital
EE141 Integrated Circuits 2nd Manufacturing
Flip-Chip Bonding

Die

Solder bumps
Interconnect
layers

Substrate

33
© Digital
EE141 Integrated Circuits 2nd Manufacturing
Package-to-Board Interconnect

(a) Through-Hole Mounting (b) Surface Mount

34
© Digital
EE141 Integrated Circuits 2nd Manufacturing
Package Types

35
© Digital
EE141 Integrated Circuits 2nd Manufacturing
Package Parameters

36
© Digital
EE141 Integrated Circuits 2nd Manufacturing
Multi-Chip Modules

37
© Digital
EE141 Integrated Circuits 2nd Manufacturing