Scribd
Upload
6 views1 page

Clock Signal Management in Digital Circuits

A clock generator circuit uses a mux to select between an external clock (ext_clock) and an internal clock (int_clock) to drive clock signals. However, turning off the external clock while the mux remains selecting it can violate a timing rule by keeping the internal clock signal active despite the external clock being off.

Uploaded by

Lam Pham Tung
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
6 views1 page

Clock Signal Management in Digital Circuits

A clock generator circuit uses a mux to select between an external clock (ext_clock) and an internal clock (int_clock) to drive clock signals. However, turning off the external clock while the mux remains selecting it can violate a timing rule by keeping the internal clock signal active despite the external clock being off.

Uploaded by

Lam Pham Tung
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

Clock generator

mux
Scan chain

ext_clock 1
Flip-
int_clock_mux
flop
ck
so 0 Flip- Flip-
d
si
int_clock flop flop
ck ck
d0 d d1 d
scan_in si so si so scan_out

When ext_clock = 0 but mux = 0, int_clock = 1 int_clock_mux = 1


ext_clock off but int_clock_mux still on
Violate rule C1-1

You might also like