Week 1
The Hardware Architecture of the
8085 Microprocessor
Objectives
Upon completion of this chapter, one should:
Understand the hardware architecture of the 8085.
Learn the internal architecture and bus sizes of the 8085.
Be familiar with the interrupt capabilities of the 8085.
Learn the bus timings how instructions break down into
machine cycles.
Be able to interface memory to the 8085.
Understand memory address decoding.
Be familiar on how to interface I/O to the 8085.
The 8085 Microprocessor
An 8 bit microprocessor with an 8 bit data
bus and a 16 bit address bus.
It can access 64K bytes of memory.
The chip has 40-pins.
It can work with a clock up to 3MHZ.
The 8085 Microprocessor
(Continued)
All of the signals can be put into six groups
(1) Address bus
(2) Data bus
(3) Control and status signals
(4) Power supply and clock signals
(5) Externally initiated signals
(6) Serial I/O ports
8085 Microprocessor Pinout
Figure 4.1
The 8085 Microprocessor
(Continued)
The address bus is split into two groups
The
low order 8 bits are labeled AD0-AD7 since they
are multiplexed with the 8 bit data bus.
The upper 8 bits of the address bus are labeled A8A15.
The data bus is 8 bits wide and is labeled AD0AD7, since it is multiplexed with the low order
bits of the address bus.
The 8085 Microprocessor
(Continued)
Two control signals ~RD and ~WR
Three status signals IO/~M, S1, and S0
One special symbol ALE.
5 interrupt signals INTR, RST7.5,
RST6.5, RST5.5, and TRAP.
SID and SOD are for inputting and
outputting serial data.
8085 Functional Block Diagram Figure
4.2
The 8085 Microprocessor
(Continued)
The basic blocks in the internal architecture are
Arithmetic
Logic Unit (ALU)
Timing and Control
Register Array
Instruction Decoder
Interrupt Control
Serial I/O Control
The 8085 Microprocessor
(Continued)
The five flags are
S
Sign Flag
Z Zero Flag
AC Auxiliary Carry
P Parity Flag
CY Carry Flag
The 8085 Microprocessor
(Continued)
The register array contains all of the
programmable registers B,C,D,E,H, and L
The register array also contains the 16-bit
Stack Pointer as well as the 16-bit
Program Counter
The 8085 Microprocessor
(Continued)
The 8085 microprocessor is designed to execute 74
different instructions.
Each instruction is divided into two parts - the
operation code (opcode) and the operand.
Each instruction breaks down into machine cycles.
Each machine cycle breaks down into clock cycles.
(T-States)
The 8085 Microprocessor
(Continued)
Machine cycles break down into the following
types
OpCode
Fetch
Memory Read
Memory Write
I/O Read
I/O Write
Interrupt Acknowledge
The 8085 Microprocessor
(Continued)
The Opcode Fetch retrieves the opcode of the instruction
that is being executed.
The Memory Read cycle is a machine cycle during which
memory is read into the accumulator.
The Memory Write cycle is when data is sent out from
the accumulator or a specific register, and written to
memory.
The I/O Read cycle is when an IN instruction is executed
and data is read in from an I/O device.
The I/O Write cycle writes data out from the accumulator
to the I/O device specified by the port address.
Memory Interfacing
ROM is used often to store the program .
RAM is used for temporary storage by
calculations or other operations done in
the microprocessor.
RAM and ROM uses the address bus, the
data bus, and the control bus.
8085 Microprocessor System with RAM and ROM
Figure 4.9
Memory Interfacing
(Continued)
A memory map shows all of the possible
addresses in a microprocessor system
and what they are assigned to.
The memory map is as large as the
address spectrum of the microprocessor.
Typical Memory Map
Figure 4.10
Memory Interfacing
(Continued)
Address decoding is needed in
microprocessor systems in order to select
the correct memory chip .
Decoder circuits can be made up from combinational logic or
decoder/demultiplexor chips.
An 8085 Memory System
Combinational Logic
Decoder Circuit
Figure 4.13
Input/Output Interfacing
I/O devices have two different ways of being
interfaced to the system
Memory-Mapped
I/O
Peripheral-Mapped I/O
Input/Output Interfacing
(Continued)
The Memory-Mapped I/O method of
addressing
Addresses
of the I/O devices are within the
memory address range and therefore they act
like any other memory location
The programmer can use any memory
instruction to read or write an I/O device
Input/Output Interfacing
(Continued)
Peripheral-Mapped I/O method is where
The
address range for the I/O devices is
outside of the address range for the memory
of the system.
Only I/O instructions can be used when
addressing I/O devices.
Summary
The 8085 is an 8 bit processor. The data bus is 8 bits wide and the
address bus is 16 bits wide.
The 8085 has a multiplexed bus between the data bus and the
lower 8 bits of the address bus.
The 8085 chip has 40 pins and can work with a clock up to 3MHZ.
All of the signals of the 8085 can be put into six groups - (1) address
bus, (2) data bus, (3) control and status signals, (4) power supply
and clock signals, (5) externally initiated signals, and (6) serial I/O
ports.
The 8085s address bus is 16 bits wide, and can as such address
64K bytes of memory. The address bus is split into two groups
AD0-AD7 and A8-A15.
The group of control and status signals include two control signals ~RD and ~WR - and three status signals IO/~M, S1, and S0 - and
one special symbol ALE.
Summary (Continued)
The 8085 has 5 interrupt signals that can be used to interrupt a
program that is executing. They are INTR, RST7.5,RST6.5,
RST5.5, and TRAP. The INTA is the interrupt acknowledgement
signal that is an output from the 8085.
SID (Serial Input Data) and SOD (Serial Output Data) are the I/O
ports on the 8085 that are used for inputting and outputting serial
data.
The basic blocks in the 8085s internal architecture are the
Arithmetic Logic Unit (ALU), Timing and Control, Register Array,
Instruction Decoder, Interrupt Control, and the Serial I/O Control.
The Arithmetic Logic Unit (ALU) performs the arithmetic operations
and the logical operations.
The Timing and Control Unit synchronizes all of the microprocessor
operations with the clock and generates all of the necessary control
signals to the rest of the microprocessor.
Summary (Continued)
The register array contains all of the programmable registers
B,C,D,E,H, and L as well as two temporary registers W and L that
are not accessible to general programming use.
The Instruction Decoder decodes the instruction and determines the
sequence of operations in the microprocessor that must take place.
The Interrupt Control Unit handles all of the incoming interrupts to
the microprocessor as well as the outgoing interrupt
acknowledgement signal.
The 8085 microprocessor is designed to execute 74 different
instructions. Each instruction is divided into two parts, the operation
code (opcode) and the operand.
Each instruction is broken down into machine cycles, and each
machine cycle breaks down into clock cycles. These clock cycles
are also called T-states.
Summary (Continued)
The first machine cycle in every instruction is the Opcode Fetch.
Machine cycles break down into the following types - OpCode
Fetch, Memory Read , Memory Write, I/O Read, I/O Write, and
Interrupt Acknowledge.
The ALE (Address Latch Enable) signal goes high during the
beginning of every machine cycle.
Different instructions have different number and type of machine
cycles in them, and the number of T states per machine cycle also
varies.
Microprocessor systems use ROM often to store the program that
is running the microprocessor, and RAM for temporary storage to be
used by calculations or other operations done in the microprocessor.
Summary (Continued)
In order to communicate with RAM and ROM, an interface is
necessary between the RAM and ROM memories and: the address
bus, the data bus, and the control bus from the microprocessor.
A memory map shows all of the possible addresses in a
microprocessor system and what they are assigned to.
Address decoding is needed in microprocessor systems in order to
select the correct memory chip where the address being requested
resides.
Decoder circuits can be made up of individual gates - combinational
logic, or they can be decoder or demultiplexor chips.
Interfacing I/O devices to the 8085 microprocessor has two different
methods of interfacing the Memory-Mapped I/O Method, and the
Peripheral-Mapped I/O Method.
Summary (Continued)
The memory-mapped method is basically
including the addresses of the I/O devices within
the memory address range and therefore
treating them like any other memory location.
In the peripheral-mapped I/O method, the
address range for the I/O devices is outside of
the address range for the memory of the system.