CHAPTER 4:

BUSES
/INTERCONNECTION
STRUCTURES
Dr. Syafiq Fauzi Bin Kamarulzaman

OUTLINE
Computer Buses
Bus Types
Sample of buses (ISA, PCI, PCI Express

etc)

PART ONE

We have all those individual

devices (CPU, memory and I/O),
how do these devices communicate
with one another?

BUSES
A computer consists of a set of

components (CPU, memory, I/O)

that communicate with each
other.
The collection of paths connecting

the various modules is call the

buses/interconnection structure.
The design of this structure will

depend on the exchange that

must be made between
modules/devices.
5

EXAMPLE OF DEVICES

BUSES
A bus is a common electrical pathway between multiple

devices

 This so called buses is used as a

mechanism to let these devices

communicate. So, what are their
feature?
Is there a dedicated bus/line for each

device to communicate with one another;

CPU to memory, CPU to printer, memory
to scanner or CPU to speaker etc? if it not
dedicated, then how?
or is it being shared by all of these
devices? Wait, if it is shared, who
determine which devices will used the
buses?
How many type of buses? Is it one, two or
three?

 It is

a shared transmission medium

(allows connection to multiple devices).
However, only ONE device can transmit
data (or instruction) at a time.

Each line is capable of transmitting

signals represent binary values (i.e. 1 or

0).
Hence, several lines of a bus can be

used
to
transmit
binary
digits
simultaneously
(in
parallel).
For
example, an 8-bit unit of data can be
transmitted over eight bus lines.

BUSES

The major parts of a computer model are the central processing

unit (CPU), memory and the Input and output circuitry (I/O).
Connecting these part are 3 sets of parallel lines called buses.
These buses consist of 50 to 100 separate lines and each line is

assigned particular function.

The 3 buses are the address bus, data bus and control bus.
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DATA BUS (OR DATA LINE)

It provide a path for moving data between devices.
Consist of from 32 to hundreds of separate lines (= width)
Each line carry only 1 bit at a time. The number of lines

(width) determine how many bits can be transferred at a

time - determine the overall system performance.
For example: if the data bus is 8-bit wide and each

instruction is 16 bits long, the processor must access the

memory module twice (2) during each instruction cycle.
The data bus lines are bi-directional.
Note: Many devices in a system will have their outputs

connected to the data bus, but only one device at a time will
have its output enabled.
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EXAMPLE
Data is represented as groups of 8 bits at a time. A collection of 8 bits is called a byte. A

data bus is simply a channel or pipeline through which these bits can pass on their way
from one location in the computer to another. The wider the bus, the more bits can be
packed side by side and sent at the same time, much as cars travelling a highway can be
driven side by side, as long as each car has its own lane to travel along. Today computer
have a data bus width of 32 bits; in other words they have the ability to send 32 bits at a
time from one location to another.
Imagine, for example, that we wish to send a lower-case letter 'a' to a printer. The

character 'a', being data, has to have a representation within the machine so that the
computer knows how to recognise it - using an agreed standard called ASCII, it has been
decided that the letter that we know as a lower-case 'a' will be represented within the
Thus the lower-case letter 'a' is
computer as a pattern of 8 bits: 01100101.
represented within the machine by the
byte 01100101. Now imagine that we
are on an overhead walkway looking
down on an 8-lane highway. That a '1' is
represented by a car, and that a '0' is
represented by the absence of a car. As
the byte 01100101 passes beneath us,
we would see the following traffic
pattern:
For a bus width of 32 bits, we would simply have
a highway four times wider.
[Link]

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ADDRESS BUS (OR

ADDRESS LINE)
Used to designate the source or destination of the data on

the data bus (or address)

The width of the address line determine the maximum

possible memory capacity of the system.

On these line the CPU sends out the address of the memory

location that is to be written to or read from.

For example, if the processor want to read a word (8, 16 or

32 bits) of data from memory, it puts the address of the

desired word on the address line.

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ADDRESS BUS (CONT)

The number of memory location that the CPU can address

is determined by the number of address lines. This is

calculate using 2n for example CPU with 16 address lines
can address 65536 memory (20 address line = _______
location?)
Note: When the CPU reads data from or writes data to a

port, it sends the port address out on the address bus.

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EXAMPLE:
The data bus on any processor transfers information between a particular memory

location or I/O device and the CPU. The only question is, "Which memory location or
I/O device? " The address bus answers that question.

To differentiate memory locations and I/O devices, the system designer assigns a

unique memory address to each memory element and I/O device. When the software
wants to access some particular memory location or I/O device, it places the
corresponding address on the address bus. Circuitry associated with the memory or
I/O device recognizes this address and instructs the memory or I/O device to read
the data from or place data on the data bus. In either case, all other memory
locations ignore the request. Only the device whose address matches the value on
the address bus responds
Think of memory as a linear array of bytes. The address of the first byte is zero and

the address of the last byte is ().

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CONTROL BUS (OR

CONTROL LINES)
Used to control the access to and the use of the data and

address lines.
Because data and address line are shared by all components,

hence the control line act as mechanism to control their use.

The CPU sends out signal on the control bus to enable the

outputs of addressed memory devices or port devices.

Typical control bus signals are: Memory Read, Memory

Write, I/O Read, I/O Write, Bus request, Interrupt request

etc.

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EXAMPLE:
The control bus is an eclectic collection of signals that

control how the processor communicates with the rest of

the system.
Example, consider data bus. The CPU sends data to
memory and receives data from memory on the data
bus. This prompts the question, "Is it sending or
receiving?" There are two lines on the control bus, read
and write, which specify the direction of data flow.

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EXAMPLE: READ
INSTRUCTION PROCESS
Example: Read a byte of data from a memory location,
1.

the CPU sends out a Memory Read signal on the control

bus. The memory Read signal enables the address
memory device to output a data word on the data bus.

2.

It then sends out the memory address of the desired

byte on the address bus

3.

Finally, the data word from memory travels along the

data bus to the CPU.

Q: Explain, how would the Write instruction process

work?
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LET WATCH A VIDEO

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SUMMARIZE
Buses - data, address and control bus buses are bidirectional
Data bus - the width determine overall system performance
Address bus - the width determine the maximum possible

memory capacity of the system.

Control bus - determine the direction of the data/address bus

flow
These buses play an important role during reading or writing

instruction process
If one module wishes to send data (write)
obtain the use of the bus
transfer data via the bus
If one module wishes to request data (read)

obtain the use of the bus

transfer request to the other module over the control and address lines, then

wait for that second module to send the data.

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21

PART TWO

WHAT DO BUSES LOOK

LIKE?

PHYSICAL REALIZATION OF
BUS ARCHITECTURE
System bus is a number of parallel

electrical conductors.
The

conductors are metal lines

etched in a card or printed circuit
board (PCB).

The bus extends across all of the

components that taps into the bus

lines.
Analogy: highway interchange

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SINGLE BUS PROBLEMS

The more devices attached to the bus
The greater the bus length - Therefore propagation time is

more. This propagation delay can affect performance. When

control of the bus passes from one device to another
frequently
The bus may become bottleneck as aggregate data transfer

demand approaches the capacity of bus. Because data rate

generated by attached devices like graphics and video
controller are growing rapidly
Only one master bus can operate at a time, other waits.

Most system use multiple buses to overcome these

problems.
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TRADITIONAL BUS
ARCHITECTURE

The traditional bus connection uses three buses local bus, system bus and
expansion bus

Local bus connects the processor to cache memory

The cache memory controller connects the cache to local bus and to the system bus.
System bus also connects main memory module
Input/output transfer to and from the main memory across the system bus, and do not
interface with the processor activity because processor accesses cache memory.

It is possible to connect
I/O controllers directly on
to the system bus?

A more efficient solution is

to make use of one or
more expansion buses
for
this
purpose.
An
expansion bus interface
buffers
data
transfer
between system bus and
I/O
controller
on
the
expansion bus.

This arrangement allows the

system to support a wide
variety of I/O devices and at the
same time insulate memory to

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HIGH-PERFORMANCE
ARCHITECTURE

In High Performance Bus Architecture, the concept is almost the same as

Traditional Bus Architecture. However, there is a high speed bus in

between System Bus and Expansion Bus.
This can improve the speed as cache memory is on the System Bus

alongside with the main memory. Thus, cache memory can access main
memory faster.

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SUMMARIZE PART TWO

Single bus vs multiple buses
Bus length = propagation delay
Bottleneck = aggregated data

Traditional bus vs high performance architecture

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28

PART THREE

SAMPLES OF BUS
ISA (Industry Standard Architecture)
EISA (Extended ISA)
MCA (Micro Channel Architecture)
PCI Bus (Peripheral Connection Interface)

ISA (INDUSTRY STANDARD

ARCHITECTURE)
The first standard for add-on components for the PC.
The ISA bus was an 8-Bit or 16-Bit local bus, which

connected straight on to the motherboard and into the main

bus framework of the PC.
Later the EISA (Extended ISA) was introduced, which had a

32-bit data bus, this obviously doubled the data exchange

rate between the peripheral components.
The EISA Bus could also take the old ISA cards. Many

components were designed to connect to these slots which

greatly enhanced the computer capability.

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PCI (PERIPHERAL COMPONENT

INTERCONNECT)
The

PCI bus is an interconnection

system between a microprocessor and
attached devices in which expansion
slots (speed close to CPU speed - for
high speed operation)

Frontside bus - physical connection that

connects the processor to most of the

other components in the computer (e.g.
main memory, hard drives and the PCI
slots.
Backside bus - connection between the

processor and the Level 2 cache. This

bus operates at a faster speed than the
frontside bus, usually at the same
speed as the processor, so all that
caching works as efficiently as possible.
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ACCELERATED GRAPHICS PORT

AGP is an interface specification that enables 3-D

graphics to display quickly on ordinary PC.

AGP is an interface designed to convey 3-D images (ex:from Web sites or CD-ROMs) much more quickly and
smoothly than is possible today on any computer other
than an expensive graphics workstation.
The interface uses your computer's main storage (RAM)
for refreshing the monitor image and to support the
texture mapping, z-buffering, and alpha blending
required for 3-D image display.

ACCELERATED GRAPHICS PORT

(CONT.)
The AGP main memory use is dynamic, meaning that

when not being used for accelerated graphics, main

memory is restored for use by the operating system or
other applications.
Intel, which has taken the lead in developing its
specifications, introduced AGP into a chipset for its
Pentium microprocessor.
The newer, faster microchips in Pentium line are
designed to work with the AGP chipset. Intel says the
advanced floating point unit and faster cache algorithm
of the more advanced Pentiums are better adapted for 3dimensional applications.

INTERFACE
Port
Serial
Parallel
PS/2
PCMCIA
USB
(Universal
Serial Bus)
No port
Infrared
Bluetooth

UNIVERSAL SERIAL BUS

Standard bus which is invented by a group of companies :

Compaq, DEC, IBM, Intel, Microsoft, NEC, Northern

Telecom, etc.
Not change switch, jumper on board or other devices
Can use the same cable
Device that use USB can use power supply from PC.
Up to 127 devices connected off single port
Low cost

36

PART FOUR

BUS DESIGN
1. Type - Dedicated or Multiplexed
2. Bus Width - Address or Data
3. Timing - Synchronous or Asynchronous
[Link] of Arbitration - Centralized or

Distributed
[Link] Transfer Type
Read
Write
Read-modify-write
Read-after-write
Block

BUS TYPE
Dedicated bus - When a bus is permanently assigned only 1
function, it is called dedicated bus.
e.g. separate address and data lines, with separate bus for memory and
I/O modules
Advantages: It gives high performance and less bus contention
Disadvantages: Increased size and cost.

Multiplexed bus - When the bus is used for more than 1 function.
e.g. 8085 microprocessor outputs A7- A0 in first clock cycles on pins. AD7
AD0.
Advantages: few pins lines are required. less cost and save space
Disadvantages: slow in speed

BUS WIDTH
It decides the number of lines to be used for address and

data.
Data the wider of data bus has an impact on the

number of bits transferred at one time. Therefore

speed increases.
Address the wider of address

bus has an impact on

range of locations that can be referenced/accessed;
e.g. 16 line address make = 64 kb , 20 address line
makes = 1 Mb memory access .

TIMING
Synchronous
occurrence of events on the
bus is determined by a clock
(Clock Cycle or Bus Cycle)

Asynchronous
occurrence of one event
follows and depends on
the previous event of bus.

METHOD OF ARBITRATION
Several bus master connected to a common bus may require access to the
same bus at the same time. A selection mechanism called bus arbitration
describes which device should be given access to the bus

Centralized hardware device called bus controller (Arbiter), is responsible

allocating time on the bus (e.g. daisy chain)

for

Distributed access control logic in each module act together to share bus. each
master has arbiter compared to only single in centralized approach. Equal
responsibility is given to all devices to carry out arbitration process, without using a
central arbiter

DATA TRANSFER TYPE

Read Dedicated address is put on bus and remain there while data are put on

the data bus

Write Dedicated data put on data bus as soon as the address has stabilized
Read Multiplexed bus is used to specifying address and then for transferring

data after a wait while data is being fetched

Write Multiplexed bus is used to specifying address and then transferring

data (same as read operation)

Read-modify-write address is broadcast once at beginning a simply read is

followed immediately by a write to the same address

Read-after-write a write followed immediately by a read from the same

address,performed for checking purposes

Block one address cycle is followed by n data cycles.
The first data item is transferred to or from the specified address; remainder

data items are transferred to or from subsequent addresses