Bridging the gap between

asynchronous design
and designers
Hao Zheng

Outline
What is an asynchronous circuit ?
Asynchronous communication
Asynchronous design styles (Micropipelines)
Asynchronous logic building blocks
Control specification and implementation
Delay models and classes of async circuits
Why asynchronous circuits ?

Synchronous circuit

CL

CL

CL

CLK

Implicit (global) synchronization between blocks

Clock period > Max Delay (CL + R)
Time is an independent physical variable (quantity)
3

Asynchronous circuit
Ack
R

CL

CL

CL

Req

Explicit (local) synchronization:

Req / Ack handshakes
Time = events + quantity
4
Time does not exist if nothing happens (Aristotle)

Motivation for Asynchronous

Asynchronous design is often unavoidable:
Asynchronous interfaces, arbiters etc.
Modern clocking is multi-phase and distributed and
virtually asynchronous (cf. GALS next slide):
Mesachronous (clock travels together with data)
Local (possibly stretchable) clock generation
Robust asynchronous design flow is coming (e.g. VLSI
programming from Philips, NCL from Theseus Logic,
fine-grain pipelining from Fulcrum)

Motivation (Technology Aspects)

Low power
Automatic clock gating
Electromagnetic compatibility
No peak currents around clock edges
Security
No electro-magnetic difference between logical 0
and 1in dual rail code
Robustness
High immunity to technology and environment
variations (temperature, power supply, ...)

Motivation (Designers View)

Modularity for system-on-chip design
Plug-and-play interconnectivity
Average-case peformance
No worst-case delay synchronization
Many interfaces are asynchronous
Buses, networks, ...

Globally Async Locally Sync (GALS)

Asynchronous
World

Req1

Clocked Domain

CL

Req3

Ack3

Ack1
Req2
Ack2

Local CLK

Req4
Ack4

Async-to-sync Wrapper
8

Key Design Differences

Synchronous logic design:

proceeds without taking timing correctness

(hazards, signal ack-ing etc.) into account
Combinational logic and memory latches
(registers) are built separately
Static timing analysis of CL is sufficient to
determine the Max Delay (clock period)
Fixed set-up and hold conditions for latches

Key Design Differences

Asynchronous logic design:

Must ensure hazard-freedom, signal ack-ing, local

timing constraints
Combinational logic and memory latches (registers)
are often mixed in complex gates
Dynamic timing analysis of logic is needed to
determine relative delays between paths

To avoid complex issues, circuits may be built as

Delay-insensitive and/or Speed-independent
(Mallers theory vs Huffman asynchronous automata)

10

Verification and Testing Differences

Synchronous logic verification and testing:
Only functional correctness aspect is verified and
tested
Testing can be done with standard ATE and at low
speed
Asynchronous logic verification and testing:
In addition to functional correctness, temporal aspect
is crucial: e.g. causality and order, deadlock-freedom
Testing must cover faults in complex gates
(logic+memory) and must proceed at normal
operation rate
Delay fault testing may be needed
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Synchronous communication

Clock edges determine the time instants where data

must be sampled
Data wires may glitch between clock edges (set-up/hold
times must be satisfied)
Data are transmitted at a fixed rate
(clock frequency)
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Dual Rail
1

1
0

Two wires with L(low) and H (high) per bit

LL = spacer, LH = 0, HL = 1
n-bit data communication requires 2n wires
Each bit is self-timed
Other delay-insensitive codes exist (e.g. k-of-n) and
event-based signalling (choice criteria: pin and power
efficiency)
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Bundled Data

Validity signal
Similar to an aperiodic local clock
n-bit data communication requires n+1 wires
Data wires may glitch when no validity signal.
Signaling protocols
level sensitive (latch)
transition sensitive (register): 2-phase / 4-phase
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Example: Memory Read Cycle

Valid address
Address

Valid data
Data

Transition signaling, 4-phase

15

Example: Memory Read Cycle

Valid address
Address

Valid data
Data

Transition signaling, 2-phase

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Asynchronous Modules
DATA
PATH

Data IN
start
req in
ack in

Data OUT
done

CONTROL

req out
ack out

Signaling protocol:
reqin+ start+ [computation] done+ reqout+ ackout+ ackin+
reqin- start[reset]
done- reqout- ackout- ackin(more concurrency is also possible)
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Asynchronous Latches: C element

Vdd
A

A
C

Z
B

A
0
0
1
1

B
0
1
0
1

Z+
0
Z
Z
1

A
Static Logic
Implementation

[van Berkel 91]

Gnd
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C-element: Other Implementations

Vdd

Vdd
A

Weak inverter
Z

Z
B

B
Dynamic

A
Gnd

Quasi-Static
Gnd
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Dual-Rail Logic
A.t
B.t
A.f
B.f

C.t

Dual-rail AND gate

C.f

Valid behavior for monotonic environment

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Completion Detection

Dual-rail
logic

done

Completion detection tree

21

Differential Cascode Voltage Switch Logic

start

Z.f

Z.t
done
A.t

C.f

B.f

A.f

B.t
C.t

N-type
transistor
network

start

3-input AND/NAND gate

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Examples of Dual-Rail Design

Asynchronous dual-rail ripple-carry adder (A.
Martin, 1991)

Critical delay is proportional to logN (N=number of

bits)
32-bit adder delay (1.6m MOSIS CMOS): 11ns versus
40 ns for synchronous
Async cell transistor count = 34 versus synchronous =
28

More recent success stories (modularity and

automatic synthesis) of dual-rail logic from NullConvension Logic from Theseus Logic
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Bundled-Data Logic Blocks

Single-rail logic

start

delay

done

Conventional logic + matched delay

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Micropipelines (Sutherland 89)

Micropipeline (2-phase) control blocks
r1
d1

C
Join

sel
outf
in
outt
Select

Merge

out
in 0
out
1
Toggle

r2
d2
r1
a1
r2
a2

g1
g2

r
a

25

RequestGrant-Done
(RGD)Arbiter

Call

Micropipelines (Sutherland 89)

Aout

delay

Rin

delay

logic

logic

delay

logic

Ain

Rout
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DataPath / Control

Rin
Aout

logic

logic

logic

Rout
Ain

CONTROL
Synthesis of control is a major challenge
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Control specification
A+
B+
AB-

B
A input
B output

28

Control specification
A+
BB

A
AB+

29

Control specification
A+

B+
A

C+

C
A-

B-

C-

30

Control specification
A+

B+
C+
A-

A
C
B

BC-

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Control Specification
Ri

FIFO
cntrl

Ao

Ri
Ao

Ro

Ri+

Ro+

Ao+

Ai+

Ri-

Ro-

Ao-

Ai-

Ai

Ro

Ai
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Gate vs Wire delay models

Gate delay model: delays in gates, no delays in wires

Wire delay model: delays in gates and wires

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Delay Models for Async. Circuits

Bounded delays (BD): realistic for gates and wires.

Technology mapping is easy, verification is

difficult

BD

Speed independent (SI): Unbounded (pessimistic)

delays for gates and negligible (optimistic) delays
for wires.

Technology mapping is more difficult,

verification is easy

DI
SI QDI

Delay insensitive (DI): Unbounded (pessimistic)

delays for gates and wires.

DI class (built out of basic gates) is almost empty

Quasi-delay insensitive (QDI): Delay insensitive
except for critical wire forks (isochronic forks).

In practice it is the same as speed independent

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Environment models
Slow enough environment = Fundamental mode
(Inputs change AFTER system has settled)
Reactive environment = I/O mode
(Inputs may change once the first output changes)

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Correctness of a Circuit wrt Delay

Assumptions
C-element: z = ab +zb + za

a
b

a
z

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Resistance
Concurrent models for specification
CSP, Petri nets, ...: no more FSMs
Difficult to design
Hazards, synchronization
Complex timing analysis
Difficult to estimate performance
Difficult to test
No way to stop the clock

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But ... some successful stories

Philips
AMULET microprocessors
Sharp
Intel (RAPPID)
Start-up companies:
Theseus logic, Fulcrum, Self-Timed
Solutions
Recent blurb: It's Time for Clockless Chips, by
Claire Tristram (MIT Technology Review, v.
104, no.8, October 2001:
[Link]
01/[Link]
)
.
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