Hardware Design Lab

CCE 355

Introduction to VHDL

Hardware Design Lab CCE 355

Lecture 1

VHDL Basics

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 Introduction
 VHDL stands for VHSIC (Very High Speed Integrated Circuits)
Hardware Description Language. In the mid-1980’s the U.S.
Department of Defense and the IEEE sponsored the
development of this hardware description language with the
goal to develop very high-speed integrated circuit. It has
become now one of industry’s standard languages used to
describe digital systems.
 The other widely used hardware description language is
Verilog. Both are powerful languages that allow you to describe
and simulate complex digital systems.
 Although these languages look similar as conventional
programming languages, there are some important differences.
A hardware description language is inherently parallel, i.e.
commands, which correspond to logic gates, are executed
(computed) in parallel, as soon as a new input arrives

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 Introduction
 A digital system can be represented at different levels of
abstraction. This keeps the description and design of complex
systems manageable. The figure below shows different levels
of abstraction.

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 Behavioral Level
 The highest level of abstraction is the behavioral level that
describes a system in terms of what it does (or how it
behaves) rather than in terms of its components and
interconnection between them.
 A behavioral description specifies the relationship between
the input and output signals. This could be a Boolean
expression or a more abstract description such as the
Register Transfer or Algorithmic level.

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 Behavioral Level
 VHDL allows one to describe a digital system at the structural
or the behavioral level.
 The behavioral level can be further divided into two kinds of
styles: Data flow and Algorithmic.
 The dataflow representation describes how data moves through
the system. This is typically done in terms of data flow between
registers (Register Transfer level).
 The data flow model makes use of concurrent statements that
are executed in parallel as soon as data arrives at the input.
 The algorithmic model makes use of sequential statements,
which are executed in the sequence that they are specified.
 VHDL allows both concurrent and sequential signal
assignments that will determine the manner in which they are
executed. Examples of both representations will be given later.

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 Structural Level
 The structural level, on the other hand, describes a system as
a collection of gates and components that are interconnected to
perform a desired function.

 A structural description could be compared to a schematic of

interconnected logic gates. It is a representation that is usually
closer to the physical realization of a system.

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 Basic Structure of a VHDL file
 A digital system in VHDL consists of a design entity that can
contain other entities that are then considered components of
the top-level entity. Each entity is modeled by an entity
declaration and an architecture body.
 One can consider the entity declaration as the interface to the
outside world that defines the input and output signals, while
the architecture body contains the description of the entity and
is composed of interconnected entities, processes and
components, all operating concurrently, as schematically
shown in the next slide.
 In a typical design there will be many such entities connected
together to perform the desired function.

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 Basic Structure of a VHDL file
( VHDL Entity)

A VHDL entity consisting of an interface (entity declaration) and a body

.((architectural description

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 Basic Structure of a VHDL file
(Cont.)
 VHDL uses reserved keywords that cannot be used as signal
names or identifiers. VHDL is not a case sensitive language.

 Lines with comments start with two adjacent hyphens (- -) and

will be ignored by the compiler, VHDL also ignores line breaks
and extra spaces.

 VHDL is a strongly typed language which implies that one has

always to declare the type of every object that can have a
value, such as signals, constants and variables.

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 Entity Declaration
 The entity declaration defines the NAME of the entity and lists
the input and output ports. The general form is as follows,

entity entity_name is
port (signal_names: mode type;
signal_names: mode type;
:
signal_names: mode type);
end [entity_name ] ;

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 Entity Declaration (Cont.)
 An entity always starts with the keyword entity, followed by its
name and the keyword is. Next are the port declarations using
the keyword port. An entity declaration always ends with the
keyword end, optionally followed by the name of the entity.

 The entity_name is a user-selected identifier.

 signal_names consists of a comma separated list of one or

more user-selected identifiers that specify external interfacing
signals.

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 Entity Declaration (Cont.)
 mode: is one of the following reserved words to indicate the
signal direction:

• in – indicates that the signal is an input.

• out – indicates that the signal is an output of the entity
whose value can only be read by other entities that use it.
• buffer – indicates that the signal is an output of the entity
whose value can be read inside the entity’s architecture.
• inout – the signal can be an input or an output.

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 Entity Declaration (Cont.)
 type: a built-in or user-defined signal type. Examples of types
are bit, bit_vector, Boolean, character, std_logic, and stc_ulogic.

• bit – can have the value 0 and 1

• bit_vector – is a vector of bit values (e.g. bit_vector (0 to 7)
• std_logic, std_ulogic, std_logic_vector, std_ulogic_vector:
can have 9 values to indicate the value and strength of a
signal. Std_ulogic and std_logic are preferred over the bit or
bit_vector types.
• boolean – can have the value TRUE and FALSE
• integer – can have a range of integer values
• real – can have a range of real values
• character – any printing character
• time – to indicate time

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 Entity Declaration (Examples)
 An XOR gate entity can be declared as follows:
entity XORGate is
port( in1, in2: in bit;
out1: out bit);
end;

 An 4-bit adder entity can be declared as follows:

entity adder is
port( A, B: in bit_vector (3 downto 0);
Cin: in bit;
SUM: out bit_vector (3 downto 0);
Cout: out bit);
end adder;

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 Architecture Body
 The architecture body specifies how the circuit operates and how it
is implemented. As discussed earlier, an entity or circuit can be
specified in a variety of ways, such as behavioral, structural
(interconnected components), or a combination of the above.
The architecture body looks as follows:

architecture architecture_name of NAME_OF_ENTITY is

-- Declarations
-- components declarations
-- signal declarations
-- constant declarations
-- function declarations
-- procedure declarations
-- type declarations
:
begin
-- Statements
end architecture_name;

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 (Architecture Body (Example
 An architecture body of the XORGate entity defined earlier is given
below:

architecture behavioral of XORGate is

begin
out1 <= (not in1 and in2) or (not in2 and in1);
end behavioral;

 The header line of the architecture body defines the architecture

name, i.e. behavioral, and associates it with the entity, XOR. The
architecture name can be any legal identifier.

 The main body of the architecture starts with the keyword begin.

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 (Architecture Body (Example
 The architecture body contains a signal assignment. The “ <= ”
symbol represents an assignment operator and assigns the
value of the expression on the right to the signal on the left.

 The architecture body ends with an end keyword followed

optionally by the architecture name.

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 Lecture 2

Data Flow Modeling

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 Data Flow Modeling
 The dataflow modeling describes a circuit in terms of its function
and the flow of data through the circuit.

 Concurrent signal assignments are event triggered and

executed as soon as an event on one of the signals occurs.

 Data flow modeling is usually used to build simple systems

(circuits)

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 Data Flow Modeling (Cont.)
 An example about the data flow architecture is the XOR entity
shown below:

architecture dataflow of XORGate is

signal X, Y: bit; -- signal declarations of internal signals X and Y
begin
X <= not in1 and in2;
Y <= not in2 and in1;
out1 <= X or Y;
end dataflow;

 The statements in the body of the architecture make use of

logical operators. Logic operators that are allowed are: and, or,
nand, nor, xor, xnor and not. Other types of operators
including relational, shift, arithmetic are allowed.

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 Concurrency
 It is worth pointing out that the signal assignments in the last
example are concurrent statements. This implies that the
statements are executed when one or more of the signals on
the right hand side change their value (i.e. an event occurs on
one of the signals).

 For instance, in the last example when the input in1 changes,
the internal signals X and Y change values that in turn causes
the last statement to update the output out.

 Digital systems are basically data-driven and an event which

occurs on one signal will lead to an event on another signal,
etc. The execution of the statements is determined by the flow
of signal values.

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 Concurrency (Cont.)
 As a result, the order in which these statements are given does
not matter (i.e., moving the statement for the output out ahead
of that for X and Y does not change the result).

X <= not in1 and in2; out1 <= X or Y;

Y <= not in2 and in1; = X <= not in1 and in2;
out1 <= X or Y; Y <= not in2 and in1;

 Concurrent execution is in contrast to conventional

programming languages in which statements are executed in a
sequential or procedural manner.

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 Concurrent Signal assignment
 Concurrent signal assignment can be:
• Simple signal assignments.
• Conditional signal assignments.
• Selected signal assignments.

 A simple concurrent signal assignment is given in the following

examples,

Sum <= (A xor B) xor Cin;

Carry <= (A and B);
Z <= (not X) or Y after 2 ns;

 The syntax is as follows:

Target_signal <= expression;

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 Concurrent Signal assignment
(Cont.)
 The syntax for the conditional signal assignment is as follows:

Target_signal <= expression when Boolean_condition else

expression when Boolean_condition else
:
expression;

 The target_signal will receive the value of the first expression

whose Boolean condition is TRUE. If no condition is found to be
TRUE, the target signal will receive the value of the final
expression. If more than one condition is true, the value of the
first condition that is TRUE will be assigned.

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 Concurrent Signal assignment
(Cont.)
 The selected signal assignment is similar to the conditional one
described above. The syntax is as follows,

with choice_expression select

target_name <= expression when choices,
target_name <= expression when choices,
:
target_name <= expression when choices;

 The target_name is a signal that will receive the value of an

expression whose choice includes the value of the
choice_expression.

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 Concurrent Signal assignment
(Cont.)
 The expression selected is the first with a matching choice.

 The choice can be a static expression (e.g. 5) or a range

expression (e.g. 4 to 9).

 The following rules must be followed for the choices:

• No two choices can overlap
• All possible values of choice_expression must be covered by the set
of choices, unless an others choice is present.

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 4-1 MUX using Conditional
Signal Assignment
entity MUX is
port (A, B, C, D: in bit;
SEL: in bit_vector (1 downto 0);
Z: out bit);
end MUX;

architecture concurr_MUX of MUX is

begin
Z <= A when SEL = ”00” else
B when SEL = ”01” else
C when SEL = “10” else
D;
end concurr_MUX;

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 4-1 MUX using Selected Signal
Assignment
entity MUX is
port (A, B, C, D: in bit;
SEL: in bit_vector(1 downto 0);
Z: out bit);
end MUX;

architecture concurr_MUX of MUX is

begin
with SEL select
Z <= A when “00”,
B when “01”,
C when “10”,
D when others; -- or D when “11”
end concurr_MUX;

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 Lecture 3

Structural Modeling

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 Structural Modeling
 A structural way of modeling describes a circuit in terms of
components and its interconnection.

 A structural description can best be compared to a schematic

block diagram that can be described by the components and
the interconnections. VHDL provides a formal way to do this
by:
• Declare a list of components to be used
• Declare signals which define the nets that interconnect
components
• Label multiple instances of the same component so that each
instance is uniquely defined.

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Where to Declare Components ?
 The components and signals are declared within the
architecture body:

architecture architecture_name of NAME_OF_ENTITY is

-- Declarations
component declarations
signal declarations
begin
-- Statements
component instantiation and connections
:
end architecture_name;

 Components can also been declared in the package

declaration (will be introduced later).

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 Component Declaration
 The component declaration consists of the component name
and the interface (ports). The syntax is as follows:
component component_name [is]
[port (port_signal_names: mode type;
port_signal_names: mode type;
:
port_signal_names: mode type);]
end component [component_name];
 The component name refers to either the name of an entity
defined in a library or an entity explicitly defined in the VHDL
file

 The list of interface ports gives the name, mode and type of
each port, similarly as done in the entity declaration.
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A Structural Description for the
XOR Circuit
 The XOR circuit can also be described in a structural model
that specifies what gates are used to construct the XOR circuit,
and how they are interconnected. The following example
illustrates it.

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 Example
XOR Circuit
architecture structural of XORGate is
--Declarations
component AndGate
port(And_in1, And_in2: in bit; And_out : out bit);
end component;
component OrGate
port (Or_in1, Or_in2: in bit; And_out: out bit);
end component;

Component Inverter
port(Inv_in: in bit; Inv_out: out bit);
end component;

signal S1, S2, S3, S4: bit;

begin

U0: Inverter port map (in1,S1);

U1: inverter port map (in2,S2);
U2: AndGate port map (in1,S2,S4);
U3: AndGate port map (in2,S1,S3);
U4: OrGate port map (S3,S4,out1);

end structural;

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 Discussion
 Following the header is the declarative part that gives the
components (gates) that are going to be used in the
description of the circuits.
 In our example, we use a two- input AND gate, two-input OR
gate and an inverter. These gates have to be defined first, i.e.
they will need an entity declaration and architecture body. The
declarations for the components give the inputs (e.g. And_in1,
And_in2) and the output (e.g. And_out).

 Next, one has to define internal nets (signal names). In our

example these signals are S1, S2, S3, and S4 of type “bit”. The
statements after the begin keyword gives the instantiations of
the components and describes how these are interconnected.

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 Ports association
 A component instantiation statement creates a new level of
hierarchy. Each line starts with an instance name (e.g. U0)
followed by a colon and a component name and the keyword
port map.

 Port map keyword defines how components are connected.

 Two ways are possible to assign ports:

• Positional association.
• Explicit association.

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 Positional Ports Association
 The general syntax for the positional association is shown
below:

instance_name : component name

port map (signal1, signal2,…signaln);

 In the last example, this is done through positional association,

i.e. when we write:
U3: AndGate port map (in2,S1,S3);

in2 of the MUXGate will be assigned to And_in1 of the

AndGate, and the internal signal S1 will be assigned to And_in2
of the AndGate. The outptu signal And_out1 of the AndGate will
be assigned to the internal signal S3.

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 Explicit Ports Association
 An alternative way is to use explicit association between the ports, as
shown below:

label: component-name port map (port1=>signal1, port2=> signal2,… port3=>signal);

U0: Inverter port map (Inv_in1 => in1, Inv_out => S1);
U1: inverter port map (Inv_in1 => in2, Inv_out => S2);
U2: AndGate port map (And_in1 => in1, And_in2 => S2, And_out => S4);
U3: AndGate port map (And_in1 => in2, And_in2 => S1, And_out => S3);
U4: OrGate port map (Or_in1 => S3,Or_in2 = S4, Or_out => out1);

 Notice – as mentioned earlier - that the order in which these

statements are written has no effect on the execution since these
statements are concurrent and therefore executed in parallel.
Indeed, the schematic that is described by these statements is
the same independent of the order of the statements.

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 Summary
 Structural modeling of design lends itself to hierarchical design,
in which one can define components of units that are used over
and over again. Once these components are defined they can
be used as blocks, cells or macros in a higher level entity.

 This can significantly reduce the complexity of large designs.

 Hierarchical design approaches are always preferred over flat

designs.

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 Lecture 3

Behavioral Modeling
Part 1

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 The Process Construct
 As discussed earlier, VHDL provides means to represent digital
circuits at different levels of representation, such as the behavioral
and structural modeling. In this section we will discuss different
constructs for describing the behavior of components and circuits in
terms of sequential statements.

 The basis for sequential modeling is the process construct. As you

will see, the process construct allows us to model complex digital
systems, in particular sequential circuits.

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 (.The Process Construct (Cont
 A process statement is the main construct in behavioral modeling that
allows you to use sequential statements to describe the behavior of a
system over time. The syntax for a process statement is:
[process_label:] process [ (sensitivity_list) ] [is]
[ process_declarations]
begin
list of sequential statements such as:
signal assignments
variable assignments
case statement
exit statement
if statement
loop statement
next statement
null statement
procedure call
wait statement
end process [process_label];

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 (.The Process Construct (Cont
 A process is declared within an architecture and is a concurrent
statement. However, the statements inside a process are
executed sequentially.

 Like other concurrent statements, a process reads and writes

signals and values of the interface (input and output) ports to
communicate with the rest of the architecture. One can thus
make assignments to signals that are defined externally (e.g.
interface ports) inside the process.

 The sensitivity list is a set of signals to which the process is

sensitive. Any change in the value of the signals in the
sensitivity list will cause immediate execution of the process.

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 (.The Process Construct (Cont
 If the sensitivity list is not specified, one has to include a wait
statement to make sure that the process will halt. Notice that
one cannot include both a sensitivity list and a wait statement.

 Variables and constants that are used inside a process have to

be defined in the process_declarations part before the keyword
begin.

 The keyword begin signals the start of the computational part

of the process. The statements are sequentially executed,
similarly as a conventional software program.

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 (.The Process Construct (Cont
 It should be noted that variable assignments inside a process
are executed immediately and denoted by the “:=” operator.
This is in contrast to signal assignments denoted by “<=” and
which changes occur after a delay. As a result, changes made
to variables will be available immediately to all subsequent
statements within the same process.

 Although the process is mainly used to describe sequential

circuits, one can also describe combinational circuits with the
process construct.

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 IF Statement
 The if statement executes a sequence of statements whose
sequence depends on one or more conditions. The syntax is as
follows:

if condition then
sequential statements
[elsif condition then
sequential statements ]
[else
sequential statements ]
end if;

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 (.IF Statement (Cont
 Each condition is a Boolean expression.

 The if statement is performed by checking each condition in the

order they are presented until a “true” is found.

 Nesting of if statements is allowed.

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 4-1 MUX using IF Statement
entity MUX is
port (S1, S0, A, B, C, D: in bit;
Z: out bit);
end MUX;

architecture behav_MUX of MUX is

begin
P1: process (S1, S0, A, B, C, D)
begin
if (( not S1 and not S0 )=’1’) then
Z <= A;
elsif (( not S1 and S0) = ‘1’) then
Z <= B;
elsif ((S1 and not S0) =’1’) then
Z <= C;
else
Z <= D;
end if;
end process P1;
end behav_MUX;

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 Alternative Solution - -
4-1 MUX using IF Statement
 A slightly different way of modeling the same MUX is shown
below:

if S1=’0’ and S0=’0’ then

Z <= A;
elsif S1=’0’ and S0=’1’ then
Z <= B;
elsif S1=’1’ and S0=’0’ then
Z <= C;
elsif S1=’1’ and S0=’1’ then
Z <= D;
end if;

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 CASE Statement
 The case statement executes one of several sequences of
statements, based on the value of a single expression. The
syntax is as follows:

case expression is
when choices =>
sequential statements
when choices =>
sequential statements
-- branches are allowed
[ when others => sequential statements ]
end case;

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 CASE Statement (Cont.)
 The case statement evaluates the expression and compares
the value to each of the choices. The when clause
corresponding to the matching choice will have its statements
executed.

 Two important rules should be considered when using the case

statement:
• No two choices can overlap (i.e. each choice can be covered
only once)
• If the “when others” choice is not present, then all possible
values of the expression must be covered by the set of
choices.

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 4-1 MUX using CASE Statement
entity MUX is
port ( SEL: in bit_vector(2 downto 1);
A, B, C, D: in bit;
Z: out bit);
end MUX;
architecture behav_MUX of MUX is
begin
PR_MUX: process (SEL, A, B, C, D)
begin
case SEL is
when “00” => Z <= A;
when “01” => Z <= B;
when “10” => Z <= C;
when “11” => Z <= D;
when others => Z <= ‘0’;
end case;
end process PR_MUX;
end behav_MUX;

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 Lecture 4

Behavioral Modeling
Part 2

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 LOOP Statement
 A loop statement is used to repeatedly execute a sequence of
sequential statements. The syntax for a loop is as follows:

[loop_label :] iteration_scheme loop

sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop [loop_label];

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 LOOP Statement (Cont.)
 Labels are optional but are useful when writing nested loops.

 The next and exit statement are sequential statements that can
only be used inside a loop.

 The next statement terminates the rest of the current loop

iteration and execution will proceed to the next loop iteration.

 The exit statement skips the rest of the statements, terminating

the loop entirely, and continues with the next statement after
the exited loop.

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 LOOP Statement (Cont.)
  There are three types of iteration schemes:
• basic loop
• while … loop
• for … loop

 We will consider each of these types in detail.

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 Basic LOOP Statement
 This loop has no iteration scheme. It will be executed
continuously until it encounters an exit or next statement.

[ loop_label :] loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop [ loop_label];

 The basic loop (as well as the while-loop) must have at least
one wait statement.

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 BCD counter using the Basic
LOOP Statement
entity COUNTER is
port( CLK: in bit;
COUNT: out integer);
end COUNTER;
architecture behave_COUNT of COUNTER is
begin
P_COUNT: process
variable intern_value: integer :=0;
begin
COUNT <= intern_value;
loop
wait until CLK=’1’;
intern_value:=(intern_value + 1) mod 10;
COUNT <= intern_value;
end loop;
end process P_COUNT;
end behave_COUNT;

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 Tip !!
 In the previous example, we defined a variable intern_value
inside the process because output ports cannot be read inside
a process.

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 WHILE-LOOP Statement
 The while…loop evaluates a Boolean iteration condition. When
the condition is true, the loop repeats, otherwise the loop is
skipped and the execution will halt.

 The condition of the loop is tested before each iteration,

including the first iteration. If it is false, the loop is terminated.

 The syntax for the while…loop is as follows:

[ loop_label :] while condition loop

sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop[ loop_label ];

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 FOR-LOOP Statement (Cont.)
 The for-loop uses an integer iteration scheme that determines
the number of iterations. The syntax is as follows:

[ loop_label :] for identifier in range loop

sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop[ loop_label ];

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 FOR-LOOP Statement (Cont.)
• The identifier (index) is automatically declared by the loop itself,
so one does not need to declare it separately.

• The value of the identifier can only be read inside the loop and
is not available outside its loop.

• One cannot assign or change the value of the index. This is in

contrast to the while-loop whose condition can involve variables
that are modified inside the loop.

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 FOR-LOOP Statement (Cont.)
• The range must be a computable integer range in one of the
following forms, in which integer_expression must evaluate to
an integer:
• integer_expression to integer_expression
• integer_expression downto integer_expression

• Example:

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 NEXT Statement
 The next statement skips execution to the next iteration of a
loop statement and proceeds with the next iteration. The syntax
is:
next [label] [when condition];

 The when keyword is optional and will execute the next

statement when its condition evaluates to true.

 The next statement has the same operation of the continue

statement in C++ programming language.

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 EXIT Statement
 The exit statement skips the rest of the statements, terminating
the loop entirely, and continues with the next statement after
the exited loop. The syntax is as follows:

exit [label] [when condition];

 The when keyword is optional and will execute the next

statement when its condition evaluates to true.

 The exit statement has the same operation of the break

statement in C++ programming language.

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 WAIT Statement
 The wait statement will halt a process until an event occurs.
There are several forms of the wait statement:
• wait until condition;
• wait for time expression;
• wait on signal;
• wait;

 The [ wait until condition ] clause will suspend the execution of

the process until the condition evaluates to true.

 Example :
wait until CLK =‘1’;

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 WAIT Statement (Cont.)
 The [ wait on signal ] clause specifies a list of one or more
signals that the wait statement will wait for events upon.
 Example :
wait on a, b;
• When an event occurs on either a or b, the process
resumes with the statement following the wait statement.

 The [ wait for time expression ] clause will suspend the

execution of the process for the time specified by the time
expression.
 Example :
wait for 10ns;

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 Tip !!
 It is worth pointing out that a process that contains a wait
statement can not have a sensitivity list.

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 NULL Statement
 The null statement states that no action will occur. The syntax
is as follows,
null;

 It can be useful in a case statement where all choices must be

covered, even if some of them can be ignored.

 As an example, consider a control signal CNTL in the range 0

to 31. When the value of CNTL is 3 or 15, the signals A and B
will be xor-ed, otherwise nothing will occur.

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 NULL Statement (Cont.)
entity EX_WAIT is
port ( CNTL: in integer range 0 to 31;
A, B: in bit_vector(7 downto 0);
Z: out bit_vector(7 downto 0) );
end EX_WAIT;

architecture arch_wait of EX_WAIT is

begin
P_WAIT: process (CNTL)
begin
Z <=A;
case CNTL is
when 3 | 15 =>
Z <= A xor B;
when others =>
null;
end case;
end process P_WAIT;
end arch_wait;

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 Lecture 5

Libraries and Packages

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 VHDL Libraries
 A library can be considered as a place where the compiler
stores information about a design project.

 The VHDL compiler automatically creates a library called

“work”.
• As the compiler analyzes and assembles different modules
of the design it adds their information to this work library.
• It also searches the work library for declarations of entities
and definitions of architectures.

 It is possible to access entities and architectures stored in a

common library using the library clause:

library IEEE;

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 VHDL Packages
 Including the library clause gives access to entities and
architectures but not type definitions.
• For that we need packages.

 A VHDL package is a file or module that contains declarations

of commonly used objects, data type, component declarations,
signal, procedures and functions that can be shared among
different VHDL models.

 A VHDL package is a file containing definitions of objects that

can be used in other programs.
• Information stored in a package becomes global in any file that
uses the package.

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 VHDL Packages (Cont.)
 One can use a package in a certain design by including a use
clause in the design file.
use [Link]-to-be-used

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 Standard Logic Types
 Standard logic values and elements are not
built-in.
 Standard logic is defined by a “package”,
IEEE 1164 STD_LOGIC
• Must be explicitly “used” by the program.
Compiler knows where to 
find this (system­dependent)
library IEEE;
use IEEE.std_logic_1164.all;

Use all definitions 
Library Name Package Name
in package

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 Standard Logic Values
 Defined in IEEE 1164 STD_LOGIC package.

Type STD_ULOGIC is ( ‘U’, -- Uninitialized

‘X’, -- Forcing Unknown
‘0’, -- Forcing 0
‘1’, -- Forcing 1
‘Z’, -- High Impedance
‘W’, -- Weak Unknown
‘L’, -- Weak 0
‘H’, -- Weak 1
‘-’, -- Don’t care
);
Subtype STD_LOGIC is resolved STD_ULOGIC

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 What we are going to use?
 Mainly we are going to use two packages in IEEE library:
• IEEE.std_logic_1164
• IEEE.std_logic_arith
 Use :
• Std_logic instead of Bit.
• Std_logic_vector instead of bit_vector.
 Use all keyword to indicate that you are going to use all the
definitions in the package.

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