CS601: Microprocessor &

Interfacing : UNIT 1

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 INTERRUPT
The meaning of ‘Interrupt’ is to break the
sequence of operation.
While the cpu is executing a program, ‘interrupt’
breaks the normal sequence of execution of
instructions, diverts its execution to some other
program called Interrupt Service Routine (ISR).
After executing ISR , the control is transferred
back again to the main program.

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 Purpose of Interrupts
• Interrupts are particularly useful when
interfacing I/O devices that provide or
require data at relatively low data transfer
rate.

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 Interrupt Sources
• Hardware Interrupts (External Interrupts)
ex: NMI, INTR
• Software Interrupts (Internal Interrupts
and Instructions)
ex: INT n (Software Instructions)
• NMI :-- Non Maskable Interrupt input pin which
means that any interrupt request at NMI input cannot
to masked or disabled by any means.
• INTR:-- It can be masked using the Interrupt Flag
(IF).

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 • If more than one type of INTR interrupt occurs at a
time, then an external chip called programmable
interrupt controller is required to handle them. (eg:
8259 interrupt controller).
• There are two types of interrupts
1. External interrupts
• These interrupts are generated by external devices
i.e out side the processor (uing NMI, INTR pins).
Eg: Keyboard interrupt.
1. Internal interrupts
• It is generated internally by the process circuit or by
the execution of an interrupt instruction. Eg: INT
instruction, overflow interrupt, divide by zero. At the
end of each instruction cycle, the 8086 checks to
see if any interrupts have been requested.

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 8086 Interrupt Vector Table
• The first 1Kbyte of memory of 8086 (00000 to
003FF) is set aside as a table for storing the
starting addresses of Interrupt Service Procedures
(ISP).

• Since 4-bytes are required for storing starting

addresses of ISPs, the table can hold 256
Interrupt procedures.

• The starting address of an ISP is often called the

Interrupt Vector or Interrupt Pointer. Therefore
the table is referred as Interrupt Vector Table.

• In this table, IP value is put in as low word of the

vector & CS is put in high vector.

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 Interrupt Vector Table
Type 4 POINTER
010H (OVERFLOW)

Type 3 POINTER
00CH
(BREAK POINT)
Type 2 POINTER
008H
(NON-MASKABLE)
Type 1 POINTER
004H (SINGLE STEP)
CS base address
Type 0 POINTER
000H (DIVIDE ERROR) IP offset

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 Interrupt Vector Table
03FFH
Type 255 (Available)

03FCH
Available
Interrupt
Type 32 (Available) s
(224)
080H
Type 31 (Reserved)
07FH Reserved
Interrupts
(27)
Type 5
0014H Reserved
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 Inerrupt Vector table

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 8086 Interrupt Response
ISR procedure
Mainline Program PUSH Flags PUSH registers
CLEAR IF , TF -
PUSH CS -
PUSH IP -
FETCH ISR POP registers
ADDRESS

POP IP IRET
POP CS
POP FLAGS

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8086 Interrupt Response Contd…
[Link] decrements SP by 2 and pushes the flag register
on the stack.
2. Disables INTR by clearing the IF.
3. It resets the TF in the flag Register.
[Link] decrements SP by 2 and pushes CS on the
stack.
[Link] decrements SP by 2 and pushes IP on the stack.
6. Fetch the ISR address from the interrupt vector
table.

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 Example
Find the physical address in the interrupt
vector table associated with
a) INT 12H b) INT 8H
Solution: a) 12H * 4 = 48H
Physical Address: 00048H ( 48 through 4BH
are set aside for CS & IP)
b) 8 * 4 = 20H
Memory Address : 00020H

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 Difference between INT
and CALL instructions

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 CALL Vs INT contd..

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 Functions associated with
INT00 to INT04 (Exceptions)
INT 00 (divide error)
• INT00 is invoked by the microprocessor whenever
there is an attempt to divide a number by zero
• ISR is responsible for displaying the message “Divide
Error” on the screen
Ex1: Mov AL,82H ;AL= 82
SUB CL,CL ;CL=00
DIV CL ;82/0 = undefined result
EX2: Mov AX,0 FFFFH; AX = FFFFH
Mov BL,2 ; BL=02
DIV BL ; 65,535/2 = 32767
larger than 255 maximum capacity of AL
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 INT 01
• For single stepping the trap flag must be 1
• After execution of each instruction, 8086
automatically jumps to 00004H to fetch 4
bytes for CS: IP of the ISR
• The job of ISR is to dump the registers on
to the screen

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 Resetting TF (TF = 0)
First method:
PUSH F
POP AX
AND AX, 1111 1110 1111 1111 B
PUSH AX
POP F

Second method:
PUSH F
MOV BP,SP
AND 0(BP), OFE FFH
POP F

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 Setting TF (TF = 1)
Use OR instruction in place of AND
instruction.
PUSH F
POP AX
OR AX, 0000 0001 0000 0000 B
PUSH AX
POP F

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 INT 02
(Non maskable Interrupt)

8086
5v
NMI

When ever NMI pin of the 8086 is activated by

a high signal (5v), the CPU Jumps to physical
memory location 00008 to fetch CS:IP of the
ISR assocaiated with NMI

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 INT 03 (break point)
• A break point is used to examine the cpu
and memory after the execution of a
group of Instructions.

• It is one byte instruction whereas other

instructions of the form “INT nn” are 2 byte
instructions.

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 INT 04 ( Signed overflow)

• There is an instruction associated with this

INT 0 (interrupt on overflow).
• If INT 0 is placed after a signed number
arithmetic as IMUL or ADD the CPU will
activate INT 04 if 0F = 1.
• In case where 0F = 0 , the INT 0 is not
executed but is bypassed and acts as a
NOP.

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 Example

Mov AL , 64
Mov BL , 64
ADD AL , BL 0100 0000 +64
INT 0 ; 0F = 1 0100 0000 +64
1000 0000 +128

• INT 0 causes the cpu to perform “INT 04” and jumps

to physical location 00010H of the vector table to
get the CS : IP of the ISR
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