FINAL TESTING PROCESS IN

SEMICONDUCTOR INDUSTRIES
Mohd Azizi bin Ahmad
(Senior Product Engineer)

Who Am I??
Name: Mohd Azizi Ahmad
Qualification:

Bachelor Engineering in Electrical-Telecommunication (UTM)

Working Experience:

Onsemiconductor (M) Sdn Bhd (1 years)

Designation: Product enginner

Job Scope: Design a testing program for Final testing process. Debug and trouble shoot the main
cause of low yield. Do an improvements for cost saving.

ST Microelectronics Sdn Bhd (3 years)

Designation: Product Engineer (Automotive Product Group)

Job Scope: Design a testing program for Final testing process. Debug and trouble shoot the main
cause of low yield. Do an improvements for cost saving.

ST Ericsson Sdn Bhd (2 years)

Designation: Product Engineer

Job Scope: Design a testing program for Final testing process. Debug and trouble shoot the main
cause of low yield. Do an improvements for cost saving.

Course Outline

Final testing process in Semiconductor industries

Step involves

Basic testing process

Knowledge needed from JTKE course

Semiconductor Process

Product Design
Process

Front-End
Process

Back-End
Process

Back-End Process
Wafer
Mount

Wafer
Saw & Wash

Die
Bond

Wire Bond

Trim & form

Plating

Mold

Electrical
Test

Mark

Tape &
Reel

Wafer
Mount

Wafer
Saw

Die
Bond

Clip
Bond

Plating

Trim/Form/
Singulate

Mold

Electrical
Test

Mark

Tape &
Reel

Wafer Mount

Wafers are mounted on a Mylar tape that adheres to the back of the wafer.
The mounting tape provides support for handling during wafer saw and the die
attach process.
Ring

Before

Wafer

mylar

wafer

After

Wafer mounted on ring

- Quality control :
- Broken wafer check, scratches, bubbles

Wafer
Mount

Wafer
Saw

Die
Bond

Clip
Bond

Plating

Trim/Form/
Singulate

Mold

Electrical
Test

Mark

Tape &
Reel

Wafer Saw and Wash

Cuts the individual die from the wafer leaving the die on the Mylar
tape.

Wafer after sawn is wash to remove silicon debris

Wafer mounted on ring

Sawn wafer
- Quality control :
- Die chip / crack, kerf width, Scribe defects

Wafer
Mount

Wafer
Saw

Die
Bond

Clip
Bond

Plating

Trim/Form/
Singulate

Mold

Electrical
Test

Mark

Tape &
Reel

Die Bond

Provides mechanical support to the silicon die and electrical

connection between die to leadframe.

Sawn wafer Die bond epoxy

Epoxy bonding
OR
Eutectic bonding

Lead frame: C194 or A42 based material

- Quality control :
- Die shear, Bond Line Thickness

Wafer
Mount

Wafer
Saw

Die
Bond

Clip
Bond

Plating

Trim/Form/
Singulate

Mold

Electrical
Test

Mark

Tape &
Reel

Wire Bond

Provides gold wire interconnection between silicon die pad and lead
frame lead / post.

Gold wire

=
Types of bonding machines:
- Shinkawa
- Quality control :
- ASM

- Ball shear, wire pull

Wafer
Mount

Wafer
Saw

Die
Bond

Clip
Bond

Plating

Trim/Form/
Singulate

Mold

Electrical
Test

Mark

Tape &
Reel

Mold
Mold compound protects the device mechanically and environmentally.
Transfer molding is used to encapsulate most plastic packages.

Fujiwa press

FicoAMS-M216

=
- Quality control :
- Wire Sweep Check
- Package offset &
mismatch check

Wafer
Mount

Wafer
Saw

Die
Bond

Clip
Bond

Plating

Trim/Form/
Singulate

Mold

Electrical
Test

Mark

Tape &
Reel

Plating

Allows for the mechanical and electrical connection between the package
and the printed circuit board.
Leadframe based packages most commonly use tin-lead solder plating
as the final lead finish.
Pb-free packages use pure Sn as final lead finish.

=
- Quality control :
- Solder thickness, composition

Wafer
Mount

Wafer
Saw

Die
Bond

Clip
Bond

Plating

Trim/Form/
Singulate

Mold

Electrical
Test

Mark

Tape &
Reel

Trim/Form (singulation)

The process where the individual leads of the leadframe are separated
from the leadframe strip.

Manual trim/form: Leads are cut and formed mechanically to the

specified shape with a single punch

Auto trim/form: Individual units are singulated from the leadframe

strip through progressive trim/form.

=
Manual trim/form

Auto trim/form

- Quality control :
- Lead dimensions

Wafer
Mount

Wafer
Saw

Die
Bond

Clip
Bond

Plating

Trim/Form/
Singulate

Mold

Electrical
Test

Mark

Tape &
Reel

Electrical Test

Electrical test is to ensure units are meeting electrical specification

before shipping. After assembly process.

+
RAW STOCK
- Quality control :
- Bin sort check
- Correlation test

Test handler type : Ismeca T16,NT16,NX16,T32

Wafer
Mount

Wafer
Saw

Die
Bond

Clip
Bond

Plating

Trim/Form/
Singulate

Mold

Electrical
Test

Mark

Tape &
Reel

Mark

Place corporate and product identification on a packaged device. Marking allows

for product differentiation.

Laser methods are used to mark packages.

Only good units are marked after test.

=
- Quality control :
- Marking verification

Unmark units

Mark units

Wafer
Mount

Wafer
Saw

Die
Bond

Clip
Bond

Plating

Trim/Form/
Singulate

Mold

Electrical
Test

Mark

Tape &
Reel

Tape & Reel

Final packaging of products prior shipping to customers.

- Quality control :
- Peel force check

Final Testing Process

- Experience Sharing

Introduction

Final Test is the process of testing the packaged integrated

circuits, chips, to specification

Final Test consists of multiple test insertions of each chip at

different temperatures, voltages, and frequency of
operation in an attempt to duplicate extreme conditions in
a real world environment

In addition to the final test of each unit, samples are pulled

from each group of units for Quality Assurance testing

Final Test is the true measure of a chips performance

Quality Assurance testing is a double check to verify

that the production final test was performed correctly

Overall Final Test Yield is the product of the yields of

each of the final test steps

Open/Short Test
1. Test if the wire are bonding well
2. Supply the voltage at every Pin (except
GND) then measure the current between Pin
and GND
3. Fail parts will be sorted to Bin 5/6
4. This testing were following Ohms Law.
1. V=IR
2. Force Current, Measure Voltage

Absolute Test 74LS08

1. Test Maximum Voltage: Supply 7V at VCC and test for certain time,
then test Functionality
2. Temperature: Devices Functionality need to be tested at Cold(0C),
Ambient(25C) and Hot(70C) temperature

Functionality Test

How to test the functionality of IC 74LS08 (AND GATE)?

1. Supply Voltage to the input (0V = LOW or 5V = HIGH)

2. Read the output voltage (0V = LOW or 5V = HIGH)
3. Fail parts will be sorted to Bin 8

Functionality Test (Cont.)

1.
2.
3.
4.
5.

VCC test: Functionality will be tested at VCC = 4.5V,5V,5.25V

VIH: Functionality tested with input Voltage range of 2V until 7V
VIL: Functionality tested with input Voltage range of 0V until 0.8V
IOH: Functionality tested with input Current range of 0A until -0.8mA
IoL: Functionality tested with input Voltage range of 0A until 16mA

Functionality Test (Cont.)

1. All parameter need to be tested according to the test condition on the

datasheet.
2. The result are same as the expected value as the datasheet.
3. All the test limits (upper or lower), must be set as 5% of the real limit
at datasheet

Functionality Test (Cont.)

1. Setup must follow the test condition and the input and output signal
will be measured
2. Time delay will be calculate base on the signal waveform

PLT (Pin Leakage Test)

Pin leakage test is the reverse test of Continuity.

In continuity we force current, and measure voltage.

In PLT, we force voltage and measure current)

In Theory, the leakage current happen when voltage =

80% of Knee voltage

QA Test (Quality Assurance)

Certain number of parts have complete testing at all

Temperature, will be tested with QA Test (Usually, 100
pcs will be randomly selected)

Part will be tested with Open/Short and Functionality

test Only. No absolute test required

Rejects part will be sort into Bin 2

Test yield required must be 100%

Experience
Sharing

Subject Related
to Final Testing in
Semiconductor

Trust Me, I am Engineer