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Memory Devices and Connections Overview

This document discusses different types of computer memory and their connections. It describes common memory pin connections including address, data, selection, and control connections. It provides details on address connections, data connections, selection connections, and control connections. It also summarizes different types of memory including RAM, ROM, EEPROM, SRAM, and DRAM.

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Karthik Likith
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5 views44 pages

Memory Devices and Connections Overview

This document discusses different types of computer memory and their connections. It describes common memory pin connections including address, data, selection, and control connections. It provides details on address connections, data connections, selection connections, and control connections. It also summarizes different types of memory including RAM, ROM, EEPROM, SRAM, and DRAM.

Uploaded by

Karthik Likith
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd

Memory devices

General types of memory


RAM
ROM
Common memory pin connections
Address connections
Data connections
Selection connections
Control connections

ADDRESS CONNECTIONS

Selects memory locations within the memory device


Labelled from A0 to An
10

address pins A0 to A9

No

of address pins found on memory device is


determined by no of memory locations found
within it.
1K memory device 10 address pins(A0-A9)-uses
10 address i/ps to select any of its 1024 memory
locations.
3

DATA CONNECTIONS

Points at which
Data

entered for storage


Extracted for reading

Contains set of data outputs or input/outputs


Bidirectional common i/p or output pin
Labelled as D0 through D7
Representation-1Kx8 bit memory device-8K memory device

SELECTION CONNECTIONS
Enables/selects memory device
Also called

chip

select(CS)
Chip enable (CE)/select(S)
If these pins active-perform read /write operation
Inactive-donot perform
RAM

memory atleast one CS or S i/p


ROM memoryatleast one CE

ROM only one control input


RAM has one/two control input
CASE 1:on ROM output enable(OE) or gate(G) connection
allows data flow out of the output data pin
OE active- output is enabled
OE inactive-output disabled
CASE 2: on RAM
If only one control i/p ------------R/W
If 2 control inputs----------WE or w
OE or G
WE active-perform a memory write
OE active-perform read operation

Other common types of memory

ROM
EEPROM-Flash memory
SRAM
DRAM

Permanently stores program & data


Non volatile
Types of ROMS
EPROM: Erasable Programmable Read only Memory

Used

when s/w must be changed often


When too few are in demand to make the ROM economical
PROM:

Programmable Read only Memory

Programmed by burning open tiny NI-chrome or silicon


oxide fuses, but once it is programmed cannot be erased.
8

Micro processor & assembly language

07/09/15

RMM: Read Mostly Memory/Flash memory/


EEPROM(Electrically erasable programmable ROM)/
EAROM(Electrically alterable ROM)/
NOVROM(Non Volatile ROM)
Electrically erasable in the system, but require more time to
erase than normal RAM
Used to store set up information for systems
Contains password stored in it
Memory cards for digital cameras memory in Mp3 audio
players.

SRAM(Static RAM devices)

Retain data for long as DC power is applied


Static memory: No special actions are required to retain stored
data

Volatile memory will not retain data without power

Stores temporary data-used when size of the Read/Write


memory is relatively small.
Largest static RAM available is 1M x 8

Difference b/w RAM & ROM

RAM

written under normal operations


ROM is programmed outside the computer & is only to read.

DRAM(Dynamic RAM Memory)


Available

in larger sizes upto 256M x 8


Same as SRAM, except it retains data for only 2 or 4ms on
an integrated capacitor.
After 2 or 4 ms contents must be re-written, since capacitor
lose charges
Refreshing of entire memory happens with 256 reads in a 2
or 4ms interval
DISADVANTAGE: Requires so many address pins.

11

12

3 methods to transfer data from one device to other exists


in micro computers.

Programmed I/O or Basic I/O

Hand shaking I/O

When data transferred between two devices is based


on the execution of data transfer program
without exchanging any handshake signals before or
after data transfer.
Before transferring the data between two devices , few
hand shaking signals are exchanged.
To ensure the readiness of device for the upcoming
data
Few hand shaking signals are exchanged after the data
transfer to signal the receiving side that data transfer is
finished

Direct memory access (DMA)


13

Very popular low cost interfacing component


8255 has 24 input/output pins in all, divided into three 8-bit
ports
Port A and port B can be used as 8-bit input/output ports
Port C can be used as an 8-bit input/output port or as two 4-bit
input/output ports or to produce handshake signals for ports A
and B.

14

Eight data lines (D0 - D7)

15

82C55 : Pin Layout


Eight data lines (D0 - D7) are available (with an 8-bit data
buffer) to read/write data into the ports or control register
RD (pin 5) and WR (pin 36), which are active low
signals for read and write operations respectively
The control signal CS (pin 6) is used to enable the 8255
chip
active low signal, i.e., when CS = '0', the 8255
is enabled
The RESET input (pin 35) is connected to the
RESET line of system like 8085, 8086, etc., so
that when the system is reset, all the ports are
initialized as input lines

16

Group A and Group B control:


Group A and B get the Control Signal from CPU and send the
command to the individual control blocks.

Group A send the control signal to port A and Port C


(Upper) PC7-PC4.

Group B send the control signal to port B and Port C


(Lower) PC3-PC0.

17

There are two basic operational modes of 8255:


Input/output Mode (I/O Mode).
Bit set/reset Mode (BSR Mode).

18

Input/output mode is selected when D7 bit of the Control Word Register is 1


There are three I/O modes:
Mode 0 - Simple I/O
Mode 1 - Strobed I/O
Mode 2 - Strobed Bi-directional I/O
D0, D1, D3, D4 are assigned for lower port C, port B, upper port C and port
A respectively. When these bits are 1, the corresponding port acts as an
input port.
if D0 = D4 = 1, then lower port C and port A act as input ports
If D0 = D4 = 0 then the corresponding port acts as an output
port
if D1 = D3 = 0, then port B and upper port C act as output ports.
D2 is used for mode selection of Group B
When D2 = 0, mode 0 is selected
When D = 1, mode 1 is selected.

19

D5 & D6 are used for mode selection of Group A


The selection is done as follows:

For example, if port B and upper port C have to be initialized as


input ports and lower port C and port A as output ports (all in mode
0):
Since it is an I/O mode, D = 1.
7
Mode selection bits, D2, D5, D6 are all 0 for mode 0
operation.
Port B and upper port C should operate as Input ports,
hence, D1 = D3 = 1.
Port A and lower port C should operate as Output ports,
hence, D4 = D0 = 0.

20

FOR BIT SET/RESET MODE : This is bit set/reset


control word format . Command Byte B(Port C only)
D7

D6

D5

D4

D3

D2

D1

D0

BIT SET/RESET
1=SET
0=RESET

X X X
Dont care

Bit select

B1
B2

1 2 34

5 6 7

1 0 10

1 0 1

0 1 10

0 1 1

0 0 01

1 1 1

B0

BIT SET/RESET
FLAG
=0 Active

FOR BIT SET/RESET MODE:

The Bit Set/Reset (BSR) mode is applicable to port C only


Each line of port C (PC0 - PC7) can be set/reset by suitably loading the control
word register
BSR mode and I/O mode are independent and selection of BSR mode does not
affect the operation of other ports in I/O mode.
D7 bit is always 0 for BSR mode.
Bits D6, D5 and D4 are don't care bits.
Bits D3, D2 and D1 are used to select the pin of Port C.
Bit D0 is used to set/reset the selected pin of Port C

23

Micro processor & assembly language

07/09/15

FOR BIT SET/RESET MODE:


As an example,
if it is needed that PC5 be set, then in the control word,
Since it is BSR mode, D7 = '0'.
Since D4, D5, D6 are not used, assume them to be '0'.
PC5 has to be selected, hence, D3 = '1', D2 = '0', D1 = '1'.
PC5 has to be set, hence, D0 = '1'.

24

Mode 0
the ports can be used for simple I/O operations
without handshaking signals
Port A, port B provide simple I/O operation
the two halves of port C are independent

25

Micro processor & assembly language

Port A

Upper C

Lower C

07/09/15

Port B

26

Micro processor & assembly language

07/09/15

This mode provides simple input and


output operations for each of the
three ports.
No handshaking is required, data is
simply written to or read from a
specified port.

27

Micro processor & assembly language

07/09/15

28

Micro processor & assembly language

07/09/15

Port A provides the segment data


inputs to display and port B provides
a means of selecting one display
position at a time.
Different values are displayed in
each digit via fast time division
multiplexing.

29

Micro processor & assembly language

Data saved
as

Row #

07/09/15

Col #
30

Micro processor & assembly language

07/09/15

When a key is depressed, its contact


bounces for a short period of time. This
problem is overcome by either using
hardware de-bouncer or sampling the
key second time a bit later to assure
that the same key is depressed.

31

Micro processor & assembly language

07/09/15

Techniques to overcome the problem


1. Two key lock out:
During the second scan (after bouncing time is over),
if still two keys of a row are found depressed, both
keys will be locked out & neither is accepted by the
P. However if any one of them is released after
first scan, the second key still depressed will be
accepted by P.
2. N key roll over:
During the second scan (after bouncing time is over),
if still more than one key is found depressed, they
are accepted by the P. The key entries are
accepted in the order in which they were pressed.

32

This functional configuration


provides a means for transferring
I/O data to or from a specified port
in conjunction with strobes or
handshaking signals.
In mode 1, Port A and Port B use
the lines on Port C to generate or
accept these handshaking signals

Micro processor & assembly language

Group A
Port A

07/09/15

Group B
Upper C

Lower C

Port B

Hand shaking
signals
35

Micro processor & assembly language

07/09/15

Two Groups (Group A and Group B).


The 8-bit data port can be either input or
output.
Pins of port C provide Hand shaking
signals.

36

Micro processor & assembly language

07/09/15

Keyboard encoder encodes the key-switch into


8 bit ASCII code whenever a key is depressed.
DAV (Data Available) is activated on a key
press, strobing the ASCII-coded key code into
Port A.

8086
INTR

PC 3

PC 5

IBF (input buffer


full)
37

~STB : The strobe input loads data into the port


latch on a 0-to-1 transition.
IBF : Input buffer full is an output indicating that the
input latch contain information.
INTR : Interrupt request is an output that requests
an interrupts.
INTE : The interrupt enable signal is neither an input
nor an output; it is an internal bit programmed via
the PC4 (port A) or PC2 (port B) bits.
PC7,PC6 : The port C pins 7 and 6 are general
purpose I/O pings that are available for any purpose.

Signal definitions for Mode 1 Strobe Input

Micro processor & assembly language

07/09/15

Printer

8255
PB0

8086

PB7
INTR

PC 0

ACK
PC2

ACK

PC41

DS

Data Strobe : to tell


the printer to latch the
incoming data.
Generated Externally

11-40
40

~OBF : Output buffer full is an output that goes low


when data is latched in either port A or port B. Goes
low on ~ACK.
~ACK : The acknowledge signal causes the ~OBF
pin return to 0. This is a response from an external
device.
INTR : Interrupt request is an output that requests
an interrupt.
INTE : The interrupt enable signal is neither an input
nor an output; it is an internal bit programmed via
the PC6(Port A) or PC2(port B) bits.
PC5,PC4 : The port C pins 5 and 4 are generalpurpose I/O pins that are available for any purpose.

Micro processor & assembly language

07/09/15

Uni directional port with


or without handshaking

Port A

Bidirectional 8 bit
I/O port

C7-C3

Port B

Hand shaking
signals

43

Micro processor & assembly language

07/09/15

In this mode data is transmitted in both


directions between the 8255 & the
peripheral devices on port A.
Handshaking signals are provided to
maintain proper bus flow discipline in a
similar manner to MODE 1.
Port B can be only configured for mode 0
or 1.

44

Timing

diagram is a combination of the Mode 1 Strobed Input and Mode


1 Strobed Output Timing diagrams.

Common questions

Powered by AI

The 8255 microprocessor supports flexible data transfer and control through its operational modes. In Input/Output (I/O) mode, ports can operate in simple I/O, strobed I/O, or strobed bi-directional I/O modes, allowing adaptation to different transfer needs with or without handshaking signals. The Bit Set/Reset (BSR) mode provides further configurability by enabling individual bit manipulation in port C, independent of the other ports' I/O mode operations. This flexibility allows the 8255 to be programmed for diverse interfacing tasks, catering to various hardware requirements and system designs .

The Bit Set/Reset (BSR) mode of the 8255 microprocessor allows individual pins of port C to be set or reset without affecting the operation of ports A and B in I/O mode. In contrast, the I/O mode defines how data is transferred through ports A, B, and C, either as input or output without controlling individual bits. When operating in BSR mode, the relevant control word register specifies which line of port C is affected, showing that BSR mode and I/O mode operations are independent with non-interference characteristics in multi-port configurations .

Address connections on a memory device are used to select specific memory locations within the device. The number of address pins on a memory device determines the total number of unique memory locations the device can access. For example, a memory device with 10 address pins (A0-A9) can access 1024 (2^10) memory locations, meaning it is a 1K memory device .

DRAM has significant limitations, including the need for constant refreshing every 2 to 4 milliseconds as it stores data in capacitors that lose charge over time. This necessitates additional circuitry to manage refresh cycles. Furthermore, DRAM requires a high number of address pins to manage large data volumes, increasing complexity and potentially reducing efficiency. These factors make DRAM more suited to large-scale data storage applications where space is a premium but require more intricate design considerations compared to SRAM .

RAM (Random Access Memory) and ROM (Read-Only Memory) serve different roles in computer systems. RAM is used for temporary data storage during runtime, and it allows data to be written and read during normal operations. It is volatile, meaning it loses data when power is removed. In contrast, ROM is non-volatile, retaining data without power and is primarily used for firmware storage; it is programmed outside the computer and not intended for frequent writing within a system. RAM is suited for processes requiring quick read-write capabilities, while ROM is used to permanently store critical system instructions .

SRAM (Static RAM) retains data as long as power is supplied, offering fast access times and simplicity in operation since it does not require refreshing, unlike DRAM. It is typically used for cache memory in CPUs due to its speed but is volatile and expensive. EEPROM (Electrically Erasable Programmable Read-Only Memory), on the other hand, allows data to be electrically erased and rewritten, making it suitable for applications requiring infrequent updates, like BIOS settings or firmware, with the advantage of non-volatile data retention even without power .

Handshaking I/O is a data transfer method that involves exchanging preliminary signals between devices to ensure readiness before actual data transfer and to signal completion afterwards. This synchronization technique is essential as it coordinates the operations between a sending and receiving device, preventing data loss or corruption by ensuring that the receiving device is prepared to accept incoming data, and confirming the successful completion of data transfer operations .

The 'two key lock out' technique addresses key bounce problems by performing a second scan after an initial key press, during which, if two keys in the same row are detected as depressed, both are ignored. This ensures that only an intentional single key press is recognized. Should one key be released after the first scan, the second key is accepted upon being verified in a subsequent scan, effectively filtering out noise from unintentional bounces .

The 8255 microprocessor uses Group A and Group B to manage port operations and signals. Group A controls Port A and the upper bits of Port C (PC7-PC4), while Group B controls Port B and the lower bits of Port C (PC3-PC0). Control signals from the CPU dictate the function of these ports, determining whether each port acts as an input or output, and also handle the necessary configurations for handshaking signals as needed .

RAM typically has one or two control inputs. With one control input, the operation is managed by a single Read/Write (R/¬W) signal. For two control inputs, ¬WE (Write Enable) must be active for a write operation, while ¬OE (Output Enable) must be active for a read operation. These controls allow RAM to perform the specified operation based on the enablement of these pins, ensuring that data can either be written to the memory device or read from it when the appropriate control signals are active .

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