DIGITAL MODULATION

Topic Outline:

Introduction
Information Capacity, Bits, Bit Rate, Baud, and M-ary
Encoding
Amplitude-Shift Keying
Frequency-Shift Keying

Introduction

Electronic communications
is the transmission, reception, and processing of information
with the use of electronic circuits
Information
is defined as the knowledge or intelligence that is
communicated between two or more points
e.g., data, voice, picture or video

Introduction

Digital Modulation
is the transmittal of digitally modulated analog signals
(carriers) between two or more points in a communication
system
digital radio because digitally modulated signals can be
propagated through Earths atmosphere and used in wireless
communications
offers several outstanding advantages over traditional analog
systems, such as ease of processing, ease of multiplexing, and
noise immunity

Introduction

Digital Communications
include systems where relatively high-frequency analog
carriers are modulated by relatively low-frequency digital
information signals (digital radio) and systems involving the
transmission of digital pulses (digital transmission)
digital transmission systems transport information in digital
form and require a physical facility between the transmitter and
the receiver (i.e., metallic wires, coaxial cable, or an optical
fiber)
In digital radio, the transmission facility could be a physical
cable or a free space

Introduction

Modulation is the process of varying a certain characteristic

(usually amplitude, frequency, or phase) of a high-frequency
carrier in proportion with the characteristic of a low-frequency
modulating or information signal.
Information
Signal/
Component of the
Carrier to be
Varied

Analog

Digital

Amplitude

Amplitude
Modulation

Amplitude-Shift
Keying

Frequency

Frequency
Modulation

Frequency-Shift
Keying

Phase

Phase Modulation

Phase-Shift Keying

Amplitude & Phase

None

Quadrature Amplitude
Modulation

Introduction

1.
2.
3.
4.

Digital Modulation is ideally suited to a multitude of

communications applications, including both cable and
wireless systems.
Applications include:
Relatively low-speed voice-band data communications
modems, such as those found in most personal computers;
High-speed data transmission systems, such as broadband
digital subscriber lines (DSL);
Digital microwave and satellite communications systems;
Cellular telephone Personal Communications Systems (PCS)

Simplified Block Diagram of a Digital

Radio System
RECEIVER

TRANSMITTER

Inp
ut
dat
a
cloc
k

Precoder

Modulator

Buffer

Analog
carrier

BPF and
Power amp

BPF and
amplifier

NOISE

cloc
k

Demodulator
and decoder

BPF

Carrier
and carrier
recovery CARRIER

OUTPUT
DATA

Introduction

In the transmitter, the precoder performs level conversion and then

encodes the incoming data into groups of bits that modulate an
analog carrier.
The modulated carrier is shaped (filtered), amplified, and then
transmitted through the transmission medium to the receiver.
In the receiver, the incoming signals are filtered, amplified, and
then applied to the demodulator and decoder circuits, which
extracts the original source information from the modulated carrier.
The clock and carrier recovery circuits recover the analog carrier
and digital timing (clock) signals from the incoming modulated
wave since they are necessary to perform the demodulation
process.

Information Capacity, Bits, Bit

Rate, Baud, and M-ary Encoding

Information Theory is a highly theoretical study of the

efficient use of bandwidth to propagate information through
ECSs and use to determine the information capacity of a data
communication system.

Information Capacity is a measure of how much information

can be propagated through a communications system and is a
function of bandwidth and transmission time.
- is often expressed as a bit rate.

Information Capacity, Bits, Bit

Rate, Baud, and M-ary Encoding
Hartleys Law is
IBxt
Shannon limit for information capacity is
I = B log2 (1 + S/N)
Or
I = 3.32 B log (1 + S/N)
For a standard telephone circuit with a signal-to-noise power
ratio of 1000 (30 dB) and a bandwidth of 2.7 kHz, the
Shannon limit for information capacity is
I = 3.32(2700) log (1 + 1000) = 26.9 kbps

Information Capacity, Bits, Bit

Rate, Baud, and M-ary Encoding

M-ary Encoding
- M represents a digit that corresponds to the number of conditions,
levels, or combinations of a given number of bits
For example, a digital signal with four possible conditions (voltage
levels, frequencies, phases, and so on) is an M-system where M = 4.
The number of bits necessary to produce a given number of
conditions is expressed mathematically as
N = log2 M
where N = number of bits necessary
M = number of conditions, levels, or combinations
with N bits

possible

Information Capacity, Bits, Bit

Rate, Baud, and M-ary Encoding

Bit rate refers to the rate of change of a digital information

signal
Baud refers to the rate of change of a signal on the
transmission medium after encoding and modulation
occurred
Baud is a unit of transmission rate, modulation rate, or
symbol rate (symbols per second)
baud = 1/tS
where baud = symbol rate (symbols per second)
tS = time for one signaling element (seconds)

Information Capacity, Bits, Bit

Rate, Baud, and M-ary Encoding

A signaling element is sometimes called a symbol and could

be encoded as change in the amplitude, frequency, or phase.

For example, binary signals are generally encoded and

transmitted one bit at a time in the form of discrete voltage
levels representing logic 1s (highs) and logic 0s (lows).

A baud is also transmitted one at a time; however, a baud may

represent more than one information bit.

Information Capacity, Bits, Bit

Rate, Baud, and M-ary Encoding

According to H. Nyquist, binary signals can be propagated

through an ideal noiseless transmission medium at a rate equal
to two times the bandwidth of the medium. The minimum
theoretical bandwidth necessary to propagate a signal is called
the minimum Nyquist bandwidth or minimum Nyquist
frequency.
Thus, fb = 2B, where fb is the bit rate in bps and B is the ideal
Nyquist bandwidth.
The actual bandwidth necessary to propagate a given bit rate
depends on several factors, including the type of encoding, and
modulation used, the types of filters used, system noise, and
desired error performance.

Information Capacity, Bits, Bit

Rate, Baud, and M-ary Encoding

For a given bandwidth (B), the highest theoretical bit rate is

2B.

For example, a standard telephone circuit has a bandwidth

approximately 2700 Hz, which has the capacity to propagate
5400 bps through it. However, if more than two levels are used
for signaling (higher-than-binary encoding), more than one bit
may be transmitted at a time, and it is possible to propagate a
bit rate that exceeds 2B.

Information Capacity, Bits, Bit

Rate, Baud, and M-ary Encoding

Using multilevel signaling, the Nyquist formulation for channel

capacity is
fb = B log2 M
where fb = channel capacity (bps)
B = minimum Nyquist Bandwidth (hertz)
M = number of discrete or voltage levels

To solve for the minimum bandwidth necessary to pass M-ary

digitally modulated carriers
B = (fb / log2 M) or
B = fb / N

Amplitude-Shift Keying

simplest digital modulation technique

A binary information signal directly modulates the amplitude
of an analog carrier
sometimes called digital amplitude modulation (DAM)
Mathematically, ASK is
vASK(t) = [1 + vm(t)][A/2cos (wct)]

where vASK(t) = ASK wave

vm(t) = digital information (modulating) signal (volts)
A/2 = unmodulated carrier amplitude (volts)
wc = analog carrier radian frequency (radians per second, 2f ct)

Amplitude-Shift Keying

If the modulating sinal (vm[t]) is normalized binary waveform, where

+1 = logic 1 and 1 = logic 0.

For a logic 1,
vASK(t) = [1 + 1][A/2cos (wct)]
vASK(t) = [2][A/2cos (wct)]
vASK(t) = Acos (wct)

For a logic 0,
vASK(t) = [1 1][A/2cos (wct)]
vASK(t) = [0][A/2cos (wct)]
vASK(t) = 0

Amplitude-Shift Keying

(a) binary input (b) ASK output waveform

ASK waveform is the same as the rate of change of the binary

input (bps); thus, the bit rate equals the baud. With ASK, the
bit rate is also equal to the minimum Nyquist Bandwidth.
B = fb / 1 = fb
baud = fb / 1 = fb

Amplitude-Shift Keying

Example:
Determine the baud and minimum bandwidth necessary to pass
a 10 kbps binary signal using amplitude shift keying.

Frequency-Shift Keying/Binary
FSK

another relatively simple, low-performance type of digital

modulation
is a form of constant-amplitude angle modulation similar to
standard FM except the modulating signal is a binary signal
that varies between two discrete voltage levels rather than a
continuously changing analog waveform
The general expression for FSK is
vfsk(t) = Vc cos {2[fc + vm(t)f]t}

Frequency-Shift Keying/Binary
FSK

The modulating signal is normalized binary waveform where a

logic 1 = +1 V and a logic 0 = 1 V.

If vm(t) = +1 V or logic 1,
vfsk(t) = Vc cos [2(fc + f)t]

If vm(t) = 1 V or logic 0,
vfsk(t) = Vc cos [2(fc f)t]

Frequency-Shift Keying/Binary
FSK

The output frequency shifts between two frequencies:

Binar
y
input

Frequency Freq.
output

space (fs)

fc f

mark (fm)

fc + f

f (Frequency Deviation) is expressed mathematically as

f = |fm - fs| / 2

Frequency-Shift Keying/Binary
FSK

The baud for binary FSK,

baud = fb / 1 = fb

FSK is the exception to the rule for digital modulation, as the

minimum bandwidth is not determined by Nyquists Equation
but
B = |(fs + fb) (fm fb)|
B = |fs fm| + 2fb

since 2f = |fm - fs|

B = 2f + 2fb
B = 2(f + fb)

almost resembles to Carsons Rule

Frequency-Shift Keying/Binary
FSK

Example:
Determine (a) the peak frequency deviation, (b) minimum
bandwidth, and (c) baud for a binary FSK signal with a mark
frequency of 49 kHz, a space frequency of 51 kHz, and an
input bit rate of 2 kbps.
Answer:
(a) 1 kHz
(b) 6 kHz
(c) 2000 symbols/sec

Frequency-Shift Keying/Binary
FSK

Bessel function can be used to determine the approximate

bandwidth for an FSK wave. The fastest rate of change
(highest fundamental frequency) in a nonreturn-to-zero (NRZ)
binary signal occurs when alternating 1s and 0s are occurring
(i.e., square wave).
Since it takes a high and a low to produce a cycle, the highest
fundamental frequency present in a square wave equals the
repetition rate of the square wave, which with a binary signal is
equal to half the bit rate.
fa = fb / 2
where fa = highest fundamental frequency of the binary input
signal (hertz)

Frequency-Shift Keying/Binary
FSK

The formula used for modulation index in FM is also valid for

FSK.
h = f / fa
where h = FM modulation index called the h-factor in FSK
fa = fundamental frequency of the binary modulating
signal (hertz)
f = peak frequency deviation (hertz)

The worst-case modulation index (deviation ratio) is that

which yields the widest bandwidth. The worst-case or widest
bandwidth occurs when both the frequency deviation and the
modulating frequency are at their maximum values.

Frequency-Shift Keying/Binary
FSK

The peak frequency deviation in FSK is constant and always at

its maximum value, and the highest fundamental frequency is
equal to half the incoming bit rate.
h = {|fm - fs| /2 }/{fb / 2}
h = fm - fs| / fb

Example:
Using the Bessel table, determine the minimum bandwidth for
an FSK signal with a mark frequency of 49 kHz, a space
frequency of 51 kHz, and an input bit rate of 2 kbps.
Answer: 6 kHz

Frequency-Shift Keying/Binary
FSK

FSK Transmitter
In a binary FSK modulator, f is the peak frequency deviation
of the carrier and is equal to the difference between the carrier
rest frequency and either the mark or the space frequency.
A VCO-FSK modulator can be operated in the sweep mode
where the peak frequency deviation is simply the product of the
binary input voltage and the deviation sensitivity of the VCO.
With the sweep mode of modulation, the frequency deviation is
expressed mathematically as
f = vm(t)kt
where kt = deviation sensitivity (hertz per volt)

FSK Demodulator
Noncoherent

FSK Input

BPF

Envelope
detector

DC

Power
Splitter

Data output

BPF

Coherent
X

FSK Input

Rectified signal

Power
Splitter

Envelope
detector

Carrier

DC

Comparator

Multiplier

LPF

Carrier
X

LPF

Data output

PLL FSK Demodulator

Phase
Comparator

Low-pass
Loop
Filter
Voltage
Controlled
Oscillator

Amp

Analog
FSK in

PLL

BINARY DATA
OUT

Topic Outline:

Introduction to PSK
BPSK
QPSK
8-PSK
16-PSK

Phase-Shift Keying

is an M-ary digital modulation scheme similar to

conventional PM except that the input is a
binary digital signal and there are limited
number of output phases possible.
The input binary information is encoded into
groups of bits before modulating the carrier.
The number of bits in a group ranges from 1 to
12 or more.
The number of output phases is defined by M
(2N=M) and determined by the number of bits
in the group (N).

Phase-Shift Keying
Binary PSK
The simplest form of PSK where N=1 and M=2.
One phase represents logic 1, and the other
phase represents a logic 0. As the input digital
signal changes state (i.e., from a 1 to a 0 or
from a 0 to a 1), the phase of the output carrier
shifts between two angles that are separated by
180.
Other names:
1. Phase-Reversal Keying (PRK)
2. Biphase Modulation

BPSK Transmitter

Level
Converter
(UP TO BP)

Balance
Modulator

Binary Data in

sin wct
BUFFER

sin wct
Reference
Carrier
Oscillator

BPF

Modulated
PSK output

BPSK Transmitter

Balance Modulator acts a phase reversing

switch

Depending on the logic condition of the digital

input, the carrier is transferred to the output
either in phase or 180 out of phase with the
reference carrier

Truth Table, Phasor Diagram and

Constellation Diagram

Truth table shows the function between the input

and the output

Phasor diagram shows the phase of each input

level

Constellation diagram sometimes called signal

state-space diagram and similar to phasor diagram
except that the entire phasor is not drawn
relative positions of the peaks of the phasors are
shown

BPSK Modulator

(+90o)
cos wct

Phasor diagram

Truth table
Binary Input

Output phase

Logic 0

180o

Logic 1

sin wct
(180o)
Logic 1

sin wct
(0o)
Logic 0

cos wct

cos wct
(-90o)

180o

0o Reference

Logic 1

Logic 0

Constellation diagram
- cos wct

Bandwidth Consideration of
BPSK

A balance modulator is a product detector; the

output is the product of two input signals.
BPSK output = [sin (2fat)] x [sin (2fct)]
where fa = max. fundamental frequency of binary input (Hz)
fc = reference carrier frequency (Hz)

Solving for the trig identity for the product of two

sine functions,
BPSK output = cos [2(fc fa)t] - cos [2(fc
+ fa)t]
Bandwidth = (fc + fa) - (fc fa) = 2 fa
Bandwidth = 2(fb/2) = fb

BPSK Example:

For a BPSK modulator with a carrier frequency

of 70 MHz and an input bit rate of 10 Mbps,
determine the maximum and minimum upper
and lower side frequencies, draw the output
spectrum, determine the minimum Nyquist
bandwidth and calculate the baud.
Answer:
BPSK output = cos [2(65 MHz)t] - cos
[2(75MHz)t]
Min. LSF = 65 MHz, Max. USF = 75 MHz

Block Diagram of a BPSK Receiver

Balance
Balance
Modulator
Modulator

BPF
BPF

BPF
BPF

Level
Level
Converter
Converter

BPSK input

Coherent
Coherent
Carrier
Carrier
Recovery
Recovery

Clock
Clock
Recovery
Recovery

UP Binary
Data output

BPSK Receiver

For a BPSK input signal of +sin wct(logic 1), the output of

the balance modulator is
output = [sin wct] x [sin wct] = sin2 wct
sin2 wct = (1 cos 2wct) = - cos 2wct -> filtered out
output = + V = logic 1

For a BPSK input signal of sin wct(logic 0), the output of

the balance modulator is
output = [sin wct] x [sin wct] = sin2 wct
sin2 wct = (1 + cos 2wct) = + cos 2wct -> filtered
out
output = V = logic 0

Quarternary or Quadrature PSK

QPSK is an M-ary encoding scheme where N=2

and M=4.
Four output phases representing each two-bit
input: 00, 01, 10 and 11.
The four possible output phases (+45, +135,
45, 135)

QPSK Modulator
I CHANNEL fb/2
Logic 1 = +1 V
Logic 0 = 1 V

BINARY INPUT
DATA fb

BALANCE
MODULATOR

REF. CARRIER
OSCILLATOR
(sin wCt)

sin wCt

Bandpass
Filter
QPSK
OUTPUT

BIT
SPLITTER

I
LINEAR
SUMMER

90 PHASE
SPLITTER
cos wCt

BIT
CLOCK

+/- sin wCt

+2

Q CHANNEL fb/2
Logic 1 = + 1 V
Logic 0 = 1 V

BALANCE
MODULATOR

Bandpass
Filter

+/- cos wCt

BPF

QPSK Modulator

Two bits (dibit) are clocked into the splitter.

After both bits have been serially inputted, they
are simultaneously parallel outputted.
One bit is directed to the I channel and the
other to the Q channel.
The I bit modulates a carrier that is in phase
with the reference oscillator, and the Q bit
modulates a carrier that is 90 out of phase or
in quadrature with the reference carrier.
A QPSK modulator is two BPSK modulators
combined in parallel.

QPSK Modulator
Example:
For a QPSK modulator as shown on the previous
slide, construct the truth table, phasor diagram,
and constellation diagram.

QPSK Modulator
Answer: QPSK outputs (4)
From trig identity sin (A + B) = sin A cos B + cos A sin
B;
If input (I = 0, Q = 0),
1 sin wct 1 cos wct = 1.414 sin (wct 135)
If input (I = 1, Q = 0),
+1 sin wct 1 cos wct = 1.414 sin (wct 45)
If input (I = 0, Q = 1),
1 sin wct +1 cos wct = 1.414 sin (wct + 135)
If input (I = 1, Q = 1),
+1 sin wct +1 cos wct = 1.414 sin (wct + 45)

QPSK Modulator:
Answer:

Truth table
Binary
Input

QPSK
Output
Phase

0
0
1
1

0
1
0
1

135
45
+ 135
+ 45

Phasor Diagram
Q
I
cos wct - sin
w ct
1
0
sin (wct +
135o)

cos wct

Q
I
cos wct + sin
w ct
1
1
sin (wct 45o)

10

Constellation
Diagram cos w t
c

11

- sin wct
- sin wct

Q
I
cos wct + sin
wct
0
0

sin wct
0o Reference

- cos wct

Q
I
cos wct + sin
w ct
0
1
sin (w t 45o)

sin wct

01
00

- cos wct

Bandwidth Considerations of a QPSK

Modulator
I Channel
fb/2

Bit
splitter
Binary
Input
Data fb

Balance
Modulator

sin wct

sin wct

I
cos wct

fb/2

Q Channel

Balance
Modulator
cos wct

The
highest
fundamental frequency
present in the data
input to the I or the Q
balance modulator is
equal to one-fourth of
the input bit rate (onehalf of fb/2 = fb/4).

Bandwidth Considerations of a QPSK

The output of the balanced modulators can be

expressed mathematically as,
output = (sin wat)(sin wct)
where

wat = 2(fb/4)t (modulating signal)

wct = 2fct
(carrier)

Example:

For a QPSK modulator with an input data rate

(fb) equal to 10 Mbps and a carrier frequency of
70 MHz, determine the minimum double-sided
Nyquist bandwidth (fN) and the baud. Use the
QPSK block diagram shown on the previous
slide as the modulator model.

Example:(Solution)

The bit rate in both the I and Q channels is

equal to one-half of the transmission bit rate or

The highest fundamental frequency presented

to either balanced modulator is

Example:(Solution)

The output wave from each balanced modulator is

The minimum Nyquist bandwidth is

B = (72.5 67.5) Mhz = 5 Mhz
The symbol rate equals the bandwidth; thus,
Baud or symbol rate = 5 megabaud

QPSK
Receiver

(sin ct)(sin ct + cos ct)

I Channel

Product
Product
detector
sin ct + cos detector
ct

sin ct

sin ct + cos ct
Input
QPSK
signal

BPF

Power
Power
Splitter
Splitter

V (logic 0)
LPF

Carrier
Carrier
Recovery
Recovery
(sin
(sin
cct)
t)

Q
Q

Received
Binary
data

II

+90
+90

cos ct
sin ct + cos Product
ct
Product
detector
Q Channel
detector

Clock
Clock
recovery
recovery

LPF
+ V (logic 1)

(cos ct)(sin ct + cos ct)

QPSK Receiver

The receive QPSK signal (sin wct + cos wct) is

one of the inputs to the I product detector. The
input is the recovered carrier (sin wct). The
output of the I product detector is

QPSK Receiver

The receive QPSK signal (sin wct + cos wct) is

one of the inputs to the Q product detector. The
other input is the recovered carrier shifted 90
in phase (cos wct). The output of the I product
detector is

Offset keyed
(OQPSK)
Ichannel
Input
data

One-half
One-half
Bit
Bit delay
delay

Balance
Balance
modulator
modulator

sin ct
Reference
Reference
Carrier
Carrier
oscillator
oscillator
o
+90
+90o

Q-channel
Input data

cos ct
Balance
Balance
modulator
modulator

Bandpass
Bandpass
filter
filter

Linear
summer
Bandpass
Bandpass
filter
filter

OQPSK
out
Bandpass
Bandpass
filter
filter

Offset keyed (OQPSK)

is a modified form of QPSK where the bit waveforms

on the I and Q channels are offset or shifted in
phase from each other by one-half of a bit time.
In conventional QPSK, a change in the input dibit
from 00 to 11 or 01 to 10 causes a corresponding
180 shift in the output phase.
An advantage of OQPSK is the limited phase shift
that must be imparted during modulation. A
disadvantage of OQPSK is that changes in the
output phase occur at twice the data rate in either
the I or Q channels.

8-PSK

Three bits are encoded, forming tribits(N=3) and

producing eight different phases (M=8).

8-PSK Transmitter
The incoming serial bit stream enters the bit splitter,
where it is converted to a parallel, three channel
output (the I or in-phase channel, the Q or inquadrature channel, and the C or control channel).
The bit rate in each channel is f b/3.
The bits in the I and C channels enter the I channel
2-to-4 level converter, and the bits in the Q and C
channel enters the Q channel 2-to-4 level converter.

8-PSK Transmitter

The 2-to-4 level converters are parallel-input

digital-to-analog converters (DACs).
The algorithm for the DAC is that the I or Q bit
determines the polarity of the output analog
signal (logic 1 = +V and logic 0=V), whereas
the C or C bit determines the magnitude (logic
1=1.307V and logic 0=0.541V).
With two magnitudes and two polarities, four
different output conditions are possible.

8 PSK Modulator

fb/3

2-to-4
2-to-4 level
level
converter
converter

PAM

Product
Product
modulator
modulator

sin ctBandpass
Bandpass

8-PSK
output

filter
filter

Input
data fb

Q I

fb/3

Reference
oscillator

Linear
Linear
summer
summer

+90
+90

fb/3

Bandpass
Bandpass
filter
filter

cos ct

C
2-to-4
2-to-4 level
level
converter
converter

Bandpass
Bandpass
filter
filter

PAM

Product
Product
modulator
modulator
I/Q

Output

- 0.541 V

- 1.307 V

+ 0.541
V

+ 1.307
V

cos wct
Q I C
100

Q I C
110

8-PSK Modulator

Q I C
101

Truth table
Binary
input

Q
0
0
0
1
0
0
0
1
1
0
1
1
1
0
1
1

C
0
0
1
1
0
0
1
1

8-PSK
Outpu
t
phase

Phasor
Diagram

Q I C
111

- sin wct

sin wct

Q I C
001

Q I C
011

112.
Q I C
5
000
157.
5
100
-67.5
-22.5
+112
.5
Constellation Diagram 101
+157
.5
+67.
- sin wct
5
+22.
5

- cos wct

Q I C
010

cos wct
110

111

sin wct

001

011

000

010
- cos wct

Example:

For a tribit input of Q=0, I=0, and C=0 (000),

determine the output phase for the 8-PSK
modulator.

Inputs:
I = (0.541)(sin wct) = 0.541 sin wct
Q = (1.307)(sin wct) = 1.307 cos wct
Summer output = 0.541 sin wct 1.307 cos wct
= 1.41sin (wct 112.5)

Bandwidth consideration of an 8-PSK

modulator

Binary
Input
data fb

C channel
fb/3 1/0
Q

fb/3
To Q channel
2-to-4 level
converter

2-to-4
level
converte
r

fb/3
C channel

PAM

Balance
d
modula
tor
sin ct

2 phases/2 voltage levels

sin ct
1.307 V
0.541 V

Example:
For an 8-PSK modulator with an input data rate
(fb) equal to 10 Mbps and a carrier frequency of
70 MHz, determine double-sided Nyquist (fN)
and the baud. Use the 8-PSK block diagram as
the modulator model.
Answer:
fbC = fbQ = fbI = 10 Mbps/3 = 3.33 Mbps
fa = fbC / 2 or fbQ / 2 or fbI / 2 = 1.667 Mbps

4-level PAM

8-PSK Receiver
I channel

I
Product
Product
Detecto
Detecto
rr

Analog-toAnalog-to-

digital
digital
converter
converter

sin wct
Bandpa
Bandpa
ss
ss
filter
filter

Power
Power
Splitt
Splitt
er
er

QIC output
data bits

Carrier
Carrier
recovery
recovery

8-PSK
Input

o
+90
+90o

cos wct

Q channel

Product
Product
Detecto
Detecto
rr

C
Analog-toAnalog-todigital
digital
converter
converter

4-level PAM

Clock
Clock
recovery
recovery

8-PSK Receiver

The power splitter directs the input 8-PSK signal to the I

and Q product detectors and the carrier recovery circuit.
The carrier recovery circuit reproduces the original
reference oscillator signal. The incoming 8-PSK signal is
mixed with the recovered carrier in the I product
detector and with a quadrature carrier in the Q product
detector.
The outputs of the product detectors are 4-level PAM
signals that are fed to the 4-to-2 level analog-to-digital
converters (ADCs).
The outputs from the I channel 4-to-2 level converter
are the I and C bits, whereas the outputs from the Q
channel 4-to-2 level converters are the Q and C bits.

8-PSK Receiver

The parallel-to-serial logic circuit converts the

I/C and Q/C bit pairs to serial I, Q, and C output
data streams.

16-PSK

is an M-ary encoding technique where M=16

and N=4.

Four bits (called quadbits) are combined,

producing 16 different output phases.
The minimum bandwidth and baud equal to
one-fourth the bit rate (fb).

16-PSK

0100

cos wct

0011
0010

0101

Truth table

0001

0110

Bit
Code

Phase

Bit Code

Phase

0000

11.25

1000

191.25

0111

0001

33.75

1001

213.75

- sin wct

0010

56.25

1010

236.25

0011

78.75

1011

258.75

0100

101.25

1100

281.25

0101

123.75

1101

303.75

0110

146.25

1110

326.25

0111

168.75

1111

348.75

0000
sin wct

1000

1111
1110

1001

1101

1010
1011

1100
- cos wct

Constellation diagram

Quadrature Amplitude
Modulation (QAM)

is a form of digital modulation similar to PSK

except the digital information is contained in
both the amplitude and phase of the
transmitted carrier

8-QAM
is an M-ary encoding techniques where M=8
Unlike 8-PSK, the output signal is not constantamplitude signal

8-QAM Transmitter

the only difference from the 8-PSK transmitter

is the omission of the inverter between the C
channel and the Q product modulator

the I and Q bits determined the polarity of the

PAM signal at the output of the 2-to-4 level
converters, and the C channel determines the
magnitude (See Truth Table of 2-to-4 level
converter)

8-QAM Transmitter
2-to-4
2-to-4
level
level
convert
convert
er
er
Bit
splitter

Input
Data fb

Q I

PAM

Product
Product
modulat
modulat
or
or

Referenc
Referenc
e
e
oscillato
oscillato
rr

Linear
Linear
summe
summe
rr

Bandpas
Bandpas
s
s
filter
filter

8-QAM
output

o
+90
+90o

2-to-4
2-to-4
level
level
convert
convert
er
er

PAM

Product
Product
modulat
modulat
or
or

Truth table 2-4

level converter
I/Q

Output

- 0.541 V

- 1.307 V

+ 0.541
V

+ 1.307
V

Example:

Assume the tribit input Q=0, I=0, and C=0 (000).

The inputs to the I channel 2-to-4 level converter are
I=0 and C=0, the output is 1 0.541V. The inputs to the
Q channel 2-to-4 level converter are Q=0 and C=0, The
output is 0.541 V.
The output of the I channel product modulator is
I = (0.541)(sin wct) = 0.541 sin wct
The output of the Q channel product modulator is
Q = (0.541)(cos wct) = 0.541 cos wct
The summer output is
8-QAM output = 0.541 sin wct 0.541 cos wct
= 0.765 sin (sin wct 135)

Truth table

8-QAM Modulator:

Phasor Diagram

101

cos wct

Binary Input

8-QAM output

QIC

Amplitude

000

0.765 V

-135

001

1.848 V

-135

010

0.765 V

-45

011

1.848 V

-45

100

0.765 V

+135

101

1.848 V

+135

110

0.765 V

+45

111

1.848 V

+45

Constellation
Diagram cos w t
c
1 01

111 (1.848 V)

100

100

110 (0.765 V)

- sin wct

1 11
110

- sin wct

sin wct
0o Reference
000

010

sin wct
000

010

001

0 11
- cos wct

011

0 01

- cos wct

Phase

8-QAM Receiver

Almost identical to the 8-PSK receiver

The difference are the PAM levels at the output of the
product detectors and the binary signals at the output
of the ADC converters
Because there are two transmit amplitudes possible,
the four demodulated PAM levels in 8-QAM are different
form those in 8-PSK. Therefore, the conversion factor
for the ADC converters must also be different.
With 8-QAM the binary output signals form the I
channel ADC converter are the I and C bits, and the
binary output signals from the Q channel ADC converter
are the Q and C bits.

4-level PAM

8-QAM Receiver
I channel

I
Product
Product
Detecto
Detecto
rr

Analog-toAnalog-to-

digital
digital
converter
converter

sin wct
Bandpa
Bandpa
ss
ss
filter
filter
8-QAM
Input

Power
Power
Splitt
Splitt
er
er

QIC output
data bits

Carrier
Carrier
recovery
recovery

o
+90
+90o

cos wct

Q channel

Product
Product
Detecto
Detecto
rr

Clock
Clock
recovery
recovery

C
Analog-toAnalog-todigital
digital
converter
converter

4-level PAM

16-QAM

is an M-ary system where M = 16 and n = 4.

16-QAM Transmitter
The input binary data are divided into four channels:
I, I, Q, and Q.
The bit rate in each channel is equal to of the input
bit rate (fb / 4).
The I and Q bits determine the polarity at the output
of the 2-to-4 level converters (a logic 1 = + and a
logic 0 = ).
The I and Q bits determine the magnitude (a logic 1
= 0.821 V and a logic 0 = 0.22 V).

16-QAM Transmitter

The output of each 2-to-4 level converters generate 4 possble

PAM signal: 0.22 V, +0.22 V, 0.821 V and +0.821 V.
The PAM signals modulated the in-phase and quadrature
carriers in the product modulators. Four outputs are possible
for each product modulator;
a. For the I product modulator
0.22 sin wct, +0.22 sin wct, 0.821 sin wct and +0.821 sin wct
b. For the Q product modulator
0.22 cos wct, +0.22 cos wct, 0.821 cos wct and +0.821 cos
wc t
The linear summer combines the outputs from the I and Q
channel product modulators and produces 16 output
conditions necessary for 16-QAM.

16-QAM Transmitter
PAM

2-to-4
2-to-4

Balance
Balance
modulat
modulat
or
or

level
level
convert
convert
er
er
Bit splitter
Binary
Input
Data fb

Q
Q

Q
Q

II

Referenc
Referenc
e
e
oscillato
oscillato
rr

I
I

Linear
Linear
summe
summe
rr

Bandpas
Bandpas
s
s
filter
filter

16-QAM
output

o
+90
+90o

2-to-4
2-to-4
level
level
convert
convert
er
er

Balance
Balance
modulat
modulat
or
or

PAM
I

Output

Output

0.22 V

0.22 V

0.821
V

0.821
V

+0.22 V

+0.22 V

+0.821

+0.821

Example:

Assume a quadbit input 0000(I=0, I=0, Q=0, and

Q0).
The inputs to the I channel 2-to-4 level converter
are I=0 and I=0. The inputs to the I channel 2-to4 level converter are I=0 and I=0.
The output of the I channel product modulator is
I = (0.22)(sin wct) = 0.22 sin wct
The output of the Q channel product modulator is
Q = (0.22)(cos wct) = 0.22 cos wct
Summer output = 0.22 sin wct 0.22 cos wct
or output = 0.311 (sin wct 135)

16-QAM Modulator:
Truth table
Binary
Input
Q Q
I

16-QAM output
I

Amplitude

Phase

0
0

0
0

0
0

0
1

0.311 V
0.850 V

-135
-165

0
0

0
0

1
1

0
1

0.311 V
0.850 V

-45
-15

0
0

1
1

0
0

0
1

0.850 V
1.161 V

-105
-135

0
0

1
1

1
1

0
1

0.850 V
1.161 V

-75
-45

1 0 0 0
1 0 0 1

0.311 V
0.850 V

+135
+165

1 0 1 0
1 0 1 1

0.311 V
0.850 V

+45
+15

1 1
1 1

0 0
0 1

0.850 V
1.161 V

+105
+135

1 1
1 1

1 0
1 1

0.850 V
1.161 V

+75
+45

16-QAM Modulator:

Phasor Diagram
cos wct 0.850

1.161

0.311
- sin wct

1101

1100

1001

1000

0001

0000

1110

1010

1111

1011

sin wct
0o Reference

- cos wct

0101

0100

0010

0011

0110

0111

Constellation
Diagram

Example:

Assume a quadbit input 0000(I=0, I=0, Q=0, and

Q0).
The inputs to the I channel 2-to-4 level converter
are I=0 and I=0. The inputs to the I channel 2-to4 level converter are I=0 and I=0.
The output of the I channel product modulator is
I = (0.22)(sin wct) = 0.22 sin wct
The output of the Q channel product modulator is
Q = (0.22)(cos wct) = 0.22 cos wct
Summer output = 0.22 sin wct 0.22 cos wct
or output = 0.311 (sin wct 135)

Bandwidth Consideration of a 16QAM Modulator

2-to-4
2-to-4
level
level
convert
convert
er
er

PAM

Balance
Balance
modulat
modulat
or
or

Bit splitter
Binary
Input
Data fb

Q
Q

Q
Q

II

To Q-channel
2-to-4 level
converter

I
I

Bandwidth = fb / 4
Baud = fb / 4

2 phases/4 voltages
sin wct
0.22 V
0.821 V

Example 1:

For a 16-QAM modulator with an input data rate (fb)

equal to 10 Mbps and a carrier frequency of 70 MHz,
determine
the
minimum
double-sided
Nyquist
frequency (fN) and the baud.

Solution:
fbI = fbI = fbQ = fbQ = fb / 4 = 10 Mbps / 4 = 2.5 Mbps
fa = fbI / 2 = 2.5 Mbps / 2 = 1.25 MHz
output = (sin 2fat)(sin 2fct)
output = cos 2(fa - fc)t cos 2(fa + fc)t
output = cos 2 (68.75 MHz)t cos 2(71.25 MHz)t
B = 71.25 MHz 68.75 MHz = 2.5 MHz

Example 2:

For the following modulation schemes, construct

a table showing the number of bit encoded,
number
of
output
conditions,
minimum
bandwidth, and baud for an information of 12
kbps: QPSK, 8-PSK, 8-QAM, 16-PSK, and 16-QAM.

Modulatio
Answer:

Bandwidth(Hz
)

Baud

QPSK

6000

6000

8-PSK

4000

4000

8-QAM

4000

4000

16-PSK

16

3000

3000

16-QAM

16

3000

3000

ASK, FSK, PSK, and QAM

Summary
Modulation

Encoding
Scheme

Outputs
Possible

Minimum
Bandwidth

Baud

ASK

Single bit

fb

fb

FSK

Single bit

fb

fb

BPSK

Single bit

fb

fb

QPSK

Dibits

fb / 2

fb / 2

8-PSK

Tribits

fb / 3

fb / 3

8-QAM

Tribits

fb / 3

fb / 3

16-PSK

Quadbits

16

fb / 4

fb / 4

16-QAM

Quadbits

16

fb / 4

fb / 4

32-PSK

Five bits

32

fb / 5

fb / 5

32-QAM

Five bits

32

fb / 5

fb / 5

64-PSK

Six bits

64

fb / 6

fb / 6

64-QAM

Six bits

64

fb / 6

fb / 6

128-PSK

Seven bits

128

fb / 7

fb / 7

128-QAM

Seven bits

128

fb / 7

fb / 7

Bandwidth Efficiency
Bandwidth Efficiency / Information Density / Spectral
Density
often used to compare the performance of one digital
technique to another
is the ratio of the transmission bit rate to the minimum
bandwidth required for a particular modulation scheme

in bits / cycle

Example 3:

For an 8-PSK system, operating with an

information bit rate of 24 kbps, determine (a)
baud, (b) minimum bandwidth, and (c)bandwidth
efficiency.

Answer:
Baud = 8000
B = 8000 MHz

Example 4:

For a 16-PSK and a transmission system with 10

kHz bandwidth, determine the maximum bit rate.

Answer:
bit rate = 4 x 10, 000 = 40, 000 bps

Squaring loop carrier recovery circuit

for a BPSK Receiver
VCO Out

BPSK
Input

Bandpa
Bandpa
ss
ss
filter
filter

Squarer
Squarer

PLL
PLL

Frequenc
Frequenc
y
y
divider
divider

Recovered
Carrier

Costas Loop Carrier Recovery Circuit

I
Balance
d
Modulat
X
or

LPF

I
Channel

Error
Voltage

PSK
Input

Power
splitt
er

VCO

Loop
filter

+90o

X
Q
Balanced
Modulator

LPF
Q Channel

Balance
d
Product
Detector

Remodulator Loop Carrier Recovery

Balanced
CircuitBalance
d
Modulator
PSK
Input

Modulat
or X

LPF

I
Channel

+90o

VCO

Loop
filter

X
Balance
d
Modulat
or