Input/Output Organization

Lecture 34

Peripheral Devices

Input Devices
Keyboard
Optical input devices
- Card Reader
- Paper Tape Reader
- Bar code reader
- Digitizer
- Optical Mark Reader
Magnetic Input Devices
- Magnetic Stripe Reader
Screen Input Devices
- Touch Screen
- Light Pen
- Mouse
Analog Input Devices

Output Devices
Card Puncher, Paper Tape Puncher
CRT
Printer (Impact, Ink Jet, Laser, Dot Matrix)
Plotter
Analog
Voice

Input/Output Organization
Lecture 34

I/O Interface

Provides a method for transferring information between internal

storage (such as memory and CPU registers) and external I/O
devices
Resolves the differences between the computer and peripheral
devices
Peripherals - Electromechanical Devices
CPU or Memory - Electronic Device

Data Transfer Rate

Peripherals - Usually slower
CPU or Memory - Usually faster than peripherals
Some kinds of Synchronization mechanism may be needed

Unit of Information
Peripherals Byte, Block,
CPU or Memory Word

Data representations may differ

Input/Output Organization
Lecture 34

I/O Bus and Interface

I/O bus

Data
Address
Control

Processor

Interface

Interface

Interface

Interface

Keyboard
and
display
terminal

Printer

Magnetic
disk

Magnetic
tape

Each peripheral has an interface module associated with it

Interface
- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller
- Synchronizes the data flow and supervises
the transfer rate between peripheral and CPU or Memory
Typical I/O instruction
Op. code

Device address

Function code
(Command)

Input/Output Organization
Lecture 34

I/O Bus and Memory Bus

Functions of Buses
MEMORY BUS is for information transfers between CPU and the MM
I/O BUS is for information transfers between CPU and I/O devices through
their I/O interface
Many computers use a common single bus system for both memory and
I/O interface units
- Use one common bus but separate control lines for each function
- Use one common bus with common control lines for both functions

Some computer systems use two separate buses, one to communicate

with memory and the other with I/O interfaces
- Communication between CPU and all interface units is via a common I/O Bus
- An interface connected to a peripheral device may have a number of data
registers , a control register, and a status register
- A command is passed to the peripheral by sending to the appropriate interface
register
- Function code and sense lines are not needed (Transfer of data, control,
and status information is always via the common I/O Bus)

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Lecture 34

Isolated vs. Memory Mapped I/O

Isolated I/O
- Separate I/O read/write control lines in addition to memory read/write
control lines
- Separate (isolated) memory and I/O address spaces
- Distinct input and output instructions
Memory-mapped I/O
- A single set of read/write control lines
(no distinction between memory and I/O transfer)
- Memory and I/O addresses share the common address space
-> reduces memory address range available
- No specific input or output instruction
-> The same memory reference instructions can
be used for I/O transfers
- Considerable flexibility in handling I/O operations

Input/Output Organization
Lecture 34

I/O Interface

Bidirectional

Chip select
Register select
Register select
I/O read

I/O write

I/O data

Port B
register

I/O data

Bus
buffers

data bus

CPU

Port A
register

CS
RS1
RS0
RD

Control
register

Timing
and
Control

Status
register

WR
CS RS1 RS0
0
x
x
1
0
0
1
0
1
1
1
0
1
1
1

Control

I/O
Device

Status

Register selected
None - data bus in high-impedence
Port A register
Port B register
Control register
Status register

Programmable Interface
- Information in each port can be assigned a meaning depending on the mode of operation of the
I/O device
Port A = Data; Port B = Command; Port C = Status
- CPU initializes(loads) each port by transferring a byte to the Control Register
Allows CPU can define the mode of operation of each port
Programmable Port: By changing the bits in the control register, it is possible to change the
interface characteristics

Input/Output Organization
Lecture 35

Asynchronous Data Transfer

Synchronous and Asynchronous Operations

Synchronous - All devices derive the timing information from common clock line
Asynchronous - No common clock

Asynchronous Data Transfer

Asynchronous data transfer between two independent units requires that
control signals be transmitted between the communicating units to
indicate the time at which data is being transmitted

Two Asynchronous Data Transfer Methods

Strobe pulse
- A strobe pulse is supplied by one unit to indicate the other unit when the
transfer has to occur
Handshaking
- A control signal is accompanied with each data being transmitted to
indicate the presence of data
- The receiving unit responds with another control signal to acknowledge
receipt of the data

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Lecture 35

Strobe Control

* Employs a single control line to time each transfer

* The strobe may be activated by either the source or the destination
unit
Source-Initiated Strobe
for Data Transfer

Destination-Initiated Strobe
for Data Transfer

Block Diagram
Source
unit

Block Diagram
Data bus
Strobe

Destination
unit

Source
unit

Data bus
Strobe

Timing Diagram
Data

Strobe

Valid data

Valid data
Data

Strobe

Destination
unit

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Lecture 35

Handshaking

Strobe Methods
Source-Initiated
The source unit that initiates the transfer has no way of
knowing whether the destination unit has actually received data
Destination-Initiated
The destination unit that initiates the transfer no way of
knowing whether the source has actually placed the data on the bus

To solve this problem, the HANDSHAKE method

introduces a second control signal to provide a Reply to
the unit that initiates the transfer

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Source Initiated Transfer using

Handshaking
Block Diagram
Source
unit

Timing Diagram

Data valid
Data accepted

Destination
unit

Valid data

Data bus

Data valid

Data accepted

Sequence of Events

Source unit

Destination unit

Place data on bus.

Enable data valid.
Accept data from bus.
Enable data accepted
Disable data valid.
Invalidate data on bus.
Disable data accepted.
Ready to accept data
(initial state).

* Allows arbitrary delays from one state to the next

* Permits each unit to respond at its own data transfer rate
* The rate of transfer is determined by the slower unit

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Destination Initiated Transfer using

Handshaking
Block Diagram
Source
unit

Data valid
Ready for data

Destination
unit

Ready for data

Data valid

Data bus

Sequence of Events

Source unit
Place data on bus.
Enable data valid.

Disable data valid.

Invalidate data on bus
(initial state).

Valid data

Destination unit
Ready to accept data.
Enable ready for data.

Accept data from bus.

Disable ready for data.

* Handshaking provides a high degree of flexibility and reliability because the successful
completion of a data transfer relies on active participation by both units
* If one unit is faulty, data transfer will not be completed -> Can be detected by means of a timeout
mechanism

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Asynchronous Serial Transfer

Asynchronous serial transfer
Synchronous serial transfer
Asynchronous parallel transfer
Synchronous parallel transfer

Four Different Types of Transfer

Asynchronous Serial Transfer

- Employs special bits which are inserted at both ends of the character code
- Each character consists of three parts; Start bit; Data bits; Stop bits.

1
Start

Character bits

1
Stop
bits

A character can be detected by the receiver from the knowledge of 4 rules;

- When data are not being sent, the line is kept in the 1-state (idle state)
- The initiation of a character transmission is detected by a Start Bit , which is always a 0
- The character bits always follow the Start Bit
- After the last character , a Stop Bit is detected when the line returns to the 1-state for at
least 1 bit time

The receiver knows in advance the transfer rate of the bits and the number of
information bits to expect

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Universal Asynchronous Receiver Transmitter

A typical asynchronous communication interface available as an IC

Bidirectional
data bus

CS
RS

I/O read
I/O write

RD
WR

Timing
and
Control

Internal Bus

Chip select

Bus
buffers

Transmitter
register

Shift
register

Control
register

Transmitter
control
and clock

Status
register

Receiver
control
and clock

Receiver
register

Shift
register

Transmit
data

Transmitter
clock

Receiver
clock
Receive
data

CS
0
1
1
1
1

RS
x
0
1
0
1

Oper. Register selected

x
None
WR
Transmitter register
WR
Control register
RD
Receiver register
RD
Status register

Transmitter Register
- Accepts a data byte(from CPU) through the data bus
- Transferred to a shift register for serial transmission
Receiver
- Receives serial information into another shift register
- Complete data byte is sent to the receiver register
Status Register Bits
- Used for I/O flags and for recording errors
Control Register Bits
- Define baud rate, no. of bits in each character, whether to generate and check parity, and
no. of stop bits

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Modes of Transfer Programmed I/O

3 different Data Transfer Modes between the central

computer(CPU or Memory) and peripherals;

Program-Controlled I/O
Interrupt-Initiated I/O
Direct Memory Access (DMA)

Program-Controlled I/O(Input Dev to CPU)

Interface

Data bus
Address bus
CPU

I/O bus

Data register

I/O read
I/O write

Status
register

Data valid

I/O
device

Data accepted

Read status register

Check flag bit

flag

=0

=1
Read data register
Transfer data to memory

no

Operation
complete?
yes
Continue with
program

Polling or Status Checking

Continuous CPU involvement

CPU slowed down to I/O speed
Simple
Least hardware

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Modes of Transfer Interrupted I/O & DMA

Interrupt Initiated I/O

- Polling takes valuable CPU time
- Open communication only when some data has to be passed -> Interrupt.
- I/O interface, instead of the CPU, monitors the I/O device
- When the interface determines that the I/O device is ready for data
transfer, it generates an Interrupt Request to the CPU
- Upon detecting an interrupt, CPU stops momentarily the task it is doing,
branches to the service routine to process the data transfer, and then
returns to the task it was performing
DMA (Direct Memory Access)
- Large blocks of data transferred at a high speed to or from high speed
devices, magnetic drums, disks, tapes, etc.
- DMA controller Interface that provides I/O transfer of data directly to and
from the memory and the I/O device
- CPU initializes the DMA controller by sending a memory address and the
number of words to be transferred
- Actual transfer of data is done directly between the device and memory
through DMA controller
-> Freeing CPU for other tasks

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Priority Interrupts

Priority
- Determines which interrupt is to be served first
when two or more requests are made simultaneously
- Also determines which interrupts are permitted to
interrupt the computer while another is being serviced
- Higher priority interrupts can make requests while
servicing a lower priority interrupt
Priority Interrupt by Software(Polling)
- Priority is established by the order of polling the devices(interrupt sources)
- Flexible since it is established by software
- Low cost since it needs a very little hardware
- Very slow
Priority Interrupt by Hardware
- Require a priority interrupt manager which accepts
all the interrupt requests to determine the highest priority request
- Fast since identification of the highest priority
interrupt request is identified by the hardware
- Fast since each interrupt source has its own interrupt vector to access
directly to its own service routine

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Hardware Priority Interrupts Daisy

Chain
VAD 2

VAD 1
Device 1
PI

PO

Device 2
PI

PO

VAD 3
Device 3
PI

PO

To next
device

Interrupt request

* Serial hardware priority function

* Interrupt Request Line
- Single common line
* Interrupt Acknowledge Line
- Daisy-Chain

INT

CPU
Interrupt acknowledge

INTACK

Interrupt Request from any device(>=1)

-> CPU responds by INTACK <- 1
-> Any device receives signal(INTACK) 1 at PI puts the VAD on the bus
Among interrupt requesting devices the only device which is physically closest
to CPU gets INTACK=1, and it blocks INTACK to propagate to the next device

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Parallel Priority Interrupts

Bus
Buffer

Interrupt register
Disk

I0

Printer

I1

Reader

Keyboard

Priority
I 2 encoder

I3

VAD
to CPU

0
Mask
register

1
2
3

IEN

IST

0
0
Enable
Interrupt
to CPU
INTACK
from CPU

IEN: Set or Clear by instructions ION or IOF

IST: Represents an unmasked interrupt has occurred. INTACK enables tristate Bus Buffer to load
VAD generated by the Priority Logic
Interrupt Register:
- Each bit is associated with an Interrupt Request from different Interrupt Source - different
priority level
- Each bit can be cleared by a program instruction
Mask Register:
- Mask Register is associated with Interrupt Register
- Each bit can be set or cleared by an Instruction

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Priority Encoder

Determines the highest priority interrupt when more than

one interrupts take place
Priority Encoder Truth table
Inputs
I0
1
0
0
0
0

I1
d
1
0
0
0

I2
d
d
1
0
0

I3
d
d
d
1
0

Outputs
x y IST
0
0
1
1
d

0
1
0
1
d

1
1
1
1
0

Boolean functions

x = I0' I1'
y = I0' I1 + I0 I2
(IST) = I0 + I1 + I2 + I3

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Interrupt Cycle

At the end of each Instruction cycle

- CPU checks IEN and IST
- If IEN IST = 1, CPU -> Interrupt Cycle
SP SP - 1
M[SP] PC
INTACK 1
PC VAD
IEN 0
Go To Fetch

Decrement stack pointer

Push PC into stack
Enable interrupt acknowledge
Transfer vector address to PC
Disable further interrupts
to execute the first instruction
in the interrupt service routine

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Initial and Final Operations

7
3

VAD=00000011

KBD
interrupt

JMP DISK

JMP PTR

JMP RDR

JMP KBD
Main program

1
749
750
11
2

DISK

Program to service
magnetic disk

PTR

Program to service
line printer

RDR

Program to service
character reader

current instr.
Stack

5
256
750

KBD

Disk
interrupt

Program to service
keyboard
255
256
6

10
9
Initial and Final Operations
Each interrupt service routine must have an initial and final set of
operations for controlling the registers in the hardware interrupt system

Initial Sequence
[1] Clear lower level Mask reg. bits
[2] IST <- 0
[3] Save contents of CPU registers
[4] IEN <- 1
[5] Go to Interrupt Service Routine

Final Sequence
[1] IEN <- 0
[2] Restore CPU registers
[3] Clear the bit in the Interrupt Reg
[4] Set lower level Mask reg. bits
[5] Restore return address, IEN <- 1

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Direct Memory Access

* Block of data transfer from high speed devices, Drum, Disk, Tape
* DMA controller - Interface which allows I/O transfer directly between Memory and Device, freeing
CPU for other tasks
* CPU initializes DMA Controller by sending memory address and the block size (number of words)

CPU bus signals for DMA transfer

BR

Bus granted

BG

CPU

Data bus
Read
Write

Data bus

DMA select

Block diagram of DMA controller

Data bus
buffers

DS
RS

Read

RD

Write

WR

Bus request

BR

Bus grant

BG

Interrupt

Control
logic

Interrupt

Address bus
buffers
Internal Bus

Bus request

ABUS
DBUS
RD
WR

Address register
Word count register
Control register

DMA request
DMA acknowledge

to I/O device

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DMA I/O Operation

Starting an I/O
- CPU executes instruction to
Load Memory Address Register
Load Word Counter
Load Function(Read or Write) to be performed
Issue a GO command
Upon receiving a GO Command DMA performs I/O
operation as follows independently from CPU
Input
[1] Input Device <- R (Read control signal)
[2] Buffer(DMA Controller) <- Input Byte; and
assembles the byte into a word until word is full
[4] M <- memory address, W(Write control signal)
[5] Address Reg <- Address Reg +1; WC(Word Counter) <- WC - 1
[6] If WC = 0, then Interrupt to acknowledge done, else go to [1]

Output
[1] M <- M Address, R
M Address R <- M Address R + 1, WC <- WC - 1
[2] Disassemble the word
[3] Buffer <- One byte; Output Device <- W, for all disassembled bytes
[4] If WC = 0, then Interrupt to acknowledge done, else go to [1]

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Cycle Stealing

While DMA I/O takes place, CPU is also executing instructions

DMA Controller and CPU both access Memory -> Memory Access Conflict
Memory Bus Controller
- Coordinating the activities of all devices requesting memory access
- Priority System
Memory accesses by CPU and DMA Controller are interwoven,
with the top priority given to DMA Controller
-> Cycle Stealing
Cycle Steal
- CPU is usually much faster than I/O(DMA), thus
CPU uses the most of the memory cycles
- DMA Controller steals the memory cycles from CPU
- For those stolen cycles, CPU remains idle
- For those slow CPU, DMA Controller may steal most of the memory
cycles which may cause CPU remain idle long time

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DMA Transfer
Interrupt
BG

Random-access
memory unit (RAM)

CPU

BR
RD

WR

Addr

Data

RD

WR

Addr

Data

Read control
Write control
Data bus
Address bus
Address
select
RD

WR

Addr

DMA ack.

DS
RS
BR
BG
Interrupt

Data

I/O
Peripheral
device

DMA
Controller
DMA request

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I/O Processor - Channel

Memory
unit

Memory Bus

Channel
- Processor with direct memory access capability that communicates with
I/O devices
- Channel accesses memory by cycle stealing
- Channel can execute a Channel Program
- Stored in the main memory
- Consists of Channel Command Word(CCW)
- Each CCW specifies the parameters needed by the channel to control
the I/O
devices and perform data transfer operations
- CPU initiates the channel by executing an channel I/O class instruction
and once initiated, channel operates independently of the CPU
Central
processing
unit (CPU)
Peripheral devices
PD
Input-output
processor
(IOP)

PD
I/O bus

PD

PD

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Channel CPU Communication

CPU operations

IOP operations

Send instruction
to test [Link]
Transfer status word
to memory
If status OK, then send
start I/O instruction
to IOP.

CPU continues with

another program

Request IOP status

Check status word

for correct transfer.
Continue

Access memory
for IOP program
Conduct I/O transfers
using DMA;
Prepare status report.
I/O transfer completed;
Interrupt CPU

Transfer status word

to memory location