INTERRUPTS AND EXCEPTIONS

Interrupts: a review
An interrupt is any service request that causes the CPU to stop its current execution stream and to execute an instruction stream that services the interrupt When the CPU finishes servicing the interrupt, it returns to the original execution stream at the point where it left off. Interrupt driven I/O for interfacing with on chip peripherals

Interrupt Constraints
Each interrupt source charaterised by
Minimum time interval between interrupts from the same source Maximum time it takes the CPU to execute interrupt sources handler

Servicing of interrupts must not be delayed beyond the limit imposed by the timing requirement of the source

BUS STRUCTURE

BUS
Bus is the mechanism by which the CPU communicates with memory and I/O devices Bus is not just a collection of wires Bus defines the protocol for communication

Bus (2)
Shared communication link single set of wires used to connect multiple subsystems A Bus is also a fundamental tool for composing large, complex systems
Processor Control Datapath Input

Memory
Output

What defines a bus?

Transaction Protocol
Timing and Signaling Specification

Bunch of Wires
Electrical Specification

Physical / Mechanical Characteristics the connectors

Address:
Data: Control:

Generic bus structure m

n

Generic Organization of a Bus

Control lines: Signal requests and acknowledgments Indicate what type of information is on the data lines Data lines carry information between the source and the destination: Data and Addresses
Address: special form of data

Complex commands

Bus Characteristics
Bus signals are usually tri-stated. Address and data lines may be multiplexed. Every device on the bus must be able to drive the maximum bus load:
Bus wires. Other bus devices.

Bus may include clock signal.

Timing is relative to clock.

Time Multiplexing
Share a single set of wires for multiple pieces of data Saves wires at expense of time
Master
data(15:0)

req

Servant
data(15:0)

Master
addr data

req

Servant
addr data

mux

demux

mux

demux

data(8)

addr/data

req data
15:8 7:0

req addr/data
addr data

data serializing

address/data muxing

Ref: Embedded Systems Design: A Unified Hardware/Software Introduction, Vahid/Givargis

Increasing the Bus Bandwidth

Non-multiplexed address and data lines:
Address and data can be transmitted in one bus cycle if separate address and data lines are available Cost: (a) more bus lines, (b) increased complexity

Data bus width:

By increasing the width of the data bus, transfers of multiple words require fewer bus cycles Cost: more bus lines

Block transfers:
Allow the bus to transfer multiple words in back-to-back bus cycles Only one address needs to be sent at the beginning The bus is not released until the last word is transferred Cost: (a) increased complexity (b) decreased response time for request

Advantages of Bus
Versatility:
New devices can be added easily

Low Cost:
A single set of wires is shared in multiple ways

Disadvantages of Bus
It creates a communication bottleneck
The bandwidth of the bus can limit the maximum I/O throughput

The maximum bus speed is largely limited by:

The length of the bus The number of devices on the bus The need to support a range of devices with:
Widely varying latencies Widely varying data transfer rates

Parallel communication
Multiple data, control, and possibly power wires One bit per wire High data throughput with short distances Typically used when connecting devices on same IC or same circuit board Bus must be kept short long parallel wires result in high capacitance values which requires more time to charge/discharge Data misalignment between wires increases as length increases Higher cost, bulky

Serial communication
Single data wire, possibly also control and power wires Words transmitted one bit at a time Higher data throughput with long distances Less average capacitance, so more bits per unit of time Cheaper, less bulky More complex interfacing logic and communication protocol Sender needs to decompose word into bits Receiver needs to recompose bits into word Control signals often sent on same wire as data increasing protocol complexity

Synchronous Bus
Includes a clock in the control lines A fixed protocol for communication that is relative to the clock Advantage: involves very little logic and can run very fast Disadvantages:
Every device on the bus must run at the same clock rate To avoid clock skew, they cannot be long if they are fast

Most processor-memory buses

Asynchronous Bus
Asynchronous Bus:
It is not clocked It can accommodate a wide range of devices It can be lengthened without worrying about clock skew It requires a handshaking protocol

Basic Protocol Concepts

A bus transaction includes two parts:
Issuing the command (and address) request Transferring the data action

Master is the one who starts the bus transaction by:

issuing the command (and address)

Slave is the one who responds to the address by:

Sending data to the master if the master ask for data Receiving data from the master if the master wants to send data

Bus Arbitration
One of the most important issues in bus design:
How is the bus reserved by a device that wishes to use it?

Master-slave arrangement:
Only the bus master can control access to the bus:
It initiates and controls all bus requests

A slave responds to read and write requests

The simplest system:

Processor is the only bus master All bus requests must be controlled by the processor Major drawback: the processor is involved in every transaction

Basic Transaction Protocols

Master req Servant Master req ack data data Servant

req data

1 2

3 4

req ack data

1 2

3 4

taccess
1. Master asserts req to receive data 1. Master asserts req to receive data

2. Servant puts data on bus within time taccess

3. Master receives data and deasserts req 4. Servant ready for next request

2. Servant puts data on bus and asserts ack

3. Master receives data and deasserts req 4. Servant ready for next request

Strobe protocol

Handshake protocol

Ref: Embedded Systems Design: A Unified Hardware/Software Introduction, Vahid/Givargis

A strobe/handshake combination
Master req wait data Servant

req wait
data

req wait

1 2 3

2 taccess

data taccess 1. Master asserts req to receive data

1. Master asserts req to receive data 2. Servant puts data on bus within time taccess (wait line is unused) 3. Master receives data and deasserts req 4. Servant ready for next request

2. Servant can't put data within taccess, asserts wait ack 3. Servant puts data on bus and deasserts wait 4. Master receives data and deasserts req 5. Servant ready for next request

Fast-response case

Slow-response case

Ref: Embedded Systems Design: A Unified Hardware/Software Introduction, Vahid/Givargis

The Daisy Chain

Device 1 Highest Priority Grant Bus Arbiter Grant

Advantage: simple
Device 2 Device N Lowest Priority Grant Release Request

wired-OR Disadvantages: Cannot assure fairness: A low-priority device may be locked out indefinitely The use of the daisy chain grant signal also limits the bus speed

Centralized Parallel Arbitration

Device 1 Device 2 Device N

Grant
Bus Arbiter

Req

Used in essentially all processor-memory busses and in high-speed I/O busses

Arbitration: Priority arbiter

Types of priority
Fixed priority
each peripheral has unique rank highest rank chosen first with simultaneous requests preferred when clear difference in rank between peripherals

Rotating priority (round-robin)

priority changed based on history of servicing better distribution of servicing especially among peripherals with similar priority demands

Arbitration using a priority arbiter

Microprocessor System bus Inta Int 3 Ireq1 Iack1 Ireq2 Iack2 6 5 Priority arbiter Peripheral1 Peripheral2 7

Ref: Embedded Systems Design: A Unified Hardware/Software Introduction, Vahid/Givargis

Direct memory access

Direct transfer of data by-passing CPU Using DMA controller
Separate single-purpose processor Microprocessor relinquishes control of system bus to DMA controller Microprocessor can meanwhile execute its regular program
No inefficient storing and restoring state due to ISR call Regular program need not wait unless it requires the system bus Harvard architecture processor can fetch and execute instructions as long as they dont access data memory if they do, processor stalls

Peripheral to memory transfer with DMA

1(a): P is executing its main program. It has already configured 3: DMA ctrl asserts Dreq to the DMA ctrl registers. request control of system bus. 4: After executing an instruction, P sees Dreq 5: (a) DMA ctrl asserted, releases the system asserts ack (b) bus, asserts Dack, and reads data from resumes execution. P stalls 0x8000 and (b) only if it needs the system bus writes that data to to continue executing. 0x0001. 7(a): P de-asserts Dack and resumes control of the bus. 6:. DMA deasserts Dreq and ack completing handshake with P1. 1(b): P1 receives input data in a register with address 0x8000.

2: P1 asserts req to request servicing by DMA ctrl.

7(b):

P1 de-asserts req.

Multilevel bus architectures

One bus for all communication
Peripherals would need high-speed, processorspecific bus interface
excess gates, power consumption, and cost; less portable
Microprocessor Cache Memory controller DMA controller

Processor-local bus

Peripheral

Peripheral

Peripheral

Bridge

Too many peripherals slows down bus

Peripheral bus

Multi-level Buses
Processor-local bus
High speed, wide, most frequent communication Connects microprocessor, cache, memory controllers, etc.

Peripheral bus
Lower speed, narrower, less frequent communication Typically industry standard bus (ISA, PCI) for portability

Bridge
Single-purpose processor converts communication between busses

Parallel protocol: PCI Bus

PCI Bus (Peripheral Component Interconnect)
High performance bus originated at Intel in the early 1990s Standard adopted by industry and administered by PCISIG (PCI Special Interest Group) Interconnects chips, expansion boards, processor memory subsystems Data transfer rates of 127.2 to 508.6 Mbits/s and 32-bit addressing Synchronous bus architecture Multiplexed data/address lines

PCI Bus Architecture

Ref: IEEE Computer, 1999 Weiss & Finkelstein

PCI Read/Write Transactions

All signals sampled on rising edge Centralized Parallel Arbitration
overlapped with previous transaction

All transfers are (unlimited) bursts Address phase starts by asserting FRAME# Next cycle initiator asserts cmd and address

PCI Read/Write Transactions

Data transfers happen on when
IRDY# asserted by master when ready to transfer data TRDY# asserted by target when ready to transfer data transfer when both asserted on rising edge

FRAME# de-asserted when master intends to complete only one more data transfer

Bridge
A bridge is a slave on the fast bus and master of the slow bus Takes command from the fast bus on which it is slave Issues commands on the slow bus Returns results from slow bus to fast bus Also functions as protocol translator

Serial Buses

Serial Protocol
Used for moving data quickly from one device to another Serial protocols like I2C & SPI are meant for short distances inside the box
Low complexity Low cost

Serial Intefaces
USB, IEEE 1394, IrDA

Recap: USB bus protocol

Polled bus, all transfers initiated by host. Basic transaction:
Host sends token packet:
Type and direction. USB device number. Endpoint number (subdevice).

Data transfer packet. Acknowledge packet.

Bus Protocol
data transfer

token

Type of transaction Direction of trans. handshake USBdevice address

Host controller initiates data transfer by generating token packet Data transferred Handshake packet for completion

Attach and Remove of USB Devices

Host
Enable port allocate Remove USB address upstream port indicato indicato disable r r

port

Hub
port

port

device

USB Organization

USB Hubs
Hubs are bridges
Increase the logical and physical fan-out of the network.
A hub has a single upstream connection Many downstream connections.

Hubs are themselves USB devices Hubs detect topology changes due insertion/deletion of devices. They also source power to the USB network