PIC16C7X
8 BIT MICROCONTROLLERS WITH A/D CONVERTERS
Core Features of PIC16C7X
High performance RISC (Reduced Instruction Set Computing) CPU 35 single word instructions 20MHz clock input internally divided by 4 200ns instruction cycle Harvard architecture In built Program Memory
PIC16C72 PIC16C73/73A PIC16C74/74A PIC16C76/77 2K X 14 words 4K X 14 words 4K X 14 words 8K X 14 words
In built Data Memory
PIC16C72 128 X 8 PIC16C73/73A/74/74A 192 X 8 PIC16C76/77 368 X 8 External & Internal interrupt capability
8 level deep stack Direct, Indirect & Relative addressing modes Power saving SLEEP mode Power On Reset (POR) PWRT, OST, WDT Programmable Code protection
Peripheral Features of PIC16C7X
I/O pins
PIC16C72/73/73A/76 PIC16C74/74A/77 22 pins (Ports A, B, C) 33 pins (Ports A, B, C, D, E)
2 Capture/Compare/PWM Modules 3 Timer Modules A/D Channels
PIC16C72/73/73A/76 PIC16C74/74A/77 5 channels 8 channels
Serial Communication SPI, I2 C, USART Brown Out Reset except in PIC16C73/74 Interrupt Sources
PIC16C72 PIC16C73/73A/76 PIC16C74/74A/77 8 sources 11 sources 12 sources
8 bits wide Parallel Slave Port available in PIC16C74/74A/77
Architecture of PIC16C72
Architecture of PIC16C73/73A/76
Architecture of PIC16C74/74A/77
Clocking Scheme
Clock input is internally divided by 4 (Q1, Q2, Q3 and Q4) each of 5MHz. PC is incremented for every Q1 Instruction is latched for every Q4
Stack & Program Memory Organization
PIC16C72 PIC16C73/73A/74/74A
PIC16C76/77 Program Memory & Stack
Data Memory Organization
Multiple bank organization with General Purpose registers and Special Purpose registers Each bank capacity 128 bytes (00 7FH ) General Purpose registers (20H - 7FH ) Special Purpose registers (00 1FH) Banks are selected using RP1 & RP0 in status register
Data Memory
PIC16C72 Register File Map
PIC16C73/73A/74/74A Register File Map
PIC16C76/77 Data memory
Special Function Registers
PORT A / TRIS A 6 bits wide Setting a bit in Data Direction Register TRISB hi-impedance input mode Clearing a bit in TRIS B output mode PORT A is multiplexed with analog inputs Operation of each pin is selected by clearing or setting ADCON1 register
RA0/AN0 Input / Output or Analog Input RA1/AN1 Input / Output or Analog Input RA2/AN2 Input / Output or Analog Input RA3/AN3/Vref Input / Output or Analog Input or V reference RA4/T0CK1 Input / Output or External Clock input for Timer 0 RA5/AN4/SS Input / Output or Analog Input or slave select input for SSP
PORT B 8 bit bidirectional port
Data Direction Register TRIS B Setting a bit in Data Direction Register TRISB hiimpedance input mode Clearing a bit in TRIS B output mode Port B pins have a weak internal pull up. The pull ups are enabled by RBPU in OPTION register. The pins can be programmed as input or output.
PORT C 8 bit bidirectional port Data Direction Register TRIS C Each pin can be configured as I/O using TRIS C register Peripheral functions are multiplexed with Port C
RC0/T1OSO/T1CK1 I/O or Timer 1 Oscillator Output or Timer 1 Clock input RC1/T1OSI/CCP2 I/O or Timer 1 Oscillator input or Capture2 input, Compare2 output, PWM2 output RC2/CCP1 - I/O or Capture1 input, Compare1 output, PWM1 output RC3/SCK/SCL I/O or Synchronous serial clock for both SPI and I2C modes RC4/SDI/SDA I/O or SPI Data input in SPI mode or data I/O in I2C mode RC5/SDO I/O or SSP data output RC6/TX/CK - I/O or USART asynchronous transmit or USART synchronous clock RC7/RX/DT - I/O or USART asynchronous receive or USART synchronous clock
Some peripherals may override TRISC. So, TRISC destination should be avoided
PORT D applicable to PIC16C74/74A/77 Data Direction Register - TRISD Can be programmed as Input or Output Configured as 8 bit wide Microprocessor Parallel Slave Port The PSP mode can be selected by setting bit 4 in TRISE register
PORT E applicable to PIC16C74/74A/77 Data Direction Register TRISE Port E is the control port for the Parallel slave port (Port D) Port E pins are multiplexed with analog inputs PORT E - RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7
STATUS Register
OPTION Register
INTCON Register
PIE1 Register PIC16C72
PIE1 Register PIC16C73/73A/74/74A/76/77
PIR1 Register PIC16C72
PIR1 Register PIC16C73/73A/74/74A/76/77
PIE2 Register PIC16C72
PIR2 Register PIC16C72
PCON Register
Program Counter
PCL & PCLATH PC register 13 bits wide PCL (0 7) readable & writable PCH (8 12) not readable PCH writable using PCLATH register
Addressing Modes
The method of specifying the data to be used in the instruction Types
Direct Addressing Mode Indirect Addressing Mode Relative Addressing Mode
Direct Addressing Mode
Uses RP0 and RP1 of STATUS Register to select RAM memory banks Done through 9 bit address bits 0 to 7 indicates the address of bank, and bits 8,9 indicate bank selection bits
Indirect Addressing Mode
Uses IRP bit of STATUS Register to select RAM memory banks Done through 8 bit address bits 0 to 7 indicates the address of bank, and bit 8 indicate the bank selection bit Used for erasing a part of RAM memory Used while programming in serial communication
Relative Addressing Mode
Used to specify the number of locations to be shifted from the current address of PC Locations to be shifted is specified by an offset New PC address = next PC address + offset Example : GOTO k
CALL k
Instruction Set
Instruction Set
Instruction Set