Unit-3_1

COMPUTER ORGANIZATION AND ARCHITECTURE

Processor Architectures :

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 Outline

• RISC-Features
• CISC Features,
• Comparison of RISC & CISC
• Superscalar Processors.
• Super pipelined Processor.

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 Processor Architectures

• The terms RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set
Computing) refer to two different types of computer architectures.
• RISC and CISC are two different types of computer processor designs, or instruction set
architectures (ISA), that refer to the way a processor communicates with a programmer.
• CISC – 1970 10 years later RISC in high end work station.
• In the past, it was believed that hardware design was easier than compiler design
• Most programs were written3 in assembly language
• Hardware concerns of the past: 1. Limited and slower memory 2. Few registers
• The Solution :- As limited registers so … Instructions have do more work, thereby minimizing
the number of instructions called in a program.
• Allow for variations of each instruction - Usually variations in memory access.
Processor Architectures

Complex Instruction Set Computer.

• Each instruction executes multiple low level operations.

– Ex. A single instruction can load from memory, perform an arithmetic

operation, and store the result in memory.

• Smaller program size.

• The essential goal of a CISC architecture is to attempt to provide a single
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machine instruction for each high level language instruction
– Ex:

– IBM/370 computers

– Intel Pentium processors

 Example of CISC

Let’s understand this with a simple CISC ADD instruction, which requires two
inputs:

[Link] locations of two numbers essential for an addition

[Link] addition and store the result in the first memory location
| ADD 1800, 1801

The ADD instruction picks up numbers from memory locations 1800 and
1801 or registers. Later, the picked-up numbers are added and eventually
stored in location 1800.

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Processor Architectures

CISC Characteristics

• A large number of instructions.

• Some instructions for special tasks used infrequently.
• A large variety of addressing modes (5 to 20).
• Variable length instruction formats.

Disadvantages :
However, it soon became apparent that a complex instruction set has a
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number of disadvantages:

• These include a complex instruction decoding scheme, an increased size of

the control unit, and increased logic delays.
Processor Architectures

In Search of reducing Complexity of the Instruction .

• Compilers became more prevalent.

• The majority of CISC instructions were rarely used.

• Some complex instructions were slower than a group of simple instructions performing
an equivalent task:
– Too many instructions for designers to optimize each one.

• Smaller instructions allowed for constants to be stored in the unused bits of the
instruction
– This would mean less memory calls to registers or memory.

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 Reduced Instruction Set Computer.

• It is a microprocessor that is designed to perform a smaller number of types of

computer instruction so that it can operate at a higher speed.
• RISC, or Reduced Instruction Set Computer utilizes a small, highly-optimized
set of instructions, rather than a more specialized set of instructions often found
in other types of architectures.
• The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s
and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all
designed with a similar philosophy which has become known as RISC
• Ultra Sun SPARC - Classic example of RISC processors
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 RISC Characteristics
• Relatively few instructions 128 or less
• Relatively few addressing modes.
• Memory access is limited to LOAD and STORE instructions.
• All operations done within the registers of the CPU.
• This architectural feature simplifies the instruction set and encourages the optimization of register
manipulation.

• An essential RISC philosophy is to keep the most frequently accessed operands in registers and minimize
register-memory operations.
• Fixed Length, easily decoded instruction format
• Typically 4 bytes in length

• Single cycle instruction execution

• Done by overlapping the fetch, decode and execute phases of two or three instructions known as Pipelining!!

• Large number of registers in the processor unit.

• Use of overlapped Register Windows.

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 Example of RISC

Let’s consider the same ADD instruction and look at how RISC devices
accomplish it.
To begin with, RISC machines do not execute the ADD instruction in one step.
Instead, it is broken down into multiple steps.
For example, you need to load the numbers from memory through a LOAD
instruction, followed by an ADD instruction that adds them, and finally, a
STORE instruction that stores the result in memory.
| Load X, 1600
| Load Y, 1601
| ADD X, Y
| Store 1600, X

In this example, the ‘Load’ instruction loads data at memory location 1600
into register X. Similarly, the second ‘Load’ instruction picks up data from
1601 and loads it into register Y. Later, the values in registers X and Y are
added. Lastly, the result X of addition is stored at memory location 1600 or
any other location. It is worth noting that operations in RISC-type processors
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are performed on ‘registers’ rather than directly on memory.
 RISC Pipeline.

• Different from normal one.

• Based on type of instruction.
• According to instruction type, decide the number of phases in pipeline.
• Number of stages in pipeline are not fixed.
RISC Pipeline.
• Most instructions are register to register
– Two phases of execution
– I: Instruction fetch
– E: Execute
• ALU operation with register input and output
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• For load and store

– Three phase execution
– I: Instruction fetch
– E: Execute
• Calculate memory address
– D: Memory
• Register to memory or memory to register operation
 To Conclude ……

• RISC and CISC are merely different design methodologies. Neither

is inherently superior to the other.

• CISC architectures are equally capable of evolving to the levels of

performance being claimed by RISC.

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To Conclude ……

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To Conclude ……

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 CISC Vs RISC

CISC RISC
• Emphasis on hardware • Emphasis on software

• Includes multi-clock • Single-clock, reduced instruction

complex instructions only

• Memory-to-memory: • Register to register:

"LOAD" and "STORE" "LOAD" and "STORE"
incorporated in instructions are independent instructions

• Small code sizes, • Low cycles per second,

high cycles per second large code sizes

• Transistors used for storing • Spends more transistors

complex instructions on memory registers

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CISC Vs RISC

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 CISC Vs RISC
Neither architecture is universally better; the choice depends on the application. RISC (Reduced Instruction Set
Computer) is generally superior for efficiency, battery life, and speed in mobile/embedded devices (e.g., ARM), while
CISC (Complex Instruction Set Computer) excels in high-performance computing requiring complex instructions,
such as desktop CPUs (e.g., Intel x86).

CISC (Complex Instruction Set Computer)

 Best for: Tasks requiring specialized, complex instructions, heavy computational lifting, or legacy software
compatibility.
 Strengths: Smaller code sizes, fewer instructions per program, lower memory usage.
 Weaknesses: Higher power consumption, complex hardware, slower clock cycles, harder to pipeline.
 Example: Intel x86, AMD processors.

RISC (Reduced Instruction Set Computer)

 Best for: Battery-operated devices, high-speed applications, and IoT, such as smartphones, tablets, and
lightweight laptops.
 Strengths: Faster instruction execution (usually one cycle), lower power consumption, higher performance via
pipelining, more general-purpose registers.
 Weaknesses: Larger code size, higher memory usage, relies heavily on compiler efficiency.
 Example: ARM (Apple M-series, Android), RISC-V.

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 Superscalar Processors
Instruction-Level Parallelism
• Multiple Independent Instruction Pipelines : each with multiple stages, i.e., Common
instructions (arithmetic, load/store , conditional branch) can be initiated and executed
independently determine dependencies between nearby instructions .

• Input of one instruction depends upon the output of a preceding instruction.

• locate nearby independent instructions issue & complete instructions in an order

different than specified in the code stream

• Uses branch prediction methods rather than delayed branches

• RISC or CISC - usually more RISC than CISC

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 Why Superscalar?

• Most operations are on scalar quantities.

• Improve these operations to get an overall improvement.
• This architecture is designed to handle multiple instructions concurrently, typically
by using multiple pipeline units and functional units.

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 What Is Superscalar ?

• Executes multiple independent instructions in parallel, first invented

in 1987.
• Common instructions (arithmetic, load, store etc)can be initiated
simultaneously and executed independently.
• Applicable to both RISC and CISC but usually in RISC.
• It is designed to improve the performance of these operations by
executing them concurrently in multiple pipelines.

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 General Superscalar Organization

• Superscalar systems support parallel execution of several instructions in separate

pipelines of multiple functional units

• The configuration above, supports the parallel execution of two integer operations,
two floating point operations and one memory operation.
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 Super pipelined Architecture

• Pipeline stages can be segmented into n distinct non-overlapping parts each of which can
execute in 1/n of a clock cycle
• Exploits the fact that many pipeline stages perform tasks that require less than half a clock
cycle, i.e., n=2.

• Doubled internal clock speed allows the performance of two tasks in one external clock cycle

• Superscalar allows parallel fetch & execute operations

• Superscalar and superpipelined architectures are both techniques used to improve processor
performance, but they achieve this in different ways.
• Superscalar processors use multiple execution units to execute multiple instructions
concurrently, while superpipelined architectures achieve parallelism by breaking down
instructions into finer stages, allowing multiple stages of the same instruction to be in progress
simultaneousl
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Comparison ……

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 Limitations
• Instruction level parallelism
• Compiler based optimisation
• Hardware techniques
• Limited by
– True data dependency
– Procedural dependency
– Resource conflicts
– Output dependency
– Antidependency
Comparison ……
Superscalar vs. Superpipelined Comparison

•Parallelism: Superscalar runs multiple instructions at once; Superpipelined

runs one instruction at a time, but at a faster rate.
•Goal: Superscalar aims for higher instructions per cycle; Superpipelined aims
for higher frequency.
•Combination: Modern processors often combine both techniques for maximum
performance.

RISC and CISC Integration

•RISC (Reduced Instruction Set Computer): Easier to implement pipelining
due to simple, uniform instructions. They often favor large register sets and
simple, deep pipelines (e.g., ARM, MIPS).
•CISC (Complex Instruction Set Computer): Complex instructions are
typically decoded into smaller, RISC-like operations (micro-ops) to be efficiently
executed in a superscalar pipeline.
•Performance: Both RISC and CISC designs heavily utilize both superscalar and
superpipelined techniques in modern designs to maximize performance

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 References
• Computer Organization And Architecture,8th Edition , William
Stallings

• [Link]
%20Guwahati/comp_org_arc/web/
• [Link]
THANK YOU
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Vishwakarma Institute of Technology, Pune