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Raising a new Generation of Leaders

EIE 411
Computer Organization and
Architecture
MODULE 3 (Part B): Introduction to CISC and RISC
What is a processor ?

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 PREAMBLE
General Classification of The Architectures of Computers:

1. Harvard and Von Neumann Architecture

Examples of Harvard: Texas Instruments TMS320 processors
Examples of Von Neumann: AVR by Atmel, PIC by Microchip

2. Instruction Set Architecture (CISC and RISC)

Examples of CISC: IBM 370, Motorola 68000
Examples of RISC: ARM, MIPS
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 PREAMBLE
3. Application Based Architecture:
- Embedded architecture (e.g. ARM64, Atmel AVR)
- Microcomputer architecture (e.g. Intel IA-32, Motorola 6800, Motorola
68000, ARM64)
- Workstation/Server architecture (Intel IA-64)
- Mini/Mainframe architecture (IBM 360, IBM 370)

Note: A computer can be classified under two or more architectures.

Example: The AVR is a modified Harvard architecture 8-bit RISC single-
chip Microcontroller, developed by Atmel.
*a microcontroller is a microcomputer on a single chip, used to control
some device such as an automobile engine or a toy.
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 PREAMBLE
What is an Instruction Set?
Note that all computers run using very low-level
commands which do some very basic functions, such as
reading data, writing data, jumping to addresses, and
calculating basic arithmetic and logic operations.
So the complete list of commands that can be run by a
CPU is known as that computer’s instruction set. High-
level languages such as C++, Fortran, must be compiled
(translated) into theses low level commands in order for a
program to run.
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PREAMBLE
These low-level commands are run in a
series of steps, which are synchronized with
the computer’s clock.
A computer runs with precise timing
dictating when instructions are fetched,
decoded, executed, and stored.

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PREAMBLE
These low-level commands are run in a s

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PREAMBLE
Some Simple Commands are:
• MOV AX,3 ; Put 3 into register AX
• ADD AX,2 ; Add 2 to the contents of AX
• SUB AX,4 ; Subtract 4 from the contents
of AX

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Introduction to CISC and RISC
An important aspect of computer
architecture is the design of the instruction
set for the processor.
NOTE THAT:
The instruction set chosen for a particular
computer determines the way that machine
language programs are constructed.
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 Introduction to CISC and RISC
A computer with a large number of instructions is
classified as a Complex Instruction Set Computer,
abbreviated CISC.
In the early 1980s, a number of computer designers
recommended that computers use fewer instructions
with simple constructs so they can be executed much
faster within the CPU without having to use memory as
often. This type of computer is classifies as a Reduced
Instruction Set Computer, abbreviated RISC.
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Introduction to CISC and RISC
When designing an instruction set for a
computer, we must consider not only the
machine language constructs, but also the
requirements imposed on the use of high-
level programming languages.
The translation from high-level language to a
low level language is done by the means of a
compiler program.
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 Introduction to CISC and RISC
• A compiler is a computer program that transforms
source code written in a high-level programming
language into another low-level computer language
(i.e. the target language). Basically, it is the translation
of a source code such as C++ into a target language
such as Assembly language.
• An assembler is a program that takes basic computer
instructions and converts them into a pattern of bits that
the computer’s processor can use to perform its basic
operations.
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Introduction to CISC and RISC

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CISC Architecture
Examples of CISC architectures:
• Digital equipment corporation VAX
computer
• IBM 370 computer
• Intel 386, 486, Pentium, Pentium Pro,
Pentium II, Pentium III
• Motorola’s 68000, 68020, 68040, etc.
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 CISC Architecture
In summary, the major characteristics of CISC architecture are:
• A large number of instructions – typically from 100 to 250 instructions.
• Some instructions that perform specialized tasks and are used
infrequently
• A large variety of addressing modes – typically from 5 to 20 different
modes
• Variable-length instruction formats
• Instructions that manipulate operands in memory. Different machine
programs can be executed on CISC machine.
• CISC machines uses micro-program control unit.
• CISC processors have limited number of registers.

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 RISC Architecture
Reduced Instruction Set Computer (RISC) is a type of
microprocessor architecture that utilizes a small, highly-
optimized set of instructions, rather than a more specialized set
of instructions often found in CISC architecture.
Examples of RISC Architecture:
• DEC Alpha
• ARM
• MIPS
• Atmel AVR

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CISC AND RISC Architecture
Most desktop or laptop computers use
CISC architecture (e.g. made by Intel).
Smartphones and tablets use RISC (e.g.
made be ARM).

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 CISC AND RISC Architecture
Let consider the key differences between RISC and
CISC under the following area:
• Instructions
• Physical size
• Speed
• Energy consumption
• Design
• Cost
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 CISC AND RISC Architecture
The key differences between an Intel’s CPU and an ARM’s CPU are:
• Instructions - RISC has fewer instructions than CISC. CISC generally
have hundreds of instructions whereas RISC usually has a lot less. To do
complex tasks, RISC CPUs must combine simple operations from their
reduced instruction set. The instruction cycle in CISC is more complex than
RISC, so RISC can be more efficient at performing simpler tasks.
• Physical size - in order to handle all those instructions CISC CPUs are
larger and require more silicon to make.
• Speed - RISC CPUs run at a lower clock speed than CISC CPUs. They can
perform simpler tasks more quickly than CISC, but more intensive tasks
will be better on a CISC CPU. However, smartphones and tablets are
generally not used to do intensive tasks like playing the most hi-spec
advanced games.
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 CISC AND RISC Architecture
• Energy consumption - because CISC CPUs are larger, they use
more electricity. RISC CPUs are designed to use less power and
they can go into 'sleep mode' when not actively processing a
program.
• Design - smartphones and tablets combine their processing
architecture into a system on a chip (SOC). As RISC CPUs are much
smaller than CISC, more functions (including the memory and
other hardware) can be combined with the CPU in one chip. CISC
CPUs are usually built into a system which has a heat sink and
fan to cool them down. Smartphones or tablets do not have space
for heat sinks or fans.
• Cost - RISC CPUs use less power and are cheaper to make.
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CISC AND RISC Architecture

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 CISC AND RISC Architecture
Android supports 3 different processor
architectures: ARM, Intel and MIPS (originally
an acronym for Microprocessor without Interlocked
Pipeline Stages). The most popular and
ubiquitous of these three is, without a
doubt, ARM. Intel is well known primarily
because of its popularity in the desktop and
server markets, however on mobile it has
had less of an impact.
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 CISC AND RISC Architecture
So what is the difference between an ARM processor
and an Intel processor? Why is ARM the more popular
choice? And does it matter what CPU is in your
smartphone or tablet?
At the highest level, the first difference between an
ARM CPU and an Intel CPU is that the former is RISC
and the latter is a CISC. RISC instructions sets are
smaller, while CISC instruction sets are larger, more
complex.
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 CISC AND RISC Architecture
Multiplying Two Numbers:
The CISC Approach
The primary goal of CISC architecture is to complete a
task in as few lines of assembly as possible. This is
achieved by building processor hardware that is
capable of understanding and executing a series of
operations. For this particular task, a CISC processor
would come prepared with a specific instruction ‘MULT’
MULT a, b
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 CISC AND RISC Architecture
Multiplying Two Numbers:
The RISC Approach
• RISC processors only use simple instructions that can
be executed within one clock cycle. Thus, the "MULT"
command described above could be divided into three
separate commands: "LOAD," which moves data from
the memory bank to a register, "PROD," which finds
the product of two operands located within the
registers, and "STORE," which moves data from a
register to the memory banks.
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 CISC AND RISC Architecture
In order to perform the exact series of steps described in the CISC
approach, a programmer would need to code four lines of assembly:

• LOAD A, a
• LOAD B, b
• PROD A, B
• STORE a, A
At first, this may seem like a much less efficient way of completing
the operation. Because there are more lines of code, more RAM is
needed to store the assembly level instructions. The compiler must
also perform more work to convert a high-level language statement
into code of this form.
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 CISC AND RISC Architecture
However, the RISC strategy also brings some
very important advantages. Because each
instruction requires only one clock cycle to
execute, the entire program will execute in
approximately the same amount of time as the
multi-cycle "MULT" command. These RISC
"reduced instructions" require less transistors of
hardware space than the complex instructions.
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 RISC Architecture
Although RISC system have been defined and designed in a
variety of ways by different groups, the key element shared
by most design are these:
• A large number of general purpose registers, or the use
of compiler technology to optimize register usage.
• A limited and simple instruction set.
• An emphasis on optimizing the instruction pipeline
An analysis of the RSIC architecture begins into focus
many of the important issues in computer organization and
architecture.
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 The comparism of RISC and non-RISC systems is given in the Table

Characteristics of some CISCs, RISCs and Supersclar Processors

Complex Reduced
Instruction Set Instruction Set
Superscaler
(CISC) Computer (RISC) Computer

IBM VAX Intel MIPS Power Ultra MIPS

Characteristics SPARC
370/168 11/780 80486 R4000 PC SPARC R10000

Year Developed 1973 1978 1989 1987 1991 1993 1996 1996

Number of
208 303 235 69 94 225 -- --
Instructions

Instruction Size
2-6 2-57 1-11 4 4 4 4 4
(bytes)

Addressing modes 4 22 11 1 1 2 1 1

Number of general-purpose
16 16 8 40-520 32 32 40-520 32
registers

Control Memory size (kbits) 420 480 246 -- -- -- -- --

Cache size
64 64 8 32 128 16-32 32 64
(kbits)

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Characteristics of Reduced Instruction Set
Architecture :
Although a variety of different approaches to
reduce Instruction set architecture have
been taken, certain characteristics are
common to all of them:
• One instruction per cycle.
• Register to register operations.
• Simple addressing modes.
• Simple instruction formats.
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 1. One machine instruction per machine
cycle :
• A machine cycle is defined to be the time it takes
to fetch two operands from registers, perform an
ALU operation, and store the result in a register.
With simple, one-cycle instructions there is little or
no need of microcode, the machine instructions
can be hardwired. Hardware implementation of
control unit executes faster than the
microprogrammed control, because it is not
necessary to access a microprogram control store
during instruction execution.
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2. Register to register operations
With register to register operation, a simple
LOAD and STORE operation is required to
access the memory, because most of the
operation are register to register. Generally
we do not have memory to memory and
mixed register/memory operation.

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3. Simple Addressing Modes

• Almost all RISC instructions use simple

register addressing. For memory
access only, we may include some
other addressing, such as displacement
and PC-relative. Once the data are
fetched inside the CPU, all instruction
can be performed with simple register
addressing.
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4. Simple Instruction Format
• Generally in most of the RISC machine,
only one or few formats are used.
Instruction length is fixed and aligned on
word boundaries. Field locations, especially
the opcode, are fixed.
With fixed fields, opcode decoding and
register operand accessing can occur
simultaneously. Simplified formats simplify
the control unit.
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 ASSIGNMENT: To agree on submission date
1: What are the distinguishing characteristics of RISC organization?
2: Briefly explain the basic approaches used to minimize register-memory
operations on RISC machines.
3: Give some reasons for shifting the paradigm from CISC to RISC.
4: Explain the concept of register window to handle the procedure calls.
5: If a circular register buffer is used to handle local variables for nested
procedures, describe the approaches for handling global variables.
6: Explain the concept of graph coloring to optimize the register uses.
7: What are the differences of using large register file and cache memory?

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