CMOS Digital Integrated Circuits
Designing Combinational Logic Circuits
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Contents
Combinational vs. Sequential Circuits Static CMOS Logic Dynamic CMOS Logic Issues in Dynamic Design Conclusion
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Combinational vs. Sequential Circuits
In
Combinational Logic Circuit
In
Out
Combinational Logic Circuit
Out
State
Combinational
Output = f(In)
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Sequential
Output = f(In, Previous In)
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Designing Combinational Logic Circuits
There are two methods combinational logic circuits
Static CMOS Logic Dynamic CMOS Logic
to
design
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Static CMOS Logic
At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).
This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
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Static CMOS Logic
VDD
In1 In2 PMOS only F(In1,In2,InN) PDN PUN
InN
In1 In2 InN
NMOS only
PUN and PDN are dual logic networks
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NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A X A B Y Y = X if A and B
Y = X if A OR B
NMOS Transistors pass a strong 0 but a weak 1
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PMOS Transistors in Series/Parallel Connection
PMOS switch closes when switch control input is low
A X A B Y = X if A AND B = A + B
Y = X if A OR B = AB
PMOS Transistors pass a strong 1 but a weak 0
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Example Gate: NAND
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Example Gate: NOR
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Complex CMOS Gate
B A C D OUT = D + A (B + C) A
D
B C
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Properties of Complementary CMOS Gates
High noise margins: VOH and VOL are at VDD and GND, respectively. No static power consumption : There never exists a direct path between VDD and VSS (GND) in steady-state mode.
Comparable rise and fall times: (under appropriate sizing conditions)
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Dynamic CMOS Logic
In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.
fan-in of n requires 2n (n N-type + n P-type) devices
Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.
requires on n + 2 (n+1 N-type + 1 P-type) transistors
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Dynamic CMOS Logic Gate
In dynamic CMOS logic a single clock can be used to accomplish both the pre-charge and evaluation operations
When is low, PMOS pre-charge transistor Mp charges Vout to Vdd, since it remains in its linear region during final pre-charge
During this time the logic inputs A1 B2 are active; however, since Me is off, no charge will be lost from Vout
When goes high again, Mp is turned off and the NMOS evaluate transistor Me is turned on, allowing for Vout to be selectively discharged to GND depending on the logic inputs
If A1 B2 inputs are such that a conducting path exists between Vout and Me, then Vout will discharge to 0 Otherwise, Vout remains at Vdd
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Dynamic CMOS Logic Circuits
Dynamic CMOS Logic circuits require a clock to precharge the output node and then to pull down the logic tree (assuming the logic inputs provide a path for current to flow)
Precharge Phase: clock is down turning on the P precharge transistor; N pull-down transistor is off. Output capacitance CN charges to Vdd. Evaluation Phase: clock goes high turning on the N pull down transistor and turning off the P precharge transistor. If logic inputs are such that neg Z is true, then output capacitance CN discharges to ground. No dc current flows during either the precharge or the evaluate phase. Power is dynamic and is given by P = CN Vdd2 f where CN represents an equivalent total capacitance on the output, f = clock frequency, =logic repetition rate
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Cascading Problem in Dynamic CMOS Logic
If several stages of the previous CMOS dynamic logic circuit are cascaded together using the same clock , a problem in evaluation involving a built-in race condition will exist Consider the two stage dynamic logic circuit below:
During pre-charge, both Vout1 and Vout2 are pre-charged to Vdd When goes high to begin evaluate, all inputs at stage 1 require some finite time to resolve, but during this time charge may erroneously be discharged from Vout2 e.g. assume that eventually the 1st stage NMOS logic tree conducts and fully discharges Vout1, but since all the inputs to the N-tree all not immediately resolved, it takes some time for the Ntree to finally discharge Vout1 to GND. If, during this time delay, the 2nd stage has the input condition shown with bottom NMOS transistor gate at a logic 1, then Vout2 will start to fall and discharge its load capacitance until Vout1 finally evaluates and turns off the top series NMOS transistor in stage 2 The result is an error in the output of the 2nd stage Vout2
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Cascaded Dynamic CMOS Logic Gates: Evaluate Problem
With simple cascading of dynamic CMOS logic stages, a problem arises in the evaluate cycle:
The pre-charged high voltage on Node N2 in stage 2 may be inadvertently (partially) discharged by logic inputs to stage 2 which have not yet reached final correct (low) values from the stage 1 evaluation operation. Can not simply cascade dynamic CMOS logic gates without preventing unwanted bleeding of charge from pre-charged nodes
Possible Solutions:
two phase clocks use of inverters to create Domino Logic NP Domino Logic Zipper/NORA logic
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CMOS Domino Logic
The problem with faulty discharge of precharged nodes in CMOS dynamic logic circuits can be solved by placing an inverter in series with the output of each gate
All inputs to N logic blocks (which are derived from inverted outputs of previous stages) therefore will be at zero volts during precharge and will remain at zero until the evaluation stage has logic inputs to discharge the precharged node PZ. This circuit approach avoids the race problem of vanilla cascaded dynamic CMOS However, all circuits only provide noninverted outputs Charge sharing between dynamic node and intermediate node of NMOS logic block during the evaluation phase.
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Issues in Dynamic Design 2: Charge Sharing
Clk A B=0 Clk
Me Mp Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness
Out CL CA CB
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Solution to Charge Sharing
Keeper Clk A
Mp Mkp
CL
Out
B
Clk
Me
solution to charge sharing is to add weak PMOS, which forces a high output level unless there is strong pull-down path between output and ground.
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Properties of Dynamic Gates
Logic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static complementary CMOS)
Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds
reduced load capacitance due to lower input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout) no Isc, so all the current provided by PDN goes into discharging CL
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Static Vs Dynamic Logic
Parameters
Number of components Behavior of logic Reliability Results Results SAP
Static Logic
2N stable high No such Problems Less P
Dynamic Logic
N+2 unstable less Charge Sharing, Erroneous results A reduced S increased
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Assignment
In Dynamic CMOS logic only NMOS network has been used and has less delay as compare to static CMOS logic. How? Implement function Not ((A.B)+C) in static and dynamic logic style.
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Thank You