STA (Static Timing Analysis)

Table of Contents
Purpose of STA..........................................................................................................................................2
STA in digital design flow..........................................................................................................................2
Types of Timing Analysis – Setup & Hold time........................................................................................3
Clock Skew................................................................................................................................................5
Slack...........................................................................................................................................................5
Recovery Time and Removal time.............................................................................................................7
Clock jitter and Latency.............................................................................................................................8
Clock types – Gated,Virtual & Derived clock...........................................................................................9
Timing Paths – False,Multicycle & Critical path.....................................................................................10
Methods to improve timing – Pipelining, Retiming & Time borrowing..................................................11
Examples..................................................................................................................................................14
Interview questions..................................................................................................................................18

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Static timing analysis (STA) is a method of validating the timing performance of a design by checking
all possible paths for timing violations under worst case conditions. STA breaks a design down into
timing paths, calculates the signal propagation delay along each path, and checks for violations of
timing constraints inside the design and at the input/output interface.

Purpose of STA

• Verifies timing without simulation: STA checks every possible timing path without needing
test vectors.
• Faster than simulation: Static timing analysis is much faster because it is not necessary to
simulate the logical operation of the circuit.
• More thorough: STA is also more thorough because it checks all timing paths, not just the
logical conditions that are sensitized by a set of test vectors.
• Ensures functionality: It verifies that the circuit will operate correctly at the intended clock
frequency by ensuring setup and hold times are met for all flip-flops.

STA in digital design flow

• Synthesis: The high-level RTL code is converted into a gate-level netlist, which is the input for
STA.
• Constraint file creation: A constraint file (e.g., SDC) is created to specify the design's clock
frequencies and other timing requirements.
The constraints in SDC file can be broadly categorized as :
• create_clock, generated_clock, virtual clock.
• Input delay and output delay
• Max delay and Min delay.
• Static Timing Analysis: The STA tool analyzes all timing paths based on the netlist and
constraint file to identify violations.
• Reporting and Fixing: The tool reports timing violations such as setup and hold time issues
and then those are fixed.
• Physical Design: After passing timing checks, the design moves to physical design for layout
and routing. STA is used again at various stages of physical design (post-synthesis, route) to
ensure the final layout meets timing.

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Types of Timing Analysis – Setup & Hold time

Setup Time : Setup time is defined as the minimum amount of time before the clock's active edge that
the data must be stable for it to be latched correctly. In other words, each flip-flop needs some time for
the data to remain stable before the clock edge arrives, such that it can reliably capture the data. This
duration is known as setup time.

Hold time : Hold time is defined as the minimum amount of time after the clock's active edge during
which data must be stable. Similar to setup time, each sequential element needs some time for data to
remain stable after clock edge arrives to reliably capture data. This duration is known as hold time.

Setup and Hold Violation :

If setup time is tsu for a flip-flop and data is not stable before t su time from the active edge of the
clock,then there is setup violation at that flop. So if the data is changing in the non shaded area (in the
above figure) before active clock edge,then it’s a setup violation.
And if hold time is thd for a flip-flop and if data is not stable after t hd time from active edge of the
clock,there is a hole violation at that flop. So if data is changing in the non shaded area (in the above
figure) after active clock edge,then it’s a hold violation.

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Setup and Hold time Equation:
Data path:
FF1 (launch) → combinational delay → FF2 (capture)
Setup Time Concept (Tsu)
• Data launched at FF1 on a rising edge must
arrive at FF2 before the next rising edge – Tsu
before the clock edge.
• If data arrives too late, it causes a setup
violation.
Example:
Clock period = 10 ns
• If launched at 0 ns, it must arrive at FF2 before
10 ns.
• If Tsu = 1 ns, it must arrive by 9 ns.

Hold Time Concept (Thd)

• After a clock edge, data at FF2 input must remain stable for Thd after the same edge.
• If the next data from FF1 arrives too early, it causes a hold violation.
Example:
If FF2 hold time Thd = 0.5 ns:
• Data launched at 10 ns should not reach FF2 before 10.5 ns.
• If it reaches in 0.5 ns from FF1 → FF2, a hold violation occurs.
In simple words,
• Setup is checked at next clock edge.
• Hold is checked at same clock edge.
As shown, data launched from launching flop is allowed to arrive at the input of the second flop only
after a delay greater than its hold requirement so that it is properly captured. Similarly, it must not have
a delay greater than (clock period – setup requirement ) of second flop. In other words, mathematically
speaking, setup check equation is given as below (assuming zero skew between launch and capture
clocks):
Tck->q + Tprop + Tsetup < Tperiod

Similarly, hold check equation is given as: Tck->q+ Tprop >Thold

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Clock Skew

When a clock comes from the same source but

reaches two flip-flops at different times, the time
difference is called clock skew.

Clock Skew = Clock arrival time at Capture Flop

− Clock arrival time at Launch Flop

How Skew Affects Timing Checks -

• Setup time equation - Tck->q + Tprop + Tsetup < Tperiod + Tskew

• Hold time equation - Tck->q+ Tprop > Thold + Tskew

Clock skew can lead to timing violations because the data at destination flop might arrive too
early (setup check gets relaxed but hold check becomes harder to meet) or it might come too late
(for negative skew,it introduces violations to setup check).

Slack

• It is difference between the desired arrival times and the actual arrival time for a signal.
• Slack time determines [for a timing path], if the design is working at the desired frequency.
• Positive Slack indicates that the design is meeting the timing and still it can be improved.
• Zero slack means that the design is critically working at the desired frequency.
• Negative slack means , design has not achieved the specified timings at the specified frequency.
• Slack has to be positive always and negative slack indicates a violation in timing.

Required time : The time within which data is required to arrive at some internal node of the design.
Arrival time : The time in which data arrives at the internal node.

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Setup Slack = Required time - Arrival time
• Tackling setup time violation: As given above, the equation for setup timing check is given as:
Tck->q+ Tprop+ Tsetup- Tskew< Tperiod

The parameter that represents if there is a setup time violation is setup slack. The setup slack
can be defined as the difference between the L.H.S and R.H.S. In other words, it is the margin
that is available such that the timing path meets setup check. The setup slack equation can be
given as:
Setup slack =Tperiod- (Tck->q+ Tprop+ Tsetup- Tskew)

If setup slack is positive, it means there is still some margin available in the timing path. On
the other hand, a negative slack means that the paths violates setup timing check by the amount
of setup slack.

Mitigating setup violation: Thus, we can meet the setup requirement, if violating, by
1. Decreasing clk->q delay of launching flop
2. Decreasing the propagation delay of the combinational cloud
3. Reducing the setup time requirement of capturing flop
4. Increasing the skew between capture and launch clocks
5. Increasing the clock period

Hold slack = Arrival time - Required time

• Tackling hold time violation: Similarly, the equation for hold timing check is as below:
Tck->q+ Tprop> Thold + Tskew

The parameter that represents if there is a hold timing violation is hold slack. The hold slack is
defined as the amount by which L.H.S is greater than R.H.S. In other words, it is the margin by

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 which timing path meets the hold timing check. The equation for hold slack is given as:

Hold slack =Tck->q+ Tprop - Thold- Tskew

If hold slack is positive, it means there is still some margin available before it will start violating
for hold. A negative hold slack means the path is violating hold timing check by the amount
represented by hold slack.
Mitigating hold violation: We can meet the hold requirement by:
1. Increasing the clk->q delay of launching flop
2. Decreasing the hold requirement of capturing flop
3. Decreasing clock skew between capturing clock and launching flip-flops.

Recovery Time and Removal time

Recovery and Removal time are timing checks used in digital design to ensure that asynchronous
control signals, primarily resets. These checks prevent metastability, glitches, and functional failures.
These are very important because -
 Asynchronous signals do not follow the clock.
 Deasserting an asynchronous reset too close to a clock edge can cause a flip-flop to enter an
undefined state.
 Recovery and Removal checks ensure safe reset release timing.

Recovery time - Recovery Time is the minimum time that an asynchronous reset signal must stay
stable before the clock edge.
 Ensures the flip-flop has enough time to “recover” from reset before sampling data.
 Conceptually equivalent to setup time, but applied to asynchronous resets.
 Violation effect: The flop may output incorrect values due to insufficient recovery time.
Removal Time - Removal Time is the minimum time that an asynchronous reset signal must stay
stable after the clock edge.
 Ensures that the clock edge is not affected by an early reset release.
 Conceptually equivalent to hold time, but applied to asynchronous resets.
 Violation effect: The flop may enter metastability if the reset is removed immediately after a
clock edge

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Both of these may lead to the flip-flop may fail to resolve to a stable logic ‘0’ or ‘1’ in [Link] results
in metastability, leading to unpredictable output and possible downstream failures.

How to avoid recovery and removal violations -

 Use reset synchronizers to safely release asynchronous resets.
 Ensure reset release meets both recovery and removal timing requirements.
 Define proper recovery/removal constraints in STA.

Clock Jitter and Latency

Clock jitter - Clock jitter is the short-term variation in the clock period from its ideal value - the clock
edge arrives earlier or later than expected. Clock jitter is typically caused by clock generator circuitry,
noise, power supply variations, interference from nearby circuitry.

Types of Jitter:
 Cycle-to-cycle jitter: Variation between adjacent clock cycles
 Period jitter: Variation in a single clock period
 Long-term jitter: Accumulated variation over many cycles

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Effects - Depending on whether the jitter causes to clock to be slower or faster, there can be setup hold
or setup violations in an otherwise timing clean system. This will in turn lead to performance or
functional issues for the chip.

Clock latency - Clock latency is the delay from the clock source to a register's clock pin. It's the time
taken for the clock signal to propagate through the clock distribution network.
Source Latency (Insertion Delay): Delay from the clock origin (oscillator/PLL) to the clock entry point
of the design.
Network Latency: From clock entry point to register clock pins
Total clock latency is given as the sum of source latency and network latency. In other words, total
clock latency at a point is given as follows:

Clock latency = Source latency + Network latency

Clock types – Gated,Virtual & Derived clock

• Gated clock - A gated clock is a clock signal that passes through logic gates (typically
AND/OR gates) to enable or disable the clock conditionally, used for power saving. Gated
clocks provide significant power savings by disabling unused clock domains. They reduce
dynamic power consumption effectively. The technique is simple to implement in most designs.
Logic gates can introduce glitches on the clock signal. Additional delay and skew get added by
the gating logic. Setup and hold violations may occur if enable signal timing is poor.
• Virtual clock - A virtual clock is a clock that exists only for timing constraint purposes in STA.
It has no physical connection to any registers in the design. Virtual clocks are used for
constraining input/output ports that are clocked by external clocks.
• Derived Clock - A derived or generated clock is created from another clock through frequency
division, phase shifting within the design.

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Timing Paths – False,Multicycle & Critical path

False Path - False path is a very common term used in STA. It refers to a timing path which is not
required to be optimized for timing as it will never be required to get captured in a limited time when
excited in normal working situation of the chip.
Even if the signal takes a long time to propagate, the circuit will still work correctly. Therefore, STA
tools are instructed to ignore such paths and not optimize them for timing.
Example of false path –
 Synchronized Signals –

Let us say we have a two flop synchronizer placed between a sending and receiving flop. In this
scenario, it is not required to meet timing from launching flop to first stage of synchronizer. Figure
above shows a two-flop synchronizer. We can consider the signal coming to flop1 as false, since,
even if the signal causes flop1 to be metastable, it will get resolved before next clock edge
arrives .So ,the path traversed by the signal coming from launch flop to the first stage synchronizer
should be considered as false path.
Multicycle path -By definition, a multi-cycle path is one in which data launched from one flop is
allowed (through architecture definition) to take more than one clock cycle to reach to the destination
flop.
 They help when logic is too slow to meet the frequency OR when data comes from a slower
clock.
 They relax timing, reduce power, and avoid slowing the entire design.
Critical Path - A critical path in Static Timing Analysis (STA) is the longest and slowest path through
which data travels between two sequential elements, such as flip-flops.
 It represents the path with the maximum delay, and therefore it limits the highest clock
frequency at which the design can operate reliably.
 If the critical path fails timing, the entire chip may malfunction at the target frequency.
STA tools focus on this path first because ensuring its timing closure is essential for achieving the
required performance of the design.

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Methods to improve timing – Pipelining, Retiming & Time
borrowing

 Pipelining - Pipelining is the process of inserting additional flip-flops into long combinational
paths to break them into smaller segments. By reducing the logic delay between registers, each
stage can meet setup time more easily, allowing the design to run at a higher clock frequency.
Although it increases latency (more cycles to get the final output), but it helps meet tight timing
requirements.
Example: A path with 10ns combinational delay can be split into two 5ns stages, potentially
doubling the clock frequency from 100MHz to 200MHz.

 Retiming - Retiming relocates existing registers along data paths without changing the circuit's
functionality or the total number of registers. The goal is to balance delays between pipeline
stages, reduce the longest (critical) path, and improve timing without adding more latency.
How it works:
• Moves flip-flops forward or backward through combinational logic
• Redistributes delays more evenly across clock cycles
• Optimizes the position of registers to balance path delays

Example- Here is an example of forward retiming (moving a register from the input to the
output of a logic block). Suppose an operation performs an addition taking 5 ns and a
multiplication taking 8 ns, all in one combinational path. This creates a 13 ns critical path,
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 limiting the clock frequency to about 76.9 MHz. By applying forward retiming, we move a
register from the input to the output of the adder, splitting the path. Now the multiplier sees
registered input and only needs 8 ns, so the new clock period becomes 8 ns, increasing the
maximum frequency to 125 MHz. This improves performance without changing the
functionality.
 Time borrowing - Time borrowing applies to designs using level-sensitive latches instead of
edge-triggered flip-flops.
A flip-flop captures data only at one event (posedge or negedge). So if the logic takes more
time than one clock period allows, a flip-flop cannot extend or “borrow” time. This is where
latches help. Latches are level-sensitive, meaning they remain transparent for part of the
clock cycle. This allows the data path to use extra time from the next half-cycle. This is called
time borrowing.
Example -
Consider a 10-unit clock with 50% duty [Link] only flip-flops, data launched at time 0
must reach the next flip-flop before time 10.
If it arrives after 10, it fails setup.

For ease of understanding, let us assume that the setup and hold for each of the flops is “0”.
Also, assume that the clock skew and clock-delays are “0”.
Now replace the middle flip-flop with a latch.
A latch is transparent for half the cycle (from 10 to 15 in this example).
This means:
 If data arrives before 10, it behaves exactly like a flip-flop.
 If data arrives after 10, the latch can still accept it as long as it arrives before 15.

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 So if data arrives at 12, it is 2 units late, but the latch still allows it to pass.
This extra 2 units is the time borrowed. However, since we borrowed 2 units in the first stage,
the next stage (latch → F3) now gets only: 10 – 2 = 8 ns.
 The path into the latch gets extra time.
 The path after the latch loses the same amount of time.
In short, A latch allows a slow path to “borrow” time from the next stage while still keeping
the total cycle time the same.

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Examples

Example 1 : Check for setup and hold violations

Setup time calculation :

Arrival Time
Tarrival =0 ns+0.5 ns=0.5 ns
Data is captured at the next clock → 10 ns.
Required Time
Trequired =10 ns−2 ns=8 ns
Setup Slack
Slack=Trequired −Tarrival =8−0.5=7.5 ns
No Setup Violation (slack > 0)
Hold Time Calculation :
Required Time
Data must remain stable till:
10 ns+1 ns=11 ns
Arrival Time of New Data
Tarrival_new =10 ns+0.5 ns=10.5 ns
Hold Slack
Slack=Tarrival_new −11=10.5−11= −0.5 ns
So there is hold violation. To avoid it, Tarrival_new > 11 ns.

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Required minimum delay = 11 – 10 = 1 ns. So the combinational delay must be ≥ 1 ns.

Example 2 : Consider the below logic circuit with delays dly1, dly2, and dly3 at different places shown
and determine the constraints to avoid setup time and hold violation.

Also for the given timing specifications calculate the maximum clock frequency of operation or
minimum required clock time period.
dly2 = 0.5ns and dly3 = 3ns. and
Tclock_Q1 =Tclock_Q2 = 2.5ns.
Tsetup_time1 =Tsetup_time2 = 2ns
Thold_time1 =Thold_time2 = 1ns

Assume timing parameters for FF1 and FF2 asTclock_Q1,Tsetup_time1, Thold_time1

andTclock_Q2,Tsetup_time2, Thold_time2 respectively.
Let us assume positive clock skew and calculate delta = dly2 – dly3.
The setup time constrain when a pair of flops circuits is given will be,
Tminimum >=Tsetup_time2 +Tclock_Q1 + dly1 – delta
**Note the setup time of the second flip flop will be considered here.
And the hold time constraint for the same will be,
Thold_time2 <=Tclock_Q1 + dly1 – delta
We must calculate delta and dly1 values first
delta = delta2 – delta3
delta = 3ns – 0ns
delta = 2.5ns
and the dly1 value by considering there is no hold violation. therefore

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Thold_time2 <= Tclock_Q1 + dly1 – delta
dly1 >= Thold_time2 – Tclock_Q1 + delta
dly1 >= 1ns – 2.5ns + 2.5ns
dly1 >= 1ns
Now by using setup time constraint we can compute minimum required clock period,
Tminimum >= Tsetup_time2 + Tclock_Q1 + dly1 – delta
Tminimum >= 2ns + 2.5ns + 1ns – 2.5ns
Tminimum >= 3ns
therefore
fmaximum = 1/3ns = 333.33MHz is the maximum frequency of operation.

Example 3 : In the following circuit, find out whether there is any setup or hold violation .

For a hold check, compare:

• Minimum delay of data path
• Maximum delay of clock path
Data Path (min delay)
CLK → FF1 → inverter → FF2
Td=1+9+6+1+1=18 ns
Clock Path (max delay)
CLK → buffer → FF2 clock
Tclk =3+9+3+2=17 ns
Hold Slack

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Slack=Td −Tclk =18−17=1 ns (positive)
Hold slack is positive, so there is no violation.
For setup, compare:
• Max data-path delay
• Min clock-path delay + clock period
Data Path (max delay)
CLK → FF1 → inverter → FF2
Td =2+11+9+2+2=26 ns

Clock Path (min delay + clock period)

Clock period = 15 ns
Path: CLK → buffer → FF2/CLK
Tclk =15+2+5+2−4=20 ns
Setup Slack
Slack=Tclk −Td =20−26= −6 ns
As setup slack is negative,so there is setup violation.

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Interview questions

[Link] is Setup time and Hold time?

2. Why is setup checked at the next clock edge but hold is checked at the same edge?

3. What is Slack? What does positive/negative slack indicate?

4. What are the equations for Setup Slack and Hold Slack.

5. How does positive and negative clock skew affect setup and hold?

6. What are Clock Latency and Clock Jitter? How do they impact timing?

7. What is a Critical Path? How do you identify it?

8. What are false paths? Give at least two examples.

9. What is a Multi-Cycle Path (MCP)?

10. What is the difference between a Virtual Clock and a Generated Clock?

11. How do you fix a setup violation?

12. How do you fix a hold violation?

13. What is Recovery and Removal time in asynchronous reset?

14. What is Time Borrowing in latch-based designs?

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