Combinational Logic Circuits:

Table of Contents
Arithmetic Circuits.................................................................................................................................................. 2

Non-arithmetic:........................................................................................................................................................ 9

Hazards & Glitches:.............................................................................................................................................. 14

Tri-State Buffers:................................................................................................................................................... 14

Delays in Combinational Circuits:................................................................................................................... 15

Using MUX to Implement Gates, Adders, Flip-Flops, D-Latch..............................................................16

Design 5x1 MUX using 2x1 MUX:.................................................................................................................... 20

Using DEMUX to realize logic gates:.............................................................................................................. 22

INTERVIEW QUESTIONS:................................................................................................................................... 23

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Arithmetic Circuits
 Arithmetic circuits are combinational logic circuits that perform
mathematical operations such as addition, subtraction,
multiplication, and division on binary numbers.

 They form the core part of digital systems like processors, calculators,
and digital signal processors (DSPs).

ADDERS:
Half_Adder:
 The Combinational circuit that performs the addition of two
bits.
 A half adder circuit has two binary inputs and two binary
output’s(sum,carry).
 It is an arithmetic circuit used to perform the arithmetic
operation of addition of two single bit words.
Truth_Table:
A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Circuit_Diagram:

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  SUM = A ⊕ B (XOR Gate)
 CARRY = A · B (AND Gate)
Code Example:

module half_adder (
input A,
input B,
output Sum,
output Carry
);
assign Sum = A ^ B; // XOR gate
assign Carry = A & B; // AND gate
endmodule
Full_Adder:
 It is used to add 3 bits and outputs sum and carry
Truth_Table:
A B C SUM CARRY

0 0 0 0 0

0 0 1 1 0

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 A B C SUM CARRY

0 0 0 0 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

A full adder's K-maps are used to determine simplified Boolean expressions

for both the sum and carry outputs based on its truth table. For a full adder
with inputs A, B, and Cin, the expressions are derived as follows:
K-Map for Full Adder
Sum Output
The sum can be organized in a Karnaugh map using A and B on one axis and Cin on the
other:

AB \ Cin 0 1

00 0 1

01 1 0

11 0 1

10 1 0

From this K-map, the simplified Boolean expression is:

Sum=A⊕B⊕Cin
Carry Output

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For the carry-out, the K-map looks like:

AB \ Cin 0 1

00 0 0

01 0 1

11 1 1

10 0 1

From this K-map, the simplified Boolean expression is:

Carry=(A AND B) OR [Cin AND (A OR B)]

Code Example:
module full_adder (
input A,
input B,
input Cin,
output Sum,
output Cout
);
assign Sum = A ^ B ^ Cin; // XOR for sum
assign Cout = (A & B) | (B & Cin) | (A & Cin); // OR of ANDs
endmodule
SUBTRACTOR:
Half_Subtractor:
It Performs subtraction of two binary digits.
It has two inputs and two outputs.
 Inputs: A (minuend), B (subtrahend)

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  Outputs:
Difference (D) = A ⊕ B
Borrow (B_out) = A' · B

Truth_Table:
A B DIFFERENCE BORROW

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

Code Example:
module half_subtractor (
input A,
input B,
output Difference,
output Borrow
);
assign Difference = A ^ B; // XOR operation
assign Borrow = (~A) & B; // NOT and AND
endmodule

Full_Subtractor:
 performs subtraction of three binary bits:
 A → minuend

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  B → subtrahend
 Bin → borrow input (from the previous stage)
It gives two outputs:
 Difference (D)
 Borrow out (Bout)

Truth_Table:
A B C DIFFERENCE BORROW

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

From the truth table:

Difference=A⊕B⊕Bin
Borrow out=A(B+Bin)+(B⋅Bin)
Code Example:
// Half Subtractor module
module half_subtractor (

input A,

input B,

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 output Diff,

output Borrow

);

assign Diff = A ^ B;

assign Borrow = (~A) & B;

endmodule

// Full Subtractor using 2 Half Subtractors

module full_subtractor (

input A,

input B,

input Bin,

output Difference,

output Bout

);

wire d1, b1, b2;

half_subtractor HS1 (.A(A), .B(B), .Diff(d1), .Borrow(b1));

half_subtractor HS2 (.A(d1), .B(Bin), .Diff(Difference), .Borrow(b2));

assign Bout = b1 | b2;

endmodule

MULTIPLIERS:

 Performs binary multiplication of two numbers.

Example

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Multiply: (A = 101, B = 011)
→ Decimal: 5 × 3 = 15 (1111 in binary)
 1-bit × 1-bit → Basic building block → AND gate
 2-bit × 2-bit → Uses AND + Adders → 2-bit multiplier
 4-bit / N-bit → Built hierarchically → Array or Booth multiplier
 Sequential Multiplier → Uses registers + adder in clock cycles → Saves hardware
 Parallel Multiplier → All partial products generated simultaneously → Faster but
larger area

Non-arithmetic:
Encoders:
 That converts 2ⁿ input lines into n output lines.

4bit to 2 bit encoder

Truth Table:
D C B A Y X

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

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Code Example:
module encoder_4to2 (input [3:0] D, output [1:0] Y);
assign Y[1] = D[2] | D[3];
assign Y[0] = D[1] | D[3];
endmodule

Decoders:
 It converts n input lines into 2ⁿ unique output lines.

2bit to 4bit encoder

Truth Table:
A B X3 X2 X1 X0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

Code Example:
module decoder_2to4 (input [1:0] A, output [3:0] Y);
assign Y[0] = ~A[1] & ~A[0];

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 assign Y[1] = ~A[1] & A[0];
assign Y[2] = A[1] & ~A[0];
assign Y[3] = A[1] & A[0];
endmodule

MULTIPLEXER:
 A Multiplexer is a data selector — it selects one input from multiple inputs
and routes it to a single output line, based on select (control) inputs.

 A 4-to-1 multiplexer (MUX) is . It has four data inputs (I3,I2,I1,I0 ), two

selection lines (S1.S0), and one output (Y). The two selection lines determine which
input is connected to the output, with different binary combinations corresponding
to each input.

 The two selection lines (S1 and S0) act as a binary address to choose one of the four
data inputs.

 Since there are two selection lines, there are 22 = 4 possible combinations for the
selection inputs.
 These combinations correspond to each of the four data inputs:
 When S1 =0 andS0 =0 , input I0 is selected to be the output.
 When S1 =0 andS0 =1, input I1 is selected to be the output.
 When S1 =1 andS0 =0, input I2 is selected to be the output.
 When S1 =1 andS0 =1, input I3 is selected to be the output.

Truth_Table:

S1 S0 OUTPUT

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 0 0 I0

0 1 I1

1 0 I2

1 1 I3

Code Example:
module mux_4x1_b(
input I0,I1,I2,I3,S0,S1,
output Y);
assign Y = S1?(S0?I3:I2):(S0?I1:I0);
endmodule

Demultiplexer:
 A demultiplexer (DEMUX) is a combinational circuit that works exactly opposite to a
multiplexer.
 A DEMUX has a single input line that connects to any one of the output lines based
on its control input signal (or selection lines)
 For ‘n’ selection lines, there are N = 2^n output lines.
1:4Demultiplexer
1:4 DEMUX has one select line and 4 output lines.

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Truth_table:
S0 S1 Y0 Y1 Y2 Y3

0 0 I0 0 0 0

0 1 0 I1 0 0

1 0 0 0 I2 0

1 1 0 0 0 I3

1:4 Demux Verilog Code:

module demux_1_4(

input [1:0] sel,

input i,

output reg y0,y1,y2,y3);

always @(*) begin

case(sel)

2'h0: {y0,y1,y2,y3} = {i,3'b0};

2'h1: {y0,y1,y2,y3} = {1'b0,i,2'b0};

2'h2: {y0,y1,y2,y3} = {2'b0,i,1'b0};

2'h3: {y0,y1,y2,y3} = {3'b0,i};

default: $display("Invalid sel input");

endcase

end

endmodule

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Hazards & Glitches:
 A hazard is a condition in a digital circuit where a temporary incorrect output occurs
even though inputs have changed logically in a way that the output should remain
stable or change only once.
 Hazards typically arise in combinational logic circuits due to uneven gate delays.
There are three main types of hazards:
 Static Hazard: The output temporarily changes from its steady state value and then
returns to it. It is subdivided into:
 Static-0 hazard: output (ideally 0) momentarily glitches to 1 and back to 0.
 Static-1 hazard: output (ideally 1) momentarily glitches to 0 and back to 1.
 Dynamic Hazard: The output changes multiple times (oscillations) when it should
only change once. This typically happens in more complex circuits with multiple
paths and delays.
 Function Hazard: Occurs due to simultaneous changes in multiple inputs, causing
unpredictable glitches.

Glitches:
 A glitch is a momentary undesired spike or pulse in the output signal, often caused
by hazards. Glitches can lead to erroneous behavior, especially in asynchronous
circuits. They come from the unbalanced propagation delays in logic paths
converging at a gate.
 Glitches are the visible result of hazards.

Causes and Effects

 Different signal paths from inputs to outputs have varying propagation delays.
 When inputs change, these delays cause intermediate outputs to momentarily glitch.
 Glitches can cause spurious switching, errors in asynchronous inputs, and increased
power consumption.

Tri-State Buffers:
 Tri-state buffers allow a circuit line to be in one of three states: logic 0, logic 1, or
high impedance (Z).

 It is used in bus systems where multiple devices share a common data line.

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TruthTable:

ENABLE INPUT OUTPUT

0 X Z

1 0 0

1 1 1

CODE Example:
module tri_state_buffer(
input wire data_in, // Data input
input wire enable, // Enable control signal
output wire data_out // Tri-state output
);

// Assign output: if enable is high, output data_in, else high impedance (Z)
assign data_out = enable ? data_in : 1'bz;

endmodule

Delays in Combinational Circuits:

 Delays in combinational circuits represent the time taken for an input change to
reflect as a stable output change. Two main types of delay are considered:
Propagation Delay (t_PD)
 The longest time it takes for a change in input to produce a valid change at the
output.
 Determines the circuit’s maximum operating speed.
 Calculated by summing the delays of gates and interconnections along the longest
path from input to output.
Contamination Delay (t_CD)
 The shortest time from input change to the initial output change.

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  Indicates when outputs can start to change.
 Calculated by summing the shortest delays of individual gates along the fastest
path.
Factors Affecting Delay
 Gate delays depend on gate type, technology (CMOS, TTL), input transition
times, and load capacitance.
 Interconnection or routing delays significantly impact total delay, especially in
large circuits or FPGAs.
 Physical parameters like temperature, supply voltage, and manufacturing
variations also influence delay.

Using MUX to Implement Gates, Adders,

Flip-Flops, D-Latch

Multiplexers (MUX) can be used as universal logic circuits to implement gates, adders,
flip-flops, and D-latches by configuring input lines and selection lines accordingly.
Gates Using MUX
 A 2:1 or 4:1 MUX can implement basic gates by setting data inputs to 0 or 1
based on the gate's truth table and using inputs as select lines.
2-input AND gate implementation using 2:1 mux: Figure 1 below shows the truth table
of a 2-input AND gate. If we observe carefully, OUT equals '0' when A is '0'. And OUT
follows B when A is '1'. So, if we connect A to the select pin of a 2:1 mux, AND gate will
be implemented if we connect D0 to '0' and D1 to 'B'.

Truth table of AND gate

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 implementation of 2-input AND gate using a 2:1 multiplexer.
 OR, NOR, XOR, and XNOR gates can also be implemented using multiple
MUXes or combinations of MUXes and inverters.
Adders Using MUX
 A 1-bit full adder can be realized using MUXes by implementing the sum and
carry logic as a combination of multiplexed inputs.
 The MUX selects between possible outputs of sum and carry based on inputs A,
B, and carry-in.
Step 1 - To implement a full adder using MUX, we need to first create the truth table of
the full adder.
 Truth Table for Full Adder -

Inputs Outputs

A B C-In Sum C-Out

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Step 2 - We need to find out the minterms for the Sum and Carry output from the truth
table.

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For Sum - f ( A, B, C-In) = Σ ( 1,2,4,7 )

For Carry: - f ( A, B, C-In) = Σ ( 3,5,6,7 )

Step 3 - Now we need the equations for Sum and Carry. To find that we will create the
Design Table for Sum and Carry output.
Design Table for Sum Output :

For Sum the minterms (1,2,4,7 ), outputs are HIGH so they are circled in the design table.
 For D0 only 4 is HIGH which corresponds to A in table, So the D0 input for the
MUX(M0) will be A.
 The same rule follows for the other inputs - D1=A', D2=A', D3=A.

Design Table for Carry Output :

For Carry ( 3, 5, 6, 7 ), outputs are HIGH, so they are circled in the design table, just like the
design table for sum.
 Here for the D0 input 0 and 4, both are LOW, so input to the MUX will be 0
 For D3 both 3 and 7 are HIGH, so the input to MUX will be 1.
 D1 and D2 will follow the previous rule and will be D1=A and D2=A

Logic_circuit:

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Flip-Flops Using MUX
 Flip-flops like master-slave D flip-flops can be built using MUXes to control data
flow and clock gating.
 MUX selects between the current state and input data depending on clock and
enable signals to store state.

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D-Latch Using MUX
 A D-latch can be implemented using a 2:1 MUX where the input D and current
latch output are inputs to the MUX.
 The enable signal acts as the select line to either pass new data or hold the existing
output, effectively latching the data.

Design 5x1 MUX using 2x1 MUX:

S0 S1 S2 OUTPUT

0 0 0 u

0 0 1 v

0 1 0 w

0 1 1 x

1 x x y

LOGIC CIRCUIT:

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The first two MUXes at the left use s0 as the select line:
 The upper MUX selects between inputs u (when s0=0) and v (when s0=1).
 The middle MUX selects between w (when s0=0) and x (when s0=1).
 The outputs of the previous level’s two MUXes are routed as inputs to the middle right
MUX, which uses s1 as its select line:
 If s1=0, the output from the “u/v” MUX is chosen.
 If s1=1, the output from the “w/x” MUX is chosen.
 The bottom input y connects directly as one input to the final MUX at the right.
 The other input to the final MUX is the output from the “second level” MUX.
 The final MUX uses s2 as the select line to choose between:
 The output of the upper path (combining u, v, w, x via the first two levels, based
on s1 and s0)
 y (bypassing the upper path)
Output:
 he output m reflects a value derived from u,v,w,x,y based on the s2,s1,s0 select lines.
 This structure is similar to a 5-to-1 multiplexer, where:
 000 selects u
 001 selects v
 010 selects w
 011 selects x
 1xx (when s2=1, regardless of s1,s0) selects y

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Using DEMUX to realize logic gates:
 A demultiplexer is a logic circuit with one input and multiple outputs.

 Design a 1:2 demux using basic universal logic gates. NAND & NOR gates are called
as universal logic gates. The 1:2 demux logic can be implemented using only NAND
gates.

CONCEPT:
Whenever both the inputs of NAND gate are tied together as single input, it works as a NOT
gate. Whereas a NAND gate followed by a NOT gate gives an AND logic. Using these concepts
a 1:2 demux can be designed as shown in figure

The function table of a 1:2 demux is tabulated. Function table

The expressions for outputs Y0 & Y1 can be formulated by considering only those FPs for
which the output is 1. Y0 = A’. Din Y1 = A . Din The simplified function can be tabulated as:

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INTERVIEW QUESTIONS:
1. Define fan-in and fan-out.
2. What is a hazard in a combinational circuit?
3. What are static-1 and static-0 hazards?
4. What causes glitches in combinational logic circuits?
5. Explain the difference between MUX and DEMUX.
6. What is a priority encoder?
7. How many select lines are needed for a 16×1 MUX?
8. How do you design a 4×1 MUX using 2×1 MUXes?
9. Can a MUX implement basic logic gates?
10. How can you implement an AND gate using a MUX?
11. How can a DEMUX be used to realize logic functions?
12. What is a ripple carry adder?
13. What is propagation delay?

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