Subject Code: R23MSCST017
MODEL PAPER
[Link] VI Semester Regular Examinations, March- 2026
MVGR College of Engineering (Autonomous)
Microprocessors and Interfacing
(CSE & Allied)
Duration: 3 Hours Max. Marks.: 70.
Question paper consists of two parts (Part- A & Part- B)
PART-A
Answer all Questions. Each question carries 2 marks.
1. Explain about multiplexed address/data bus in 8086. 2M
2. Examine how segment and offset registers in the 8086 microprocessor work together to 2M
generate a physical address, illustrating the process with an example.
3. List the addressing modes of 8086 microprocessors. 2M
4. Examine the following instruction sequence and explain the output in 8086. 2M
PUSH AX
PUSH BX
POP AX
POP BX
5. What is the purpose of the EQU directive? 2M
6. Illustrate the formula used to determine the delay produced by a loop. 2M
7. State the primary functions performed by the 8255 PPI. 2M
8. State the functions of the TXD and RXD pins in the 8251 USART. 2M
9. Write the major components of the 8051 microcontrollers. 2M
10. What is the purpose of the TMOD register in 8051? 2M
PART-B
Answer any one of the two questions from each unit. Each question carries 10 marks.
UNIT-I
Q1 A i. Explain the architecture of 8086 Microprocessors with neat diagram. 7M
ii. How QS1 and QS0 signals indicate the 8086-instruction queue status and what is the work of 3M
processor at each state.
(OR)
Q1 B i. Draw and explain about each pin of 8086 microprocessor. 7M
ii. Analyze the concept of odd–even memory banking in the 8086 and discuss its effect on 3M
memory read and write operations.
UNIT-II
Q2 A i. List the Logical Instructions. Explain each instruction with example. 7M
ii. Examine the behavior of repeated rotate operations on the AL register in 8086 by developing 3M
an assembly program and analyzing how many rotations are needed to regain the original
data.
(OR)
Q2 B i. Explain string manipulation instructions in 8086 with example. 7M
ii. Analyze how the NOP and WAIT instructions contribute to processor idle behavior and 3M
synchronization in the 8086 microprocessor.
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Subject Code: R23MSCST017
UNIT-III
Q3 A i. List and explain the steps involved in assembling, linking, loading, and debugging an 8086 7M
program.
ii. Examine how misuse of assembler directives can lead to logical errors and debugging 3M
difficulties, and analyze these effects with examples.
(OR)
Q3 B i. Construct an 8086 assembly program showing the operation of a software interrupt. 7M
ii. Analyze how the 8086 handles an interrupt request and transfers program control to the 3M
Interrupt Service Routine.
UNIT-IV
Q4 A i. Explain the architecture of 8255 PPI with neat diagram 7M
ii. Evaluate how the 8255 Programmable Peripheral Interface distinguishes between control- 3M
word and data-word operations, and assess the role of the A0 and A1 address lines in
enabling this differentiation.
(OR)
Q4 B i. Draw and explain the pin diagram of the 8257 DMA controller in detail. 7M
ii. Analyze the sequence of events by which the DMA controller coordinates with the system 3M
bus during DMA data transfer.
UNIT-V
Q5 A i. Explain the architecture of 8051 microcontrollers with neat diagram. 7M
ii. Analyze the mechanism by which the RS1 and RS0 bits in the PSW influence register bank 3M
switching in the 8051 microcontroller.
(OR)
Q5 B i. Describe the TMOD register of 8051 microcontroller and explain the function of each field. 7M
ii. Analyze the mechanism by which the 8051 timer overflow flag helps in determining precise 3M
time intervals.
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