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Simulation Exercise 2

The document outlines a design task for a two-stage amplifier using LTSpice in TSMC 180nm technology, specifying parameters such as VDD, input resistance, and gain requirements for both the Common-Gate and Common-Drain stages. It requires the designer to determine transistor sizes, bias voltages, and component values to meet the specifications while ensuring all transistors remain in saturation. Additionally, the report must include a design procedure, transient simulation results, and an AC analysis of gain variation with frequency.

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6 views1 page

Simulation Exercise 2

The document outlines a design task for a two-stage amplifier using LTSpice in TSMC 180nm technology, specifying parameters such as VDD, input resistance, and gain requirements for both the Common-Gate and Common-Drain stages. It requires the designer to determine transistor sizes, bias voltages, and component values to meet the specifications while ensuring all transistors remain in saturation. Additionally, the report must include a design procedure, transient simulation results, and an AC analysis of gain variation with frequency.

Uploaded by

pratikjaisal
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Simulation Exercise – 2

Consider the two-stage amplifier topology shown in the circuit below. The first stage is a Common-
Gate (CG) amplifier, while the second stage is a Common-Drain (CD) amplifier. vin is the amplifier input and
vout is the amplifier output. You can assume Rin to be zero (vin is driven by an ideal input source).

Design the two-stage amplifier using LTSpice in TSMC 180nm technology with the following specifications.

a. VDD = 1.8V
b. Small signal input resistance of the two-stage amplifier is 50 W.
c. Small signal gain of CG amplifier is 10.
d. Small signal gain of CD amplifier is 0.9.
e. Load resistance RL is 50 W.
f. Peak-to-Peak output swing (vout) should be 0.9 V.
g. The dc-gate bias voltage of transistor M3 must be 1.3V.
h. The minimum input frequency is 1 kHz.
i. Channel length L of all the transistors is 1µm.

Note that M1 and M4 must be biased using the same gate voltage VB0. You can adjust the W/L of the
transistors to get the required current based on your calculations. Although the transistors in TSMC180 have
a finite l, ignore them for your hand-calculations for simplicity. Then observe and report the effect of l. Note
that, you can achieve these specifications only if all the transistors are always in saturation.

You must find the suitable sizes for transistors M1 to M4, values for VB0, VB1, C1, C2 and RD so that all the
specifications are met. You should derive the small signal gain of CG and CD amplifiers which will aid you
in your design.

You will need to submit the following results in your report.

• Detailed design procedure with equations justifying your design choices

• Plot of vout vs. time (transient simulation) for vin = A*cos (2p10000t), for A = 0.025, 0.05 and 0.1V. If
your design is correct, you should see what is happening to the output when A is 0.1V. Explain your
observations.

• Plot the variation of gain (vout/vin) with input frequency swept from 10 Hz to 1MHz. You can do this
using AC analysis in LTSpice. The x-axis of your plot must be in log scale.

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