Module-3 Input and Output Organization

Accessing I/O-Devices:
A single bus-structure can be used for connecting I/O-devices to a computer. The
simple arrangement of connecting set of I/O devices to memory and processor by means
of system bus is as shown in the figure. Such an arrangement is called as Single Bus
Organization.

 The single bus organization consists of

 Memory
 Processor
 System bus
 I/O device
 The system bus consists of 3 types of buses:
 Address bus (Unidirectional)
 Data bus (Bidirectional)
 Control bus (Bidirectional)
 The system bus enables all the devices connected to it to involve in the data transfer
operation.
 The system bus establishes data communication between I/O device and processor.

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 Each I/O device is assigned a unique set of address.

 When processor places an address on address-lines, the intended-device
responds to the command.
 The processor requests either a read or write-operation.
 The requested-data are transferred over the data-lines

Steps for input operation:

 The address bus of system bus holds the address of the input device.

 The control unit of CPU generates IORD Control signal.

 When this control signal is activated the processor reads the data from the
input device(DATAIN) into the CPU register.
Steps for output operation:
 The address bus of system bus holds the address of the output device.

 The control unit of CPU generates IOWR control signal.

 When this control signal is enabled CPU transfers the data from
processor register to outputdevice(DATAOUT)

There are 2 schemes available to connect I/O devices to CPU

1. Memory mapped I/O:
 In this technique both memory and I/O devices can share the common memory
to store theinstruction as well as the operands.
 Memory related instructions are used for data transfer between I/O and processor.
 In case of memory mapped I/O input operation can be implemented as,
MOVE DATAIN, R0
 This instruction sends the contents of location DATAIN to register R0. Similarly output can be
implemented as,
MOVE R0, DATAOUT
2. I/O Mapped I/O:
 In this technique CPU separates address space for memory and I/O devices.

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 Hence two sets of instruction are used for data transfer.

 One set for memory operations and another set for I/O operations.
 The I/O operation can be implemented as, IN AL, DX
 This instruction reads one byte of data from the I/P register whose address is
store in DX register into AL register.
 The O/P operation can be implemented as, OUT DX, AL
 This instruction transfer the contents of AL register into the O/P register (DATA OUT)
whose address is stored in DX register.

Comparison between I/O mapped I/O and Memory mapped I/O:

I/O Interface for an Input Device:

The hardware arrangement of connecting I/P device to the system bus is as shown in the fig.

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This hardware arrangement is called as I/O interface. The I/O interface consists of 3
functional devices namely:
1) Address Decoder:
 Its function is to decode the address in-order to recognize the input
device whose address isavailable on the unidirectional address bus.
 The unidirectional address bus of system bus is connected to input of the
address decoder asshown in figure
2) Control Circuit:
 The control bus of system bus is connected to control circuit as shown in the fig.
 It controls the read write operations with respect to I/O device.
3) Status & Data register:
 It specifies type of operation (either read or write operation) to be performed on
I/O device.
4) Data Register:
It stores the data to be read from input device to or it holds the data to be written into
outputdevice.
There are 2 types:
DATAIN - Input-buffer associated with keyboard.
DATAOUT -Output data buffer of a display/printer.

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Program Controlled I/O:

 To explain the concept of program controlled I/O consider two operations
namely inputoperation and output operation.
a) Input operation:
 It is the process of transferring ASCII value of a character
from DATA IN registerto CPU register.
b) Output operation:
 It is the process of transferring ASCII value of a character
from CPU register toDATA OUT register.
 Design 2 sets of instruction for input and output operations respectively,
 These 2 sets of instructions are stored in memory of the CPU. Now allow
the CPU to execute this program in-order to control the input and output
operation.
 “It is the process of controlling the input and output operations by executing 2
sets of instruction, one set for input operation and the next set for output
operation.”
Interrupt:
 It is an event which suspends the execution of one program and begins the
execution of another program.
 The arrival of interrupt causes the processor to transfer the execution control
from main programto sub program.
 To explain the concept of interrupt, consider the following two programs namely:

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The following steps take place when the interrupt related instruction is executed:
 It suspends the execution of current instruction i.
 Transfer the execution control to sub program from main program.
 Increments the content of PC by 4 memory location.
 It decrements SP by 4 memory locations.
 Pushes the contents of PC into the stack segment memory whose address is stored in
SP.
 It loads PC with the address of the first instruction of the sub program.

The following steps takes place when return instruction is executed

 It transfers the execution control from sub program to main program.
 It retrieves the content of stack memory location whose address is stored in SP into
the PC.
 After retrieving the return address from stack memory location into the
PC it increments theContent of SP by 4 memory location.
Interrupt Latency is a delay between
→ time an interrupt-request is received and
→ start of the execution of the ISR.
• Generally, the long interrupt latency in unacceptable.

Interrupt Hardware:
 The external device (I/O device) request the processor by activating one bus
line and this bus lineis called as interrupt request line.
 The one end of this interrupt request line is connected to input power supply
by means of pull upregister is as shown in the fig.
 Another end of interrupt request line is connected to INTR (Interrupt
request) signal ofprocessor as shown in the fig.

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 The I/O device is connected to interrupt request line by means of switch as shown in
the fig.
 When all the switches are open the voltage drop on interrupt request line is equal to
the VDD.
 This state is called as in-active state of the interrupt request line.
 The I/O device interrupts the processor by closing its switch.
• When switch is closed the voltage drop on the interrupt
request line is found to be zero. Therefore INTR=0 and
INTR=1.
• The signal on the interrupt request line is logical OR of
requests from the several I/O devices. Therefore,
INTR=INTR1 + INTR2 +……+ INTRn

Enabling and Disabling the Interrupts:

• All computers fundamentally should be able to enable and disable interruptions as
desired.
• The problem of infinite loop occurs due to successive interruptions of active INTR
signals.
• There are 3 mechanisms to solve problem of infinite loop:
1) Processor should ignore the interrupts until execution of first instruction of the
ISR.

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2) Processor should automatically disable interrupts before starting the execution

of the ISR.
3) Processor has a special INTR line for which the interrupt-handling circuit.
Interrupt-circuit responds only to leading edge of signal. Such line is
called edge-triggered.
• Sequence of events involved in handling an interrupt-request:
1) The device raises an interrupt-request.
2) The processor interrupts the program currently being executed.
3) Interrupts are disabled by changing the control bits in the processor status
register (PS).
4) The device is informed that its request has been recognized.
In response, the device deactivates the interrupt-request signal.
5) The action requested by the interrupt is performed by the interrupt-service
routine.
6) Interrupts are enabled and execution of the interrupted program is resumed.

Handling Multiple Devices:

While handling multiple devices, the issues concerned are:
 How can the processor recognize the device requesting an interrupt?
 How can the processor obtain the starting address of the appropriate ISR?
 Should a device be allowed to interrupt the processor while
another interrupt isbeing serviced?
 How should 2 or more simultaneous interrupt-requests be handled?
Vectored Interrupt:
• A device requesting an interrupt identifies itself by sending a special-code to processor
over bus.
• Then, the processor starts executing the ISR.
• The special-code indicates starting-address of ISR.
• The special-code length ranges from 4 to 8 bits.

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• The location pointed to by the interrupting-device is used to store the staring address to
ISR.
• The staring address to ISR is called the interrupt vector.
• Processor
→ loads interrupt-vector into PC &
→ executes appropriate ISR.
• When processor is ready to receive interrupt-vector code, it activates INTA line.
• Then, I/O-device responds by sending its interrupt-vector code & turning off the INTR
signal.
• The interrupt vector also includes a new value for the Processor Status Register.
Interrupt Nesting:

• A multiple-priority scheme is implemented by using separate INTR & INTA lines for
each device
• Each INTR line is assigned a different priority-level as shown in Figure.
• Priority-level of processor is the priority of program that is currently being executed.
• Processor accepts interrupts only from devices that have higher-priority than its own.
• At the time of execution of ISR for some device, priority of processor is raised to that of
the device.
• Thus, interrupts from devices at the same level of priority or lower are disabled.

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Privileged Instruction
• Processor's priority is encoded in a few bits of PS word. (PS = Processor-Status).
• Encoded-bits can be changed by Privileged Instructions that write into PS.
• Privileged-instructions can be executed only while processor is running in Supervisor
Mode.
• Processor is in supervisor-mode only when executing operating-system routines.
Privileged Exception
• User program cannot
→ Accidently or intentionally change the priority of the processor &
→ disrupt the system-operation.
• An attempt to execute a privileged-instruction while in user-mode leads to a Privileged
Exception.

Simultaneous Requests:
Daisy Chain
• The daisy chain with multiple priority levels is as shown in the figure.

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 The interrupt request line INTR is common to all devices as shown in the fig.
 The interrupt acknowledge line is connected in a daisy fashion as shown in the figure.
 This signal propagates serially from one device to another device.
 The several devices raise an interrupt by activating INTR signal. In response to
the signal, processortransfers its device by activating INTA signal.
 This signal is received by device 1. The device-1 blocks the propagation of
INTA signal to device-2,when it needs processor service.

 The device-1 transfers the INTA signal to next device when it does not require the processor
service.
 In daisy chain arrangement device-1 has the highest priority.
 Advantage: It requires fewer wires than the individual connections.

Arrangement of Priority Groups:

• In this technique, devices are organizes in a group and each group is connected
to the processor at adifferent priority level.
• Within a group devices are connected in a daisy chain fashion as shown in the figure.

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Direct Memory Address (DMA):

 It is the process of transferring the block of data at high speed in between main
memory and external device (I/O devices) without continuous intervention of
CPU is called as DMA.
 The DMA operation is performed by one control circuit and is part of the I/O interface.
 This control circuit is called DMA controller. Hence DMA transfer operation is
performed by DMAcontroller.
 To initiate Directed data transfer between main memory and external devices
DMA controller needsparameters from the CPU.
 These 3 Parameters are:
1) Starting address of the memory block.
2) No of words to be transferred.
3) Type of operation (Read or Write).
After receiving these 3 parameters from CPU, DMA controller establishes directed
data transfer operation between main memory and external devices without the
involvement of CPU.
• Register of DMA Controller:
It consists of 3 type of register:
Starting address register:
The format of starting address register is as shown in the fig. It is used to store
the starting addressof the memory block.

Word-Count register:
The format of word count register is as shown in fig. It is used to store the no of words

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Module-3 Input and Output Organization

to be transferredfrom main memory to external devices and vice versa.

Status and Controller register:
The format of status and controller register is as shown in fig.
a) DONE bit:
 The DMA controller sets this bit to 1 when it completes the direct data
transfer between mainmemory and external devices.
 This information is informed to CPU by means of DONE bit.
b) R/W (Read or Write):
 This bit is used to differentiate between memory read or memory write operation.
 The R/W = 1 for read operation and
= 0 for write operation.
 When this bit is set to 1, DMA controller transfers the one block of data
from external deviceto main memory.
 When this bit is set to 0, DMA controller transfers the one block of data
from main memoryto external device.
c) IE (Interrupt enable) bit:
 The DMA controller enables the interrupt enable bit after the completion
of DMA operationd)
d) Interrupt request (IRQ):
 The DMA controller requests the CPU to transfer new block of data
from source todestination by activating this bit.
The computer with DMA controller:
 The DMA controller connects two external devices namely disk 1 and disk 2 to
system bus as shown in the above fig.
 The DMA controller also interconnects high speed network devices to system
bus as shown in the above fig.
 Let us consider direct data transfer operation by means of DMA controller
without the involvement of CPU in between main memory and disk 1 as indicated
by dotted lines (in the fig.).

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Module-3 Input and Output Organization

 To establish direct data transfer operation between main memory and disk 1.
DMA controllerrequest the processor to obtain 3 parameters namely:
 1)Starting address of the memory block.
 2)No of words to be transferred.
 3)Type of operation (Read or Write).
 After receiving these 3 parameters from processor, DMA controller directly
transfers block ofdata main memory and external devices (disk 1).
 This information is informed to CPU by setting respective bits in the status and
controllerregister of DMA controller.
 These are 2 types of request with respect to system bus
 1). CPU request.
 2). DMA request.
 Highest priority will be given to DMA request.
 Actually the CPU generates memory cycles to perform read and write operations.
 The DMA controller steals memory cycles from the CPU to
perform read and writeoperations. This approach is called as
“Cycle stealing”.
 An exclusive option will be given for DMA controller to transfer block of data
from external devices to main memory and from main memory to external
devices. This technique is called as “Burst mode of operation.”

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