UNIT-4

Sequential Logic Circuit

Dr Sirisha Daggubati
A combinational Logic circuit could be defined as a circuit whose present output depends only on the present
inputs.

Present Present

The example of Combinational Circuit include:

•Half Adder
•Full Adder
•Half Subtractor
•Full Subtractor
•Encoder
•Decoder
•Multiplexer
•De-Multiplexer
•Magnitude Comparator
In sequential logic circuit the present output depends on the present input as well as past output
Present 1 Decimal Counter: Counts from 0 to 9 [Every time it adds 1 to previous output]
Present
Time Present Past/previo Present
Past/previous Input us Output Output
Output
T0 1 0 1
T1 1 1 2
T2 1 2 3
Sequential Logic Circuit T3 1 3 4

We required to store previous output T4 1 4 5

So we need Memory T5 1 5 6
These memory elements are typically latches and flip-flops
T6 1 6 7
T7 1 7 8
• Latches and flip-flops are the basic elements for storing information.
• One latch or flip-flop can store one bit of information.
• The main difference between latches and flip-flops
• Latches, their outputs changes immediately when their inputs change.
• Flip-flops: Their output changes only when there is a change in clock signal.
• There are basically four main types of latches and flip-flops: SR, D, JK, and T.
What is Flip-Flop?
• Flip-flop is a basic digital memory circuit, which stores one bit of information.
• Flip flops are the fundamental blocks of most sequential circuits.
• It is also known as a bistable multivibrator or a binary or one-bit memory.
• Flip-flops are used as memory elements in sequential circuits.
• There are basically four main types of and flip-flops:
• SR flip-flop
• D flip-flop
• JK flip-flop Key Difference Between Flip Flop and Latch
• T flip-flop
Latch Flip Flop
Latch alters the output based on The flip-flop output changes only
the changes in input constantly. when the clock pulse is activated
along with the input change.
In the absence of clocks, latches As clock signals synchronise
operate asynchronously. operations of the flip-flop, it
operates synchronously.
Latches are created with logic Flip-flops consist of a latch and a
gates. clock together as one unit.
0 1

0 1
 0 1

1
1 0

1 1

0
1

0 1
0 1

0
1

1 0

0
1
1 0

0 1

0 1
 1
0

0
1

0 0
 D - Latch

• The D Latch is a logic circuit most

frequently used for storing data in digital
systems.
• It is based on the S-R latch, but it doesn’t
have an “undefined” or “invalid” state
problem.
 0 R
0

=0 0 Memory
0
X 0
0 S
 1 1 R 0
1
1 0 1
0
=1 0 Memory
0
1 1 0
0
0 S
0
 0 0 R 1
1
1 0 1 0
=1 0 Memory
0
0 1
1 1
1 1 S

D latch is also known as a transparent latch,

data latch, or gated latch
 Latch
• Latches are the basic memory elements for storing information.
• One latch or flip-flop can store one bit of information.
• Latches, their outputs changes immediately when their inputs change.
• There are basically four main types of latches and flip-flops:
• SR Latch
• D Latch
• JK Latch
• T Latch
 SR Latch
JK Latch
• JK latch has two inputs J and K.
• JK latch is just like SR latch, but it eliminates
the undefined state of SR latch.

1 1 Qn=0 0 0
0
1 1
Any input is 0 output is 1

0 Qn’=1
1
0
0 1
JK Latch
• JK latch has two inputs J and K.
• JK latch is just like SR latch, but it eliminates
the undefined state of SR latch.

1 1 Qn+1=0 Qn=0 0 0
0
1 1
Any input is 0 output is 1

0 Qn’=1
1
0
0 1
JK Latch
• JK latch has two inputs J and K.
• JK latch is just like SR latch, but it eliminates
the undefined state of SR latch.

0 1 Qn=1 0 0
0
0 1
Any input is 0 output is 1

1 Qn’=0
0
1 0
1
JK Latch
• JK latch has two inputs J and K.
• JK latch is just like SR latch, but it eliminates
the undefined state of SR latch.

0 1 Qn+1=1 Qn=1 0 0
0
0 1 1
Any input is 0 output is 1

1 Qn’=0
0
1 0
1
JK Latch
• JK latch has two inputs J and K.
• JK latch is just like SR latch, but it eliminates
the undefined state of SR latch.

1 1 Qn=0 0 0
0
1 1 1
Any input is 0 output is 1
0
1

0 Qn’=1
1
1 1
0
JK Latch
• JK latch has two inputs J and K.
• JK latch is just like SR latch, but it eliminates
the undefined state of SR latch.

1 1 Qn+1=0 Qn=0 0 0
0
1 1 1
Any input is 0 output is 1
0 0
1

0 Qn’=1
1
0 1
JK Latch
• JK latch has two inputs J and K.
• JK latch is just like SR latch, but it eliminates
the undefined state of SR latch.

0 1 Qn=1 0 0
0
1 1 1
Any input is 0 output is 1
0 0
1

1 Qn’=0
1
0 1
1
JK Latch
• JK latch has two inputs J and K.
• JK latch is just like SR latch, but it eliminates
the undefined state of SR latch.

0 1 Qn+1=0 Qn=1 0 0
0
1 1 1
Any input is 0 output is 1
0 0
1 0

1 Qn’=0
1
0 1
1
JK Latch
• JK latch has two inputs J and K.
• JK latch is just like SR latch, but it eliminates
the undefined state of SR latch.

1 0 Qn=0 0 0
1
1 1 1
Any input is 0 output is 1
0 0
1 0

Qn’=1 0
0
0 1
1
0 1
JK Latch
• JK latch has two inputs J and K.
• JK latch is just like SR latch, but it eliminates
the undefined state of SR latch.

1 0 Qn+1=1 Qn=0 0 0
1
1 1 1
Any input is 0 output is 1
0 0
1 0

Qn’=1 0 1
0
0 1
1
0 1
JK Latch
• JK latch has two inputs J and K.
• JK latch is just like SR latch, but it eliminates
the undefined state of SR latch.

0 1 Qn=1 0 0
1
0 1 1
Any input is 0 output is 1
0 0
1 0

Qn’=0 0 1
1
0 1
0
1 1
JK Latch
• JK latch has two inputs J and K.
• JK latch is just like SR latch, but it eliminates
the undefined state of SR latch.

0 1 Qn+1=1 Qn=1 0 0
1
0 1 1
Any input is 0 output is 1
0 0
1 0

Qn’=0 0 1
1
0 1 1
0
1 1
JK Latch
• JK latch has two inputs J and K.
• JK latch is just like SR latch, but it eliminates
the undefined state of SR latch.

1 0 Qn=0 0 0
1
1 1 1
Any input is 0 output is 1
0 0
1 0

Qn’=1 0 1
0
1 1 1
1
0 1
0

1
JK Latch
• JK latch has two inputs J and K.
• JK latch is just like SR latch, but it eliminates
the undefined state of SR latch.

1 0 Qn+1=1 Qn=0 0 0
1
1 1 1
Any input is 0 output is 1
0 0
1 0

Qn’=1 0 1
0
1 1 1
1
0 1
0 1

1
JK Latch
• JK latch has two inputs J and K.
• JK latch is just like SR latch, but it eliminates
the undefined state of SR latch.

0 1 Qn=1 0 0
1
1 1 1
Any input is 0 output is 1
0 0
1 0

Qn’=0 0 1
1
1 1 1
1
1 0
0 1

1
JK Latch
• JK latch has two inputs J and K.
• JK latch is just like SR latch, but it eliminates
the undefined state of SR latch.

0 1 Qn+1=0 Qn=1 0 0
1
1 1 1
Any input is 0 output is 1
0 0
1 0

Qn’=0 0 1
1
1 1 1
1
1 0
0 1
JK Latch

J K Qn+1 State
0 0 Qn No
Change
0 1 0 Reset
1 0 1 Set
1 1 Qn’ Toggle
 Latch
• Latches are the basic memory elements for storing information.
• One latch or flip-flop can store one bit of information.
• Latches, their outputs changes immediately when their inputs change.
• There are basically four main types of latches and flip-flops:
• SR Latch
• D Latch
• JK Latch
• T Latch
 T-Latch

1 1 Qn+1
0
0 1

0
0
1 1
1
0

• Latches are the basic memory elements for storing information.

• One latch or flip-flop can store one bit of information.
• Latches, their outputs changes immediately when their inputs change.
• There are basically four main types of latches and flip-flops:
• SR Latch
• D Latch
• JK Latch
• T Latch
 T-Latch

1 1 Qn+1=0
0
0 1
0

0
0
1 1
1
0
 T-Latch

0 1 Qn+1=1
1
0 0
0

0 1

1
0
0 0
1
1
 T-Latch

1 0 Qn+1=1
0
1 1
0

1 1

1
0
1
1 1
1
0
 T-Latch

0 1 Qn+1=0
1
1 1
0
No change
1 1

1
1
1 Toggles
1 0
0 0
1
Construction of SR Flip Flop Using NAND Gates

1. Circuit Diagram of SR-Flip Flop

2. Working of SR-Flip Flop
3. Rewrite Truth Table in terms of Qn
(present state)& Qn+1(next state)
4. Characteristics Table of SR-Flip Flop
5. Characteristic Equation
6. Excitation Table
 1. Circuit Diagram of SR-Flip Flop
2. Working of SR-Flip Flop
3. Rewrite Truth Table in terms of Qn
0 1 (present state)& Qn+1(next state)
4. Characteristics Table of SR-Flip Flop
5. Characteristic Equation
1 6. Excitation Table

1
0

Truth Table of SR Flipflop

Clk S R Q Q’
1 0 0 Mem Mem Memo
ry
1 0 1
1 1 0
1 1 1
 1. Circuit Diagram of SR-Flip Flop
2. Working of SR Flip flop 2. Working of SR-Flip Flop
3. Rewrite Truth Table in terms of Qn
(present state)& Qn+1(next state)
4. Characteristics Table of SR-Flip Flop
5. Characteristic Equation
6. Excitation Table

0 1 0

1
1
0
1 Truth Table of SR Flipflop
Clk S R Q Q’
1 0 0 Mem Mem Memo
ry
1 0 1 0 1 Reset
1 1 0
1 1 1
 1. Circuit Diagram of SR-Flip Flop
2. Working of SR-Flip Flop
3. Rewrite Truth Table in terms of Qn
2. Working of SR Flip flop (present state)& Qn+1(next state)
4. Characteristics Table of SR-Flip Flop
5. Characteristic Equation
6. Excitation Table

1 0 1

1
0
1
0 Truth Table of SR Flipflop
Clk S R Q Q’
1 0 0 Mem Mem Memo
ry
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1
 1. Circuit Diagram of SR-Flip Flop
2. Working of SR-Flip Flop
3. Rewrite Truth Table in terms of Qn
1 0 (present state)& Qn+1(next state)
4. Characteristics Table of SR-Flip Flop
5. Characteristic Equation
1 6. Excitation Table

0
1

Truth Table of SR Flipflop

Clk S R Q Q’
1 0 0 Q Q’ Memo
ry
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 Invalid Invalid Invalid
 2. Truth Table of SR Flipflop 1. Circuit Diagram of SR-Flip Flop
Clk S R Qn Qn’ 2. Working of SR-Flip Flop
3. Rewrite Truth Table in terms of Qn
1 0 0 Q Q’ Memo
ry
(present state)& Qn+1(next state)
4. Characteristics Table of SR-Flip Flop
1 0 1 0 1 Reset 5. Characteristic Equation
1 1 0 1 0 Set 6. Excitation Table
1 1 1 Invalid Invalid Invalid
4. Characteristics Table of SR-Flip Flop
[Link] Truth Table in terms of Qn (present state)& Qn+1(next state)
Qn S R Qn+1
Clk S R Qn+1 0 0 0 0
CHARACTERISTIC TABLES
1 0 0 Qn Using the characteristic table, the 0 0 1 0
1 0 1 0 “next state” of a flip flop can be
obtained when the “inputs” and
0 1 0 1
1 1 0 1 “present state” of the flip flop are 0 1 1 Invalid
1 1 1 Invalid available.
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 Invalid
4. Characteristics Table of SR-Flip Flop
Qn S R Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 Invalid
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 Invalid

1. Circuit Diagram of SR-Flip Flop

EXCITATION TABLES
2. Working of SR-Flip Flop
This table can be used for finding the “inputs” of the flip flop
3. Rewrite Truth Table in terms of Qn
provided “present state” and “next state” values are available.
(present state)& Qn+1(next state)
4. Characteristics Table of SR-Flip Flop
5. Characteristic Equation
6. Excitation Table
 D Flip Flop
Block Diagram
A flip-flop is defined as a memory element that can store one bit of binary
data. A bit is the smallest unit of information that can have two possible values:
0 or 1. In D flip flop, the single input "D" is referred to as the "Data" input.

1 . Circuit Diagram of D Flipflop

 D Flip Flop

Working of D Flip Flop

When the data input is set to 1, the flip flop would be set, and when it is set to 0, the flip flop would
become reset

Truth Table
 5. Characteristic Equation

𝑄𝑛+1 =D

EXCITATION TABLES
4. Characteristics Table of SR-Flip Flop This table can be used for finding the “inputs” of the flip flop
provided “present state” and “next state” values are available.
Qn D Qn+1
0 0 0 Qn Qn+1 D
0 1 1 0 0 0
1 0 0 0 1 1
1 1 1 1 0 0
CHARACTERISTIC TABLES 1 1 1
Using the characteristic table, the
“next state” of a flip flop can be
obtained when the “inputs” and
“present state” of the flip flop are
available.
 If Clk=1, J=1, K=1, Q=1, Q’=0

0
1
1 1
1

1 1
0 0
1
1
1
 0
1
1 1→0
1

1 1
0 0→1
1
1
1
If Clk=1, J=1, K=1, Q=1 Q’=0
Race Around Condition in J K Flip-flop Output Q=0 , Q’=1
•For J -K flip-flop, if J =K=1, and if clk=1 for a long We understand that output is
period of time, then output Q will toggle as long as Toggled with Previous state
CLK remains high which makes the output
or uncertain.
•This is called a race around condition in J -K flip-
flop.
•We can overcome this problem by making the
=1 for very less duration. The circuit used to
overcome race around conditions is called the
Master S lave J K flip flop.
 T -Flipflop / Toggle Flip flop

• It is basically a JK Flipflop with J and K terminals permanently connected together.

Inputs Output
Clk T Output
1 0 Nochange
1 1 Toggles

Characteristics Table Excitation Table-T FlipFlop

Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0
Characteristic Equation of SR Flip Flop
Characteristic Equation of D Flip Flop
 Steps for Flip Flop Conversion
SR Flip Flop to D Flip Flop 1. Note the Available and Required FF
2. Write the Characteristic Table of Required FF
3. Write the Excitation Table of Available FF
Step:1 Available FF= SR , Required FF = D
4. Solve Boolean Expression
Step:2 Characteristic Table of Required FF
5. Draw Circuit
Step:3 Write the Excitation Table of Available FF

Step 4. Solve Boolean Expression

Step 5. Draw Circuit
 Steps for Flip Flop Conversion
1. Note the Available and Required
FF
2. Write the Characteristic Table of
Required FF
3. Write the Excitation Table of
Available FF
Characteristic Table Excitation Table
4. Solve Boolean Expression
5. Draw Circuit

•Present state: The state of the flip-flops before a clock pulse

occurs.
•Next state: The state of the flip-flops after a clock pulse
occurs. The next state is determined by the present state and
the input signals when the clock pulse occurs.
•Previous state: The state of the circuit before the present
state.
 Excitation Table

Characteristic Table
 Excitation Table

Characteristic Table
 Excitation Table

Characteristic Table
 Excitation Table

Characteristic Table
0 0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
SR Flip Flop to JK Flip Flop
 Steps for Flip Flop Conversion
1. Note the Available and Required FF
2. Write the Characteristic Table of Required
FF
3. Write the Excitation Table of Available FF
4. Solve Boolean Expression
Characteristic Table 5. Draw Circuit
Excitation Table
SR Flip Flop to T Flip Flop
 Steps for Flip Flop Conversion
1. Note the Available and Required FF
2. Write the Characteristic Table of Required FF
3. Write the Excitation Table of Available FF
4. Solve Boolean Expression
5. Draw Circuit
Characteristic Table

Excitation Table
Steps for Flip Flop Conversion
1. Note the Available and
Required FF
2. Write the Characteristic
Table of Required FF
3. Write the Excitation Table of
Available FF
4. Solve Boolean Expression
5. Draw Circuit
 By
Dr Sirisha Daggubati
Clk=1 Master FF will be activated
Clk=0 Slave FF will be activated
 ON OFF

Qm,
Qn
1 Clk=0

Qn
Q’m

Note****-At a time only one FF will be in ON state,

so the feedback connection will break.
Clk=1 Master ON—Slave 0ff—Output= Qm,Q’m
Clk=0 Master OFF—Slave ON—Output= Qn,Q’n

The next state output we have got will not have any effect on the master-
Hence there will not be any oscillations in the output-Race around
condition is eliminated
 OFF ON

Qm,
Qn=Qm
0 Clk=1

Qn=Q’m
Q’m

Note****-At a time only one FF will be in ON state,

so the feedback connection will break.
Clk=1 Master ON—Slave 0ff—Output= Qm,Q’m
Clk=0 Master OFF—Slave ON—Output= Qn,Q’n

The next state output we have got will not have any effect on the master-
Hence there will not be any oscillations in the output-Race around
condition is eliminated
 J=1, K=1, Qn=1 and Qn’=0

0 1 Qm=0
1 Qn=1
1

1 0
1
0 Qn=0
1
1 Qm=1
 J=1, K=1, Qn=1 and Qn’=0

0 Qm=0 Qm=0
1 1 0
1 1 Qn=1→0
1 1

0 1 1
1 1
0 Qn=0→1
1 0 1
1 Q’m=1 Q’m=1

Truth Table of Master Slave JK Flip Flop

Clk J(S) K(R) Qn+1 Q’n+1
1 0 0 Qn Q’n
1 0 1 0 1
1 1 0 1 0
1 1 1 Q’n Qn
 Trick to Remember Flip Flop Excitation Table
The excitation tables are used to determine the inputs of the flip-flop when the previous state and the next
state are given
Qn Qn+1 S R J K D T
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 0 1
1 1 X 0 X 0 1 0

Excitation Table-SR FlipFlop Excitation Table-JK FlipFlop Excitation Table-D FlipFlop Excitation Table-T FlipFlop
Qn Qn+1 S R Qn Qn+1 J K Qn Qn+1 D Qn Qn+1 T
0 0 0 X 0 0 0 X 0 0 0 0 0 0
0 1 1 0 0 1 1 X 0 1 1 0 1 1
1 0 0 1 1 0 X 1 1 0 0 1 0 1
1 1 X 0 1 1 X 0 1 1 1 1 1 0
 Counters
Basics, Types, Classifications, and Applications

Dr. Sirisha Daggubati

Clock is common to all flip flops Main clock is only applied to the first flip flop and
then for rest of flip flops the output of previous flip
flop is taken as a clock.
3 Bit Counter
Q2 Q1 Q0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Asynchronous (Ripple)
Up-Counter
Dr. Sirisha Daggubati
 Asynchronous (Ripple) Counter
Asynchronous (Ripple) Counter: We don’t provide same clock signal to all memory elements
Q: Design Three Bit Ripple Counter ? Or Design a, three-bit Asynchronous Up Counter.
.
Step:1 We need three memory Element, T-Flip Flop [ In T flipflop output will Toggle, when T=1 and Clock triggers]

FF-1 FF-2 FF-3

Asynchronous (Ripple)
Down Counter
Dr. Sirisha Daggubati
 Asynchronous (Ripple) Counter
Asynchronous (Ripple) Counter: We don’t provide same clock signal to all memory elements
Q: Design Three Bit Ripple Down Counter ? Or Design a, three-bit Asynchronous Down Counter.
.
Step:1 We need three memory Element, T-Flip Flop [ In T flipflop output will Toggle, when T=1 and Clock triggers]

FF-1 FF-2 FF-3

Modulo N Counter
Dr. Sirisha Daggubati
Modulo N Counter by Asynchronous Counter
 BCD Counter
or
Decade Counter
Dr. Sirisha Daggubati
2-Bit Synchronous Counter
Using JK Flip Flop
Dr. Sirisha Daggubati
 2-bit Synchronous Counter Using JK Flip Flop
Steps to Design Synchronous Counter
1. Identify number of bits and Flip Flops
2. Write Excitation Table of Flip Flop
3. Make State Diagram and State Table
4. Solve Boolean Expression
5. Make Circuit
State Diagram: The state diagram is the pictorial representation of the behavior of sequential circuits.
State Table:The information contained in the state diagram is transformed into a table called a state table.
3-Bit Synchronous Counter
Using T Flip Flop
Dr. Sirisha Daggubati
 3-bit Synchronous Counter Using Flip Flop
Steps to Design Synchronous Counter
1. Identify number of bits and Flip Flops
2. Write Excitation Table of Flip Flop
3. Make State Diagram and State Table
4. Solve Boolean Expression
5. Make Circuit
State Diagram: The state diagram is the pictorial representation of the behavior of sequential circuits.
State Table:The information contained in the state diagram is transformed into a table called a state table.
[Link] Synchronous Counter Asynchronous Counter
Clock is common to all flip flops Main clock is only applied to the first flip flop and
then for rest of flip flops the output of previous flip
flop is taken as a clock.
1.

2. Faster in operation Slower in Operation

3. Does not produce any decoding errors. Produces decoding error.

4. Also called Parallel Counter. Also called Serial Counter.

5. Designing as well implementation are complex Designing as well as implementation is very easy.

6. Operate in any desired count sequence. Operate only in fixed count sequence (UP/DOWN).

Synchronous Counter examples are: Ring Asynchronous Counter examples are: Ripple UP
7.
counter, Johnson counter. counter, Ripple DOWN counter.