SEMICONDUCTOR TECHNOLOGIES VIETNAM
CO., LTD
DIGITAL SYSTEM DESIGN LABORATORY
IMPLEMENTATION OF BASIC COMBINATION
LOGIC CIRCUIT USING VERILOG
1
I. EXPERIMENTS OBJECTIVES
This experiments are intended to implement Basic Combination Logic and Sequential Circuit in Verilog.
Interns are required to write a testbench to simulate the given example code and Top level module to
implement these codes in Simulation tools.
a) For each experiment write the Verilog Code in three method (dataflow, behavior and gate level)
c) For each model, Write the testbench to simulate this module.
II. PROCEDURE
II.1 LAB EXPERIMENT 1 : WRITE HDL CODE TO REALIZE ALL LOGIC GATES
Referenced Verilog codes in 3 methods ( Dataflow, behavior, gate level):
1. WRITE VERILOG HDL CODES TO SIMULATE AND IMPLEMENT THE FULL ADDER
CIRCUIT:
2. WRITE VERILOG HDL CODES TO SIMULATE AND IMPLEMENT THE RIPPLE CARRY
ADDER CIRCUIT:
3. WRITE VERILOG HDL CODES TO SIMULATE AND IMPLEMENT 2:1 MULTIPLEXER
2
CIRCUIT:
4. WRITE VERILOG HDL CODES TO SIMULATE AND IMPLEMENT 4:1 MULTIPLEXER
CIRCUIT:
3
4