Module 1:
Topic Key Points
Verilog Standards IEEE 1364 (95,01,05), IEEE 1800 System-Verilog
Application Areas Digital ICs, FPGA, verification, modelling
Abstraction Levels Behavioural → RTL → Structural → Switch
Data Types wire (net), reg (stored), constant
Operators logical, arithmetic, bitwise, reduction, relational, conditional
Numbers <size>’<base><number> ex., 2’b11, 4’hAB etc.
Ports input, output, inout
Primitives and, or, not, xor, nand, buf, tri-state, transistor
Application Areas
ASIC design, Custom processors, DSP cores, Cryptographic
Digital IC Design
hardware blocks
Implementing controllers, Image processing/Microprocessor
FPGA Design
based systems
Verification Testbench creation, Functional validation before fabrication
System Modelling Fast simulation models for hardware/software co-design
RTL (Register Transfer Level) Design Used to write synthesizable hardware
Abstraction Levels of Verilog
1. Behavioural Level (Algorithmic)
• Describes what the circuit does
• Uses always blocks, if, case, loops
• No need to specify gates
• Example: always @(posedge clk) begin q <= d; end
2. Register Transfer Level (RTL)
• Most used level for synthesis
• Describes transfers between registers and logic operations
• Example: assign sum = a + b;
3. Structural Level (Gate-Level)
• Describes hardware as interconnection of modules/gates
• Example: and (y, a, b);
Verilog Data Types
A. Net Data Types (wire, tri, etc.)
Used to represent connections between hardware elements.
Key Features:
• Driven by continuous assignments or gate/module outputs
• Cannot store values (no memory)
• Reflects actual electrical nets
Most common:
• wire — simple signal connection
• tri — tri-state connection
B. Register Data Types (reg)
• Store values until explicitly changed
• Used inside procedural blocks (always, initial)
• Not necessarily a hardware register unless triggered by clock
C. Constants
Number format: <size>’<base> <value>
Base Meaning Example
b binary 8'b10101010
d decimal 12'd255
h hex 16'hA2F3
o octal 6'o17
Verilog Ports
Ports define module input/output connections.
Types:
1. input
2. output
3. inout (bidirectional)
Rules:
• input and inout default to net type (wire)
• output can be:
o wire (default)
o reg (if assigned in procedural block)
Verilog Primitives
Gate-level primitives
Gate Example Syntax
and and (out, a, b);
or or (out, a, b);
xor xor (out, a, b);
not not (out, a);
nand nand (out, a, b);
nor nor (out, a, b);
buf buf (y, x);
bufif1 Tri-state buffer
Verilog Operators
Logical Operators Bitwise Operators
! Logical NOT ~ Bitwise NOT
&& Logical AND & Bitwise AND
^ Bitwise XOR
Reduction Operators Arithmetic Operators
&a AND all bits + addition
^a XOR all bits - subtraction
* multiplication
/ division
% modulus
Relational Operators Equality Operators
< less than == logical equality
> greater than != logical inequality
<= ≤ === case equality (includes X/Z)
>= ≥ !== case inequality
Concatenation Operator Conditional Operator
{,} assign y = {a, b}; (?:) assign y = (sel) ? a : b;
Module 2
Topic Description
Digital Systems Logic-based hardware
Embedded Hardware + software for specific
Systems tasks
Architecture High-level block design
Functional Design RTL coding + Simulation
Verification Ensuring correctness
Synthesis RTL → gates
Physical Design Layout creation
Optimization Improve area, speed, power
Representation Behavioural, RTL, Gate, Physical
Introduction to Design Methodology
• A design methodology is a structured approach used to design digital and embedded
systems systematically.
• It ensures that complex systems are built efficiently, correctly, and optimally in terms of area,
speed, and power.
• Design methodology is essential because modern chips contain millions to billions of
transistors, making manual design impossible without well-defined processes.
Digital Systems and Embedded Systems
A. Digital Systems
Digital systems process information in binary form (0s and 1s).
Examples:
• Microprocessors
• DSPs (Digital Signal Processors)
• Digital communication systems
• Controllers
Key Characteristics:
• High speed
• Low noise sensitivity
• Logical operations
• Implemented using transistors, gates, flip-flops, finite-state machines
B. Embedded Systems
An embedded system is a combination of hardware + software, designed to perform a specific task.
Examples:
• Smartphones
• Washing machines
• Automotive control units (ECU)
• IoT devices
Components:
• Microcontroller or processor
• Memory (RAM/ROM/Flash)
• Sensors & actuators
• Communication interfaces
• Real-time operating system (in advanced designs)
Features:
• Real-time behaviour
• Low power consumption
• Application-specific (not general-purpose)
Real-world Circuits
Real-world circuits are built considering non-ideal behaviours:
Non-ideal effects:
• Gate delays
• Noise
• Power consumption
• Temperature effects
• Parasitics (resistance, capacitance, inductance)
Types of real-world circuits:
• Digital: logic gates, counters, adders, multiplexers
• Analog: OP-AMP circuits, filters
• Mixed-signal: ADCs, DACs
• RF circuits: wireless communication modules
Understanding these is critical for translating a design idea into working hardware.
Design Methodology
Design methodology describes the steps followed to convert a specification into a manufactured
chip or working system.
The steps are:
1. System Specification
2. Architectural Design
3. Functional Design & Verification
4. RTL Coding
5. Logic Synthesis
6. Physical Design
7. Fabrication
8. Testing & Validation
A. Architecture Design
Architecture design defines:
• Overall system structure
• Functional blocks
• Data flow
• Communication protocols
• Memory organization
Example for a processor:
• ALU
• Register file
• Control unit
• Cache structure
• Pipeline stages
Architecture design answers:
• What blocks are required?
• How do they interact?
• What performance is needed?
Outputs of architecture stage:
• Block diagrams
• Timing diagrams
• High-level models (SystemC, MATLAB, Simulink)
B. Functional Design & Verification
Functional Design
Implements the architecture at RTL (Register-Transfer Level) using HDLs:
• Verilog
• VHDL
• system-Verilog
RTL describes:
• Clocked logic
• Combinational logic
• Data paths
• Control paths
Verification
Ensures the RTL matches the specification before hardware fabrication.
Methods:
• Testbenches
• Directed tests
• Constrained-random verification
• Code coverage and functional coverage
• Gate-level simulation
Verification is crucial — 70% of design time is spent on verification.
C. Synthesis
Synthesis converts RTL code → Gate-level netlist.
It maps high-level logic to actual standard cells (NAND, NOR, flip-flops, etc.).
Synthesis tools:
• Synopsys Design Compiler
• Cadence Genus
• Xilinx Vivado (FPGA)
Output:
• Netlist
• Area reports
• Timing reports
• Power reports
Constraints include:
• Clock frequency
• I/O delays
• Multi-cycle paths
D. Physical Design (Backend)
Physical design converts the synthesized gate-level netlist into a layout ready for chip fabrication.
Stages include:
1. Floor-planning
• Macro/block placement
• I/O placement
• Power grid design
2. Placement
• Place standard cells optimally
3. Clock Tree Synthesis (CTS)
• Build a balanced clock distribution network
• Minimize skew and insertion delay
4. Routing
• Connect all components with metal layers
5. RC Extraction
• Extract actual parasites
6. Timing Closure
• Ensure timing meets setup & hold requirements
7. DFM (Design for Manufacturability)
• Ensure chip can be fabricated reliably
Final output:
• GDSII or OASIS file
• Sent to fabrication (foundry)
Design Optimization
A. Area Optimization
Goal: reduce silicon area
Methods:
• Use smaller arithmetic units
• Optimize logic expressions
• Share common logic blocks
• Reduce pipeline registers
• Use multi-bit flip-flops
Smaller area reduces cost per chip.
B. Timing Optimization
Goal: meet clock frequency requirements
Techniques:
• Reduce critical path delay
• Add pipeline stages
• Balance logic levels
• Improve cell drive strength
• Reduce fan-out
• Perform retiming
Timing is measured as:
• Setup time
• Hold time
• Clock-to-Q delay
C. Power Optimization
Power = Dynamic + Static
Dynamic power:
P = α C V² f
Reduce by:
• Clock gating
• Lower voltage (DVFS)
• Reduce switching activity
Static power:
• Caused by leakage
Reduce by:
• Using high-Vt cells
• Power gating
• Multi-threshold CMOS
Power is critical for battery devices and IoT.
System Representation
Systems can be represented at multiple abstraction levels:
1. Behavioural Representation
• High-level algorithms
• Finite state machines
• Used for simulation
2. RTL Representation
• Registers, combinational logic
• Synthesizable Verilog/VHDL
3. Gate-Level Representation
• NAND/NOR logic
• Standard cell mapping
4. Physical Representation
• Layout polygons
• Placement and routing
• Parasitic components
5. System-Level Modelling
• UML diagrams
• MATLAB/Simulink
• Transaction-level modelling (TLM)
Each level represents the system differently for design, optimization, and verification purposes.
Module 4
Topic Description
Synthesis RTL → Gate-level translation
Combinational Logic assign statements, combinational always blocks
Tri-state and Bus Interface Z state, bus sharing logic
Sequential with Latches level-sensitive storage
Sequential with FFs edge-triggered flip-flops
Explicit FSMs next-state + output logic
Registered Logic pipelined combinational logic
State Encoding binary, one-hot, Gray-code
1. Introduction to Synthesis
Synthesis is the process of converting RTL (Register-Transfer Level) Verilog/VHDL code → gate-level
hardware using standard cells such as AND, OR, NAND, NOR, D-FF, latches, buffers, tri-state drivers,
etc.
Inputs to Synthesis:
• RTL Verilog
• Technology library (.lib)
• Timing constraints (clock period, input/output delays)
Outputs of Synthesis:
• Gate-level netlist
• Area, timing, and power reports
Major steps during synthesis:
1. Elaboration → expand modules, parameters
2. Boolean Optimization → simplify logic
3. Technology Mapping → map logic to available gates
4. Timing Optimization → resizing, buffering
5. Register mapping → infer flip-flops, latches
Synthesis ensures that the RTL description is translated to efficient hardware that meets timing, area
and power constraints.
2. Synthesis of Combinational Logic
Combinational logic has no memory; output depends only on current inputs.
Typical RTL forms:
assign y = (a & b) | (~a & c);
or
always @(*) begin
y = a ^ b;
end
During synthesis:
• Boolean equations are simplified
• Common sub-expressions are factored
• Logic is mapped to NAND/NOR gates
Rules for synthesizable combinational logic:
1. Always use always @(*) for combinational blocks
2. Ensure all outputs are assigned in all paths (avoid unintended latches)
3. Avoid delays (#5) — not synthesizable
4. Avoid infinite loops and initial blocks
Example Combinational Circuit (MUX)
assign y = sel ? b : a;
Synthesis maps this to multiplexor hardware from the standard cell library.
3. Synthesis of Three-State Devices and Bus Interfaces
Three-state devices drive:
• 1
• 0
• High-impedance (Z)
Used in bus interfaces where multiple devices share the same bus.
RTL Example:
assign bus = enable ? data : 8'bz;
Synthesis behavior:
• For ASIC flows: tri-state buffers may be mapped to tri-state standard cells or multiplexers (if
tri-state is not supported internally).
• For FPGA: true internal tri-state is usually not supported, so synthesis replaces it with a
multiplexer.
Bus example:
assign bus = (dev1_en) ? dev1_data :
(dev2_en) ? dev2_data :
8'bz;
Rule: Only one device must drive the bus at a time.
4. Synthesis of Sequential Logic with Latches
A latch is level-sensitive and synthesized when RTL describes storage that is:
• not clock-controlled
• produced by incomplete combinational assignment
Example (Latch Inference):
always @(*) begin
if (en)
q = d; // missing else → latch inferred
end
Synthesis Interpretation:
• Hardware latch cell is created
• When en = 1, q follows d
• When en = 0, q holds previous value
Guidelines:
• Avoid unintentional latches
• Use latches only when required (rare in RTL design)
5. Synthesis of Sequential Logic with Flip-Flops
Flip-flops are inferred with edge-triggered sensitivity.
Example:
always @(posedge clk)
q <= d;
Synthesis maps to D-Flip-Flop in the standard cell library.
Flip-flop with Reset:
always @(posedge clk or posedge rst)
if (rst)
q <= 0;
else
q <= d;
Synthesis behavior:
• Creates asynchronous reset FF
• If reset is inside clock block:
always @(posedge clk) begin
if (rst)
q <= 0;
else
q <= d;
end
Synthesizes to synchronous reset FF.
6. Synthesis of Explicit State Machines (FSMs)
FSMs follow state register + next-state logic structure.
Three recommended styles:
A. One always-block FSM
(Not recommended — mixing sequential & combinational logic
B. Two always-block FSM (recommended)
Block 1: Sequential (state register)
always @(posedge clk or posedge rst)
if (rst)
state <= S0;
else
state <= next_state;
Block 2: Combinational (next-state logic)
always @(*) begin
case (state)
S0: next_state = start ? S1 : S0;
S1: next_state = S2;
S2: next_state = S0;
endcase
end
Synthesis:
• Maps state register to flip-flops
• Maps next-state logic to gates
C. Three always-block FSM (best practice)
1. State register
2. Next-state logic
3. Output logic
This improves readability and synthesis results.
7. Registered Logic
Registered logic means combinational logic + registers at the outputs or inputs.
Example:
always @(posedge clk)
out <= a + b;
This ensures:
• Stable outputs
• Improved timing
• Pipeline behavior
Synthesis maps:
• a + b to adder logic
• out <= to flip-flops
Registered logic is crucial for meeting high-speed timing constraints.
8. State Encoding
FSM states must be encoded before synthesis.
Three common encoding styles:
1. Binary Encoding
Uses minimum bits:
For 8 states → 3 bits.
Pros:
• Small area
Cons:
• More complex logic → slower
2. One-Hot Encoding
One flip-flop per state:
Only one FF is ‘1’ at a time.
Pros: Very fast next-state logic
Cons: More flip-flops (area increases)
Ideal for FPGAs.
3. Gray Encoding
Only one-bit changes between states.
Pros:
• Reduces switching noise & glitches
• Useful for asynchronous domains
Encoding Example:
parameter S0 = 3'b000,
S1 = 3'b001,
S2 = 3'b011,
S3 = 3'b010;
Synthesis Tools:
• Automatically choose best encoding unless fixed by designer
• Options: one-hot, binary, gray, or auto