MICROPROCESSOR AND MICROCONTROLLER

AIM

 To learn the concepts of microprocessor, microcontroller and its applications

 To design microprocessor & microcontroller along with interfacing devices
 To understand the impact of microcontroller in engineering applications.

OBJECTIVE
 Provide an overview of difference between microprocessor and micro controller.
 Provide background knowledge and core expertise in 8086 microprocessor and 8051
microcontroller.
 Provide an overview of architecture and the pin configuration of 8086 microprocessor
and Intel 8051 microcontroller.
 Exhibit programming skills, choose suitable hardware and program the devices to
solve engineering problems.
 Overview about advanced microcontroller like AVR,PIC and ARM

PRE TEST
1)The binary number 11111010 is equivalent to hexadecimal number is …………..
a) FA b)AF c)2A d)F1

2)2’s complement of binary number 0101 is ………..

a) 1011 b) 1111 c) 1101d)1110

3) A device which converts BCD to seven segments is called ……..

a) Encoder b) Decoder c) Multiplexer d)None of these

4)For the gate in the given figure the output will be ………..
 a) 0 b) 1 c) Ad) Ā

4) The basic storage element in a digital system is ………….

a) Flipflop b) counter c) multiplexer d)encoder

5) Which device has one input and many outputs?

a) Multiplexer b) Demultiplexer c) Counter d)Flip flop

6) The hexadecimal number (3E8)16 is equal to decimal number ………

a) 1000 b) 982 c)768 d)323

7) A three state switch has three outputs. These are …….. , …….. , ……….
a) low, low and high b) low, high, high c)low. floating, low d) low, high, floating

8) 1’s complement of 11100110 is ……………….

a) 00011001 b)10000001 c)00011010 d)00000000

9) The hexadecimal number (3E8)16 is equal to decimal number ………

a) 1000 b)982 c) 768 d)323

10) A counter type A/D converter contains a 4 bit binary ladder and a counter driven by a 2
MHz clock. Then conversion time is ………..
a) 8 μ sec b)10 μ sec c)2 μ sec d) 5 μ sec

Answer
1) a 2) a 3) b 4) d 5) a 6) a 7) d 8) a 9) a 10) a

THEORY BEHIND

MODULE I

INTEL 8086 MICROPROCESSOR

Microprocessor Evolution and Types- Architecture of 8086- Pin configuration-Instruction

Set- Addressing Modes – Interrupts-Simple Programs.

EVOLUTION OF MICROPROCESSOR – TYPES OF MICROPROCESSORS

The microprocessor is nothing but the CPU and it is an essential component of the computer.
It is a silicon chip that comprises millions of transistors and other electronic components that
process millions of instructions per second. A Microprocessor is a versatile chip that is
combined with memory and special-purpose chips and pre-programmed by software. It
accepts digital data as i/p and processes it according to the instructions stored in the memory.
The microprocessor has many functions like functions of data storage; interact with various
other devices and other time-related functions. But, the main function is to send and receive
the data to make the function of the computer well. This article discusses the types and
evolution of microprocessors.

Microprocessor

Evolution of Microprocessor

The microprocessor has become a more essential part of many gadgets. The evolution of
microprocessors was divided into five generations such as first, second, third, fourth and fifth
generation and the characteristics of these generations are discussed below.

First Generation Microprocessors

The first generation microprocessors were introduced in the year 1971-1972. The instructions
of these microprocessors were processed serially; they fetched the instruction, decoded and
then executed it. When an instruction of the microprocessor was finished, then the
microprocessor updates the instruction pointer & fetched the following instruction,
performing this consecutive operation for each instruction in turn.

Second Generation Microprocessors

In the year 1970, a small number of transistors were available on the integrated circuit in the
second-generation microprocessors. Examples of the second-generation microprocessors are
16-bit arithmetic 7 pipelined instruction processing, MC68000 Motorola microprocessor.
These processors are introduced in the year 1979, and Intel 8080 processor is another
example of the microprocessor. The second generation of the microprocessor is defined by
overlapped fetch, decode and execute the steps. When the first generation is processed in the
execution unit, then the second instruction is decoded and the third instruction is fetched.
The difference between the first generation microprocessor and second-generation
microprocessors was mainly the use of new semiconductor technologies to manufacture the
chips. The result of this technology resulted in a fivefold increase in instruction, speed,
execution and higher chip densities.

Third Generation Microprocessors

The third generation microprocessors were introduced in the year 1978, as denoted by Intel’s
8086 and the ZilogZ8000. These were 16-bit processors with a performance like mini
computers. These types of microprocessors were different from the previous generations of
microprocessors in that all main workstation industrialists began evolving their own ISC
based microprocessor architectures.

Fourth Generation Microprocessors

As many industries converted from commercial microprocessors to in house designs, the

fourth generation microprocessors are entered with outstanding design with a million
transistors. Leading-edge microprocessors like Motorola’s 88100 and Intel’s 80960CA could
issue & retire more than one instruction per clock cycle.

Fifth Generation Microprocessors

Fifth-generation microprocessors employed decoupled superscalar processing, and their

design soon exceeded 10 million transistors. In the fifth generation, PCs are a low-margin,
high volume business conquered by a single microprocessor.

Types of Microprocessor

Microprocessors are classified into five types, namely: CISC-Complex Instruction Set
Microprocessors, RISC-Reduced Instruction Set Microprocessor, ASIC- Application Specific
Integrated Circuit, Superscalar Processors, DSP’s-Digital Signal Microprocessors.
 Types of Microprocessors

Complex Instruction Set Microprocessors

The short term of Complex Instruction Set Microprocessors is CISM and they classify a
microprocessor in which orders can be performed together along with other low-level
activities. These types of processors perform different tasks like downloading, uploading,
recalling data into the memory card and recalling data from the memory card. Apart from
these tasks, it also does complex mathematical calculations in a single command.

Reduced Instruction Set Microprocessor

The short term of Reduced Instruction Set Microprocessor is RISC. These types of processors
are made according to the function in which the microprocessor can carry out small things in
specific commands. In this way, these processors complete more commands at a faster rate.

Superscalar Microprocessors

Superscalar processor facsimiles the hardware on the processor to perform various tasks at a
time. These processors can be used for ALUs or multipliers. They have different operational
units and these processors can carry out more than one command by continuously
transmitting several instructions to the extra operational units inside the processor.
The Application Specific Integrated Circuit

The short term of Application Specific Integrated Circuit processor is an ASIC. These
processors are used for particular purposes that include automotive emissions control or
personal digital assistants computer. This type of processor is made with the proper
specification, but apart from these, it can also be made with off the shelf gears.

Digital Signal Multiprocessors

Digital signal processors are also called as DSP’s, these processors are used to encode and
decode the videos or to convert the D/A (digital to analog) &A/D (analog to digital). They
need a microprocessor that is excellent in mathematical calculations. The chips of this
processor are employed in RADAR, home theatres, SONAR, audio gears, TV set-top boxes,
and Mobile phones
There are many companies like Intel, Motorola, DEC (Digital Equipment Corporation ), TI
(Texas Instruments) associated with many microprocessors such as 8085 microprocessors,
ASIC, CISM, RISC, DSPs and 8086 microprocessors like Intel

ADVANTAGES AND DISADVANTAGES OF MICROPROCESSORS

The advantages of microprocessors are

 The processing speed is high

 Intelligence has been brought to systems
 Flexible.
 Compact size.
 Easy maintenance
 Complex mathematics

Some of the disadvantages of the microprocessor are it might get overheated and the
limitation of the microprocessor imposes on the size of data.

The applications of the microprocessors mainly involve in controllers in home

appliances, wireless communication equipment, office publication and automation, consumer
electronic goods, calculators, accounting system, video games, industrial controllers and data
acquisition systems
8086 MICROPROCESSOR ARCHITECTURE AND OPERATION

It is a 16 bit microprocessor. 8086 has a 20 bit address bus can access up to 220 memory
locations ( 1 MB) . It can support up to 64K I/O ports. It provides 14, 16-bit registers. It has
multiplexed address and data bus AD0- AD15 and A16 – A19. It requires single phase clock
with 33% duty cycle to provide internal timing. 8086 is designed to operate in two modes,
Minimum and Maximum. It can prefetches up to 6 instruction bytes from memory and
queues them in order to speed up instruction execution. It requires +5V power supply. A 40
pin dual in line package.

Minimum and Maximum Modes

The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This is a
single microprocessor configuration. The maximum mode is selected by applying logic 0 to
the MN / MX# input pin. This is a multi-microprocessors configuration.
8086 microprocessor architecture
Internal Architecture of 8086 has two blocks BIU and EU. The BIU performs all bus
operations such as instruction fetching, reading and writing operands for memory and
calculating the addresses of the memory operands. The instruction bytes are transferred to the
instruction queue. EU executes instructions from the instruction system byte queue. Both
units operate asynchronously to give the 8086 an overlapping instruction fetch and execution
mechanism which is called as Pipelining. This results in efficient use of the system bus and
system performance. BIU contains Instruction queue, Segment registers, Instruction pointer,
Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index
register, Flag register. Bus Interface Unit: It provides a full 16 bit bidirectional data bus and
20 bit address bus. The bus interface unit is responsible for performing all external bus
operations.

Specifically it has the following functions: Instruction fetch, Instruction queuing, Operand
fetch and storage, Address relocation and Bus control. The BIU uses a mechanism known as
an instruction stream queue to implement a pipeline architecture.
This queue permits prefetches of up to six bytes of instruction code. Whenever the queue of
the BIU is not full, it has room for at least two more bytes and at the same time the EU is not
requesting it to read or write operands from memory, the BIU is free to look ahead in the
program by prefetching the next sequential instruction. These prefetching instructions are
held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a
single memory cycle. After a byte is loaded at the input end of the queue, it automatically
shifts up through the FIFO to the empty location nearest the output. The EU accesses the
queue from the output end. It reads one instruction byte after the other from the output of the
queue. If the queue is full and the EU is not requesting access to operand in memory. These
intervals of no bus activity, which may occur between bus cycles, are known as Idle state. If
the BIU is already in the process of fetching an instruction when the EU request it to read or
write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle
before initiating the operand read / write cycle. The BIU also contains a dedicated adder
which is used to generate the 20 bit physical address that is output on the address bus. This
address is formed by adding an appended 16 bit segment address and a 16 bit offset address.
For example, the physical address of the next instruction to be fetched is formed by
combining the current contents of the code segment CS register and the current contents of
the instruction pointer IP register. The BIU is also responsible for generating bus control
signals such as those for memory read or write and I/O read or write.

Execution Unit

The Execution unit is responsible for decoding and executing all instructions. The EU
extracts instructions from the top of the queue in the BIU, decodes them, generates operands
if necessary, passes them to the BIU and requests it to perform the read or write bus cycles to
memory or I/O and perform the operation specified by the instruction on the operands.
During the execution of the instruction, the EU tests the status and control flags and updates
them based on the results of executing the instruction. If the queue is empty, the EU waits for
the next instruction byte to be fetched and shifted to top of the queue. When the EU executes
a branch or jump instruction, it transfers control to a location corresponding to another set of
sequential instructions. Whenever this happens, the BIU automatically resets the queue and
then begins to fetch instructions from this new location to refill the queue.
Internal Registers of 8086

The 8086 has four groups of the user accessible internal registers. They are the instruction
pointer, four data registers, four pointer and index register, four segment registers.
The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the status
register, with 9 of bits implemented for status and control flags. Most of the registers contain
data/instruction offsets within 64 KB memory segment. There are four different 64 KB
segments for instructions, stack, data and extra data. To specify where in 1 MB of processor
memory these 4 segments are located the processor uses four segment registers:

Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor
instructions. The processor uses CS segment for all accesses to instructions referenced by
instruction pointer (IP) register. CS register cannot be changed directly. The CS register is
automatically updated during far jump, far call and far return instructions.

Stack segment (SS) is a 16-bit register containing address of 64KB segment with program
stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and
base pointer (BP) registers is located in the stack segment. SS register can be changed
directly using POP instruction.

Data segment (DS) is a 16-bit register containing address of 64KB segment with program
data. By default, the processor assumes that all data referenced by general registers (AX, BX,
CX, DX) and index register (SI, DI) is located in the data segment. DS register can be
changed directly using POP and LDS instructions.

Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with
program data. By default, the processor assumes that the DI register references the ES
segment in string manipulation instructions. ES register can be changed directly using POP
and LES instructions. It is possible to change default segments used by general and index
registers by prefixing instructions with a CS, SS, DS or ES prefix.

All general registers of the 8086 microprocessor can be used for arithmetic and logic
operations. The general registers are:

Accumulator register consists of two 8-bit registers AL and AH, which can be combined
together and used as a 16-bit register AX. AL in this case contains the low-order byte of the
word, and AH contains the high-order byte. Accumulator can be used for I/O operations and
string manipulation.

Base register consists of two 8-bit registers BL and BH, which can be combined together and
used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH
contains the high-order byte. BX register usually contains a data pointer used for based, based
indexed or register indirect addressing.

Count register consists of two 8-bit registers CL and CH, which can be combined together
and used as a 16-bit register CX. When combined, CL register contains the low-order byte of
the word, and CH contains the high-order byte. Count register can be used in Loop,
shift/rotate instructions and as a counter in string manipulation,.

Data register consists of two 8-bit registers DL and DH, which can be combined together and
used as a 16-bit register DX. When combined, DL register contains the low-order byte of the
word, and DH contains the high- order byte. Data register can be used as a port number in I/O
operations. In integer 32-bit multiply and divide instruction the DX register contains high-
order word of the initial or resulting number. The following registers are both general and
index registers:

Stack Pointer (SP) is a 16-bit register pointing to program stack. Base Pointer (BP) is a 16-
bit register pointing to data in stack segment. BP register is usually used for based, based
indexed or register indirect addressing.

Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register
indirect addressing, as well as a source data address in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register
indirect addressing, as well as a destination data address in string manipulation instructions.
Other registers:

Instruction Pointer (IP) is a 16-bit register.

Flags is a 16-bit register containing 9 one bit flags.

Overflow Flag (OF) - set if the result is too large positive number, or is too small negative
number to fit into destination operand.

Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index
registers. If cleared then the index registers will be auto-incremented.

Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.

Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction.
Sign Flag (SF) - set if the most significant bit of the result is set.

Zero Flag (ZF) - set if the result is zero

Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL
register.

Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is
even.

Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during
last result calculation.

ADDRESSING MODES
The way of specifying data to be operated by an instruction is known as addressing modes.

Implied - the data value/data address is implicitly associated with the instruction.

Register- references the data in a register or in a register pair.

Immediate - the data is provided in the instruction.

Direct - the instruction operand specifies the memory address where data is located.

Register indirect - instruction specifies a register containing an address, where data is

located. This addressing mode works with SI, DI, BX and BP registers.

Based :- 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or
BP), the resulting value is a pointer to location where data resides.

Indexed :- 8-bit or 16-bit instruction operand is added to the contents of an index register (SI
or DI), the resulting value is a pointer to location where data resides.
Based Indexed :- the contents of a base register (BX or BP) is added to the contents of an
index register (SI or DI), the resulting value is a pointer to location where data resides.

Based Indexed with displacement :- 8-bit or 16-bit instruction operand is added to the
contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a
pointer to location where data resides.

INTERRUPTS IN 8086 MICROPROCESSOR

The processor has the following interrupts:

INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI
instructions or using more complicated method of updating the FLAGS register with the help
of the POPF instruction.

When an interrupt occurs, the processor stores FLAGS register into stack, disables further
interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt
processing routine address of which is stored in location 4 * <interrupt type>. Interrupt
processing routine should return with the IRET instruction.

NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR
interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is
stored in location 0008h. This interrupt has higher priority then the maskable interrupt.

Software interrupts can be caused by: INT instruction - breakpoint interrupt. This is a type 3
interrupt. INT <interrupt number> instruction - any one interrupt from available 256
interrupts. INTO instruction - interrupt on overflow Single-step interrupt - generated if the TF
flag is set. This is a type 1 interrupt. When the CPU processes this interrupt it clears TF flag
before calling the interrupt processing routine.

Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape opcode
(type 7). Software interrupt processing is the same as for the hardware interrupts.

The figure below shows the 256 interrupt vectors arranged in the interrupt vector table in the
memory.
Minimum Mode Interface When the Minimum mode operation is selected, the 8086
provides all control signals needed to implement the memory and I/O interface. The
minimum mode signal can be divided into the following basic groups : address/data bus,
status, control, interrupt and DMA.
Address/Data Bus : these lines serve two functions. As an address bus is 20 bits long and
consists of signal lines A0 through A19. A19 represents the MSB and A0 LSB. A 20bit
address gives the 8086 a 1Mbyte memory address space. More over it has an independent I/O
address space which is 64K bytes in length.
The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0 through
A15 respectively. By multiplexed we mean that the bus work as an address bus
during first machine cycle and as a data bus during next machine cycles. D15 is the MSB and
D0 LSB. When acting as a data bus, they carry read/write data for memory, input/output data
for I/O devices, and interrupt type codes from an interrupt controller.

Status signal : The four most significant address lines A19 through A16 are also multiplexed
but in this case with status signals S6 through S3. These status bits are output on the bus at
the same time that data are transferred over the other bus lines. Bit S4 and S3 together from a
2 bit binary code that identifies which of the 8086 internal segment registers are used to
generate the physical address that was output on the address bus during the current bus cycle.
Code S4S3 = 00 identifies a register known as extra segment register as the source of the
segment address.
 Memory segment status code

Status line S5 reflects the status of another internal characteristic of the 8086. It is the logic
level of the internal enable flag. The last status bit S6 is always at the logic 0 level.

Control Signals : The control signals are provided to support the 8086 memory I/O
interfaces. They control functions such as when the bus is to carry a valid address in which
direction data are to be transferred over the bus, when valid write data are on the bus and
when to put read data on the system bus.

ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on the
bus. This address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE.
Another control signal that is produced during the bus cycle is BHE bank high enable. Logic
0 on this used as a memory enable signal for the most significant byte half of the data bus D8
through D1.

These lines also serves a second function, which is as the S7 status line. Using the M/IO and
DT/R lines, the 8086 signals which type of bus cycle is in progress and in which direction
data are to be transferred over the bus. The logic level of M/IO tells external circuitry
whether a memory or I/O transfer is taking place over the bus. Logic 1 at this output signals a
memory operation and logic 0 an I/O operation. The direction of data transfer over the bus is
74ignallin by the logic level output at DT/R. When this line is logic 1 during the data transfer
part of a bus cycle, the bus is in the transmit mode.
Therefore, data are either written into memory or output to an I/O device. On the other hand,
logic 0 at DT/R signals that the bus is in the receive mode. This corresponds to reading data
from memory or input of data from an input port. The signal read RD and write WR indicates
that a read bus cycle or a write bus cycle is in progress. The 8086 switches WR to logic 0 to
signal external device that valid write or output data are on the bus. On the other hand, RD
indicates that the 8086 is performing a read of data of the bus.

During read operations, one other control signal is also supplied. This is DEN (data enable)
and it signals external devices when they should put data on the bus. There is one other
control signal that is involved with the memory and I/O interface. This is the READY signal.
READY signal is used to insert wait states into the bus cycle such that it is extended by a
number of clock periods. This signal is provided by an external clock generator device and
can be supplied by the memory or I/O sub- system to signal the 8086 when they are ready to
permit the data transfer to be completed.

Maximum Mode Interface When the 8086 is set for the maximum-mode configuration, it
provides signals for implementing a multiprocessor / coprocessor system environment. By
multiprocessor environment we mean that one microprocessor exists in the system and that
each processor is executing its own program. Usually in this type of system environment,
there are some system resources that are common to all processors. They are called as global
resources. There are also other resources that are assigned to specific processors. These are
known as local or private resources. Coprocessor also means that there is a second processor
in the system. In this two processor does not access the bus at the same time. One passes the
control of the system bus to the other and then may suspend its operation. In the maximum-
mode 8086 system, facilities are provided for implementing allocation of global resources
and passing bus control to other microprocessor or coprocessor.
ASSEMBLY LANGUAGE PROGRAMMING OF 8086
Machine Language
• Set of fundamental instructions the machine can execute.
• Expressed as a pattern of 1’s and 0’s

Assembly Language
• Alphanumeric equivalent of machine language
• Mnemonics more human-oriented than 1’s and 0’s

Assembler:
• Computer program that transliterates (one-to-one mapping) assembly to machine
language
• Computer’s native language is machine/assembly language

CPU Registers:
Fourteen 16-bit registers „ Data Registers
• AX (Accumulator Register): AH and AL
• BX (Base Register): BH and BL
• CX (Count Register): CH and CL
• DX (Data Register): DH and DL „ Pointer and Index Registers
• SI (Source Index)
• DI (Destination Index)
• SP (Stack Pointer)
• BP (Base Pointer)
• IP (Instruction Pointer)
Segment Registers
• CS (Code Segment)
• DS (Data Segment)
• SS (Stack Segment)
• ES (Extra Segment) „
FLAGS Register:
• Zero flag • Sign flag • Parity flag • Carry flag • Overflow flag
Fetch-Execute Process „ Program Counter (PC) or Instruction Pointer (IP)
• Holds address of next instruction to fetch „ Instruction Register (IR)
• Stores the instruction fetched from memory. „
Fetch-Execute process
• Read an instruction from memory addressed by PC
• Increment program counter
• Execute fetched instruction in IR
• Repeat process

Assembly Language Syntax

Program consists of statement per line. „ Each statement is an
instruction or assembler directive „ Statement syntax
• Name operation operand(s) comment „ Name field
• Used for instruction labels, procedure names, and variable names.
• Assembler translates names into memory addresses
• Names are 1-31 characters including letters, numbers and special characters ? . @ _ $ %
• Names may not begin with a digit.
INSTRUCTION SET OF 8086 MICROPROCESSOR

The 8086 microprocessor supports 8 types of instructions −

 Data Transfer Instructions

 Arithmetic Instructions

 Bit Manipulation Instructions

 String Instructions

 Program Execution Transfer Instructions (Branch & Loop Instructions)

 Processor Control Instructions

 Iteration Control Instructions

 Interrupt Instructions

Let us now discuss these instruction sets in detail.

Data Transfer Instructions

These instructions are used to transfer the data from the source operand to the destination
operand. Following are the list of instructions under this group −

Instruction to transfer a word

 MOV − Used to copy the byte or word from the provided source to the provided
destination.

 PPUSH − Used to put a word at the top of the stack.

 POP − Used to get a word from the top of the stack to the provided location.

 PUSHA − Used to put all the registers into the stack.

 POPA − Used to get words from the stack to all registers.

 XCHG − Used to exchange the data from two locations.

 XLAT − Used to translate a byte in AL using a table in the memory.

Instructions for input and output port transfer

 IN − Used to read a byte or word from the provided port to the accumulator.
  OUT − Used to send out a byte or word from the accumulator to the provided port.

Instructions to transfer the address

 LEA − Used to load the address of operand into the provided register.

 LDS − Used to load DS register and other provided register from the memory

 LES − Used to load ES register and other provided register from the memory.

Instructions to transfer flag registers

 LAHF − Used to load AH with the low byte of the flag register.

 SAHF − Used to store AH register to low byte of the flag register.

 PUSHF − Used to copy the flag register at the top of the stack.

 POPF − Used to copy a word at the top of the stack to the flag register.

Arithmetic Instructions

These instructions are used to perform arithmetic operations like addition, subtraction,
multiplication, division, etc.

Following is the list of instructions under this group −

Instructions to perform addition

 ADD − Used to add the provided byte to byte/word to word.

 ADC − Used to add with carry.

 INC − Used to increment the provided byte/word by 1.

 AAA − Used to adjust ASCII after addition.

 DAA − Used to adjust the decimal after the addition/subtraction operation.

Instructions to perform subtraction

 SUB − Used to subtract the byte from byte/word from word.

 SBB − Used to perform subtraction with borrow.

  DEC − Used to decrement the provided byte/word by 1.

 NPG − Used to negate each bit of the provided byte/word and add 1/2’s complement.

 CMP − Used to compare 2 provided byte/word.

 AAS − Used to adjust ASCII codes after subtraction.

 DAS − Used to adjust decimal after subtraction.

Instruction to perform multiplication

 MUL − Used to multiply unsigned byte by byte/word by word.

 IMUL − Used to multiply signed byte by byte/word by word.

 AAM − Used to adjust ASCII codes after multiplication.

Instructions to perform division

 DIV − Used to divide the unsigned word by byte or unsigned double word by word.

 IDIV − Used to divide the signed word by byte or signed double word by word.

 AAD − Used to adjust ASCII codes after division.

 CBW − Used to fill the upper byte of the word with the copies of sign bit of the
lower byte.

 CWD − Used to fill the upper word of the double word with the sign bit of the lower
word.

Bit Manipulation Instructions

These instructions are used to perform operations where data bits are involved, i.e.
operations like logical, shift, etc.

Following is the list of instructions under this group −

Instructions to perform logical operation

 NOT − Used to invert each bit of a byte or word.

  AND − Used for adding each bit in a byte/word with the corresponding bit in another
byte/word.

 OR − Used to multiply each bit in a byte/word with the corresponding bit in another
byte/word.

 XOR − Used to perform Exclusive-OR operation over each bit in a byte/word with
the corresponding bit in another byte/word.

 TEST − Used to add operands to update flags, without affecting operands.

Instructions to perform shift operations

 SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.

 SHR − Used to shift bits of a byte/word towards the right and put zero(S) in MSBs.

 SAR − Used to shift bits of a byte/word towards the right and copy the old MSB into
the new MSB.

Instructions to perform rotate operations

 ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to
Carry Flag [CF].

 ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to
Carry Flag [CF].

 RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF and CF to
MSB.

 RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to
LSB.

String Instructions

String is a group of bytes/words and their memory is always allocated in a sequential order.

Following is the list of instructions under this group −

 REP − Used to repeat the given instruction till CX ≠ 0.

 REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.

  REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF
= 1.

 MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to

another.

 COMS/COMPSB/COMPSW − Used to compare two string bytes/words.

 INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the

provided memory location.

 OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided

memory location to the I/O port.

 SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in
AL or string word with a word in AX.

 LODS/LODSB/LODSW − Used to store the string byte into AL or string word into
AX.

Program Execution Transfer Instructions (Branch and Loop Instructions)

These instructions are used to transfer/branch the instructions during an execution. It

includes the following instructions −

Instructions to transfer the instruction during an execution without any condition −

 CALL − Used to call a procedure and save their return address to the stack.

 RET − Used to return from the procedure to the main program.

 JMP − Used to jump to the provided address to proceed to the next instruction.

Instructions to transfer the instruction during an execution with some conditions −

 JA/JNBE − Used to jump if above/not below/equal instruction satisfies.

 JAE/JNB − Used to jump if above/not below instruction satisfies.

 JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.

 JC − Used to jump if carry flag CF = 1

 JE/JZ − Used to jump if equal/zero flag ZF = 1

  JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.

 JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.

 JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.

 JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.

 JNC − Used to jump if no carry flag (CF = 0)

 JNE/JNZ − Used to jump if not equal/zero flag ZF = 0

 JNO − Used to jump if no overflow flag OF = 0

 JNP/JPO − Used to jump if not parity/parity odd PF = 0

 JNS − Used to jump if not sign SF = 0

 JO − Used to jump if overflow flag OF = 1

 JP/JPE − Used to jump if parity/parity even PF = 1

 JS − Used to jump if sign flag SF = 1

Processor Control Instructions

These instructions are used to control the processor action by setting/resetting the flag
values.

Following are the instructions under this group −

 STC − Used to set carry flag CF to 1

 CLC − Used to clear/reset carry flag CF to 0

 CMC − Used to put complement at the state of carry flag CF.

 STD − Used to set the direction flag DF to 1

 CLD − Used to clear/reset the direction flag DF to 0

 STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.

 CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input.
Iteration Control Instructions

These instructions are used to execute the given instructions for number of times. Following
is the list of instructions under this group −

 LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX =
0

 LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX

=0

 LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 &

CX = 0

 JCXZ − Used to jump to the provided address if CX = 0

Interrupt Instructions

These instructions are used to call the interrupt during program execution.

 INT − Used to interrupt the program during execution and calling service specified.

 INTO − Used to interrupt the program during execution if OF = 1

 IRET − Used to return from interrupt service to the main program

MODULE II

INTEL 8051 MICROCONTROLLER

8051 Architecture-pin configuration – flags and PSW-CPU registers-Internal RAM & ROM-

Special Function Registers- I/O Ports & Circuits.

INTEL 8051 Microcontroller
INTRODUCTION TO MICROCONTROLLER

A microcontroller is a small and low-cost microcomputer, which is designed to perform the

Specific tasks of embedded systems like displaying microwave’s information, receiving
remotesignals, etc. The general microcontroller consists of the processor, the memory (RAM,
ROM, and EPROM), Serial ports, peripherals (timers, counters), etc.

The following table highlights the differences between a microprocessor and a

microcontroller

TYPES OF MICROCONTROLLERS

Microcontrollers are divided into various categories based on memory, architecture, bits and
Instruction sets.

Following is the list of their types –

A) Bit
Based on bit configuration, the microcontroller is further divided into three categories.

8-bit microcontroller − this type of microcontroller is used to execute arithmetic and

logical operations like addition, subtraction, multiplication division, etc. For example,
Intel 8031 and 8051 are 8 bits microcontroller.
16-bit microcontroller − this type of microcontroller is used to perform arithmetic and
logical operations where higher accuracy and performance is required. For example,
Intel 8096 is a 16-bit microcontroller.
32-bit microcontroller − this type of microcontroller is generally used in automatically
controlled appliances like automatic operational machines, medical appliances, etc.

b) Memory Based on the memory configuration, the microcontroller is further divided into
two categories.
External memory microcontroller − This type of microcontroller is designed in such a
way that they do not have a program memory on the chip. Hence, it is named as external
memory microcontroller. For example: Intel 8031 microcontroller.
Embedded memory microcontroller − this type of microcontroller is designed in such a
way that the microcontroller has all programs and data memory, counters and timers,
interrupts, I/O ports are embedded on the chip. For example: Intel 8051 microcontroller.

c) Instruction Set
Based on the instruction set configuration, the microcontroller is further divided into two
Categories.
CISC − CISC stands for complex instruction set computer. It allows the user to insert
asingle instruction as an alternative to many simple instructions.
RISC − RISC stands for Reduced Instruction Set Computers. It reduces the operational
time by shortening the clock cycle per instruction.

APPLICATIONS OF MICROCONTROLLERS

Microcontrollers are widely used in various different devices such as −

 Light sensing and controlling devices like LED.
 Temperature sensing and controlling devices like microwave oven, chimneys.
 Fire detection and safety devices like Fire alarm.
 Measuring devices like Volt Meter.

INTRODUCTION TO 8051 MICROCONTROLLER

8051 microcontroller is designed by Intel in 1981. It is an 8-bit microcontroller. It is built

with40 pins DIP (dual inline package), 4kb of ROM storage and 128 bytes of RAM storage, 2
16-bittimers. It consists of are four parallel 8-bit ports, which are programmable as well as
addressable as per the requirement. An on-chip crystal oscillator is integrated in the
microcontroller having crystal frequency of 12 MHz.

Features of 8051 MC
 4K bytes internal ROM
 128 bytes internal RAM
 Four 8-bit I/O ports (P0 - P3).
 Two 16-bit timers/counters
 One serial interface
 only 1 On chip oscillator (external crystal)
 6 interrupt sources (2 external , 3 internal, Reset)
 64K external code (program) memory(only read)PSEN
 64K external data memory(can be read and write) by RD,WR
 Code memory is selectable by EA (internal or external)

ARCHITECTURE OF 8051 MICROCONTROLLER.

In the following diagram, the system bus connects all the support devices to the CPU. The
system bus consists of an 8-bit data bus, a 16-bit address bus and bus control signals. All
otherdevices like program memory, ports, data memory, serial interface, interrupt control,
timers, andthe CPU are all interfaced together through the system bus.
 The pin diagram of 8051 microcontroller looks as follows –

 Pins 1 to 8 − these pins are known as Port 1. This port doesn’t serve any other [Link]
is internally pulled up, bi-directional I/O port.
 Pin 9 − It is a RESET pin, which is used to reset the microcontroller to its initial values.
 Pins 10 to 17 − these pins are known as Port 3. This port serves some functions like
interrupts, timer input, control signals, serial communication signals RxD and TxD, etc.

 Pins 18 & 19 − these pins are used for interfacing an external crystal to get the system
clock.
 Pin 20 − this pin provides the power supply to the circuit.
 Pins 21 to 28 − these pins are known as Port 2. It serves as I/O port. Higher order
address bus signals are also multiplexed using this port.
 Pin 29 − this is PSEN pin which stands for Program Store Enable. It is used to read a
signal from the external program memory.
 Pin 30 − this is EA pin which stands for External Access input. It is used to
enable/disable the external memory interfacing.
 Pin 31 − this is ALE pin which stands for Address Latch Enable. It is used to
demultiplex the address-data signal of port.
 Pins 32 to 39 − these pins are known as Port 0. It serves as I/O port. Lower order
address and data bus signals are multiplexed using this port.
 Pin 40 − this pin is used to provide power supply to the circuit.

8051 microcontrollers have 4 I/O ports each of 8-bit, which can be configured as input or
output. Hence, total 32 input/output pins allow the microcontroller to be connected with the
peripheral devices.
 Pin configuration, i.e. the pin can be configured as 1 for input and 0 for output as per the
logic state.
Input/Output (I/O) pin − All the circuits within the microcontroller must be
connected to one of its pins except P0 port because it does not have pull-up
resistors built-in.
Input pin − Logic 1 is applied to a bit of the D register. The output of transistor is
turned off and the other pin remains connected to the power supply voltage over
a pull-up resistor of high resistance.

 Port 0 − The P0 (zero) port is characterized by two functions −

When the external memory is used then the lower address byte (addresses A0A7)
is applied on it, else all bits of this port are configured as input/output.
When P0 port is configured as an output then other ports consisting of pins with
built-in pull-up resistor connected by its end to 5V power supply, the pins of this
port have this resistor left out.

Input Configuration
If any pin of this port is configured as an input, then it acts as if it “floats”, i.e. the input has
unlimited input resistance and in-determined potential.

Output Configuration
When the pin is configured as an output, then it acts as an “open drain”. By applying logic 0
toa port bit, the appropriate pin will be connected to ground (0V), and applying logic 1, the
external output will keep on “floating”.In order to apply logic 1 (5V) on this output pin, it is
necessary to build an external pullup resistor.

Port 1
P1 is a true I/O port as it doesn’t have any alternative functions as in P0, but this port can be
configured as general I/O only. It has a built-in pull-up resistor and is completely compatible
with TTL circuits.

Port 2
P2 is similar to P0 when the external memory is used. Pins of this port occupy addresses
intended for the external memory chip. This port can be used for higher address byte with
addresses A8-A15. When no memory is added then this port can be used as a general
input/output port similar to Port 1.

Port 3
In this port, functions are similar to other ports except that the logic 1 must be applied to
appropriate bit of the P3 register.

Pins Current Limitations

 When pins are configured as an output (i.e. logic 0), then the single port pins can receive
a current of 10mA.
 When these pins are configured as inputs (i.e. logic 1), then built-in pull-up resistors
provide very weak current, but can activate up to 4 TTL inputs of LS series.
 If all 8 bits of a port are active, then the total current must be limited to 15mA (port P0:
26mA).
 If all ports (32 bits) are active, then the total maximum current must be limited to 71mA.

INTERRUPT OF 8051 MICROCONTROLLER

Interrupts are the events that temporarily suspend the main program, pass the control to the
external sources and execute their task. It then passes the control to the main program where
it had left off.

8051 has 5 interrupt signals, i.e. INT0, TFO, INT1, TF1, RI/TI. Each interrupt can be enabled
or disabled by setting bits of the IE register and the whole interrupt system can be disabled by
clearing the EA bit of the same register.

Steps in executing an interrupt

 Upon receiving the interrupt signal the Microcontroller , finish current instruction and
saves the PC on stack
 Jumps to a fixed location in memory depending on type of interrupt
 Starts to execute the interrupt service routine until RETI (return from interrupt)
 Upon executing the RETI the microcontroller returns to the place where it was
interrupted. Get pop PC from stack
 Each interrupt has a specific place in code memory where program execution
(interrupt service routine) begins.
 External Interrupt 0: 0003h
 Timer 0 overflow: 000Bh
 External Interrupt 1: 0013h
 Timer 1 overflow: 001Bh
 Serial : 0023h
 Timer 2 overflow(8052+) 002bh

IE (Interrupt Enable) Register

This register is responsible for enabling and disabling the interrupt. EA register is set to one
for enabling interrupts and set to 0 for disabling the interrupts. Its bit sequence and their
meanings are shown in the following figure.

EA - It disables all interrupts. When EA = 0 no interrupt will be acknowledged and EA = 1

enables the interrupt individually.
ES - Enables/disables serial port interrupt.
ET1 - Enables/disables timer1 overflow interrupt.
EX1 - Enables/disables external interrupt1.
ET0 - Enables/disables timer0 overflow interrupt.
EX0 - Enables/disables external interrupt0.

IP (Interrupt Priority) Register

We can change the priority levels of the interrupts by changing the corresponding bit in the
Interrupt Priority (IP) register as shown in the following figure.
A low priority interrupt can only be interrupted by the high priority interrupt, but not
interrupted by another low priority interrupt.
If two interrupts of different priority levels are received simultaneously, the request of
higher priority level is served.
If the requests of the same priority levels are received simultaneously, then the internal
polling sequence determines which request is to be serviced.

PS - It defines the serial port interrupt priority level.

PT1 - It defines the timer interrupt of 1 priority.
PX1 - It defines the external interrupt priority level.
PT0 - It defines the timer0 interrupt priority level.
PX0 - It defines the external interrupt of 0 priority level.
TCON register specifies the type of external interrupt to the microcontroller.

8051 MEMORY ORGANIZATION

The 8051 microcontroller's memory is divided into Program Memory and Data Memory.
Program Memory (ROM) is used for permanent saving program being executed, while Data
Memory (RAM) is used for temporarily storing and keeping intermediate results and
variables.
Program Memory (ROM)
Program Memory (ROM) is used for permanent saving program (CODE) being executed.
The memory is read only. Depending on the settings made in compiler, program memory
may also use to store constant variables. The 8051 executes programs stored in program
memory only. code memory type specified is used to refer to program memory. 8051
memory organization allows external program memory to be added.

Internal Data Memory

Up to 256 bytes of internal data memory are available depending on the 8051 derivative.
Locations available to the user occupy addressing space from 0 to 7Fh, i.e. first 128 registers
and this part of RAM is divided in several blocks. The first 128 bytes of internal data memory
are both directly and indirectly addressable. The upper 128 bytes of data memory (from 0x80
to0xFF) can be addressed only indirectly. Since internal data memory is used for CALL stack
also and there is only 256 bytes splited over few different memory areas fine utilizing of this
memory is crucial for fast and compact code.
Memory block in the range of 20h to 2Fh is bit-addressable, which means that each bit being
there has its own address from 0 to 7Fh. Since there are 16 such registers, this block contains
in total of 128 bits with separate addresses ( Bit 0 of byte 20h has the bit address 0, and bit 7
of byte 2Fh has the bit address 7Fh).
Three memory typesspecifies can be used to refer to the internal data memory: data, idata,
and bdata.
External Data Memory
Access to external memory is slower than access to internal data memory. There may be up
to 64K Bytes of external data memory. Several 8051 devices provide on-chip XRAM space
that is accessed with the same instructions as the traditional external data space. This XRAM
space is typically enabled via proper setting of SFR register and overlaps the external
memory space. Setting of that register must be manually done in code, before any access to
external memory orXRAM space is made.
The mikroC PRO for 8051 has two memory typesspecifies that refers to external memory
space: xdata and pdata.

SFR Memory
The 8051 provides 128 bytes of memory for Special Function Registers (SFRs). SFRs are bit,
byte, or word-sized registers that are used to control timers, counters, serial I/O, port I/O, and
peripherals.

8051 TIMER/COUNTER

8051 Timer/Counter Two internal Timers/Counters 16-bit timer/counter Timer uses system
clockas source of input pulses Counter uses external input pulses from port 3 (T0,T1) If
associatedinterrupt is enabled, when count overflow an interrupt is generated Registers TH0,
TL0 :timer/counter register of timer 0 TH1, TL1 : timer/counter register of timer 1
TMOD: ModeSelect register,TCON: Control Register
TIMER

Set the initial value of registers

Start the timer and then the 8051 counts up.
Input from internal system clock (machine cycle)
When the registers equal to 0 and the 8051 sets a bit to denote time out

Counter

Count the number of events

Show the number of events on registers
External input from T0 input pin (P3.4) for Counter 0
External input from T1 input pin (P3.5) for Counter 1
External input from Tx input pin.
We use Tx to denote T0 or T1.
TMOD REGISTER

 Both Timer 0 &Timer 1 use the same Mode register TMOD

 It is an-8-bit register .The lower 4-bits are meant for
 Timer 0 &the upper 4-bits are meant for Timer 1
 It is not bit addressable.
 It is used similar to any other register of 8051. For ex:
MOV TMOD, #21H
 Every timer has a mean of starting and stopping.
GATE=0
Internal control
The start and stop of the timer are controlled by way of software
Set/clear the TR for start/stop timer
SETB TR0
CLR TR0
GATE=1
External control
The hardware way of starting and stopping the timer by software and
an external source.
Timer/counter is enabled only while the INT pin is high and the TR
control pin is set (TR).
 C/T: Timer or counter selected cleared for timer operation (input from internal system
clock). Set for counter operation (input from Tx input pin).
 M1, M0:Used for mode selection, because the Timers of 8051 can be set in 4-different
modes.
M1 M0 Mode Operation
0 0 0 13-bit timer mode 8-bit THx + 5-bit TLx (x= 0 or 1)
0 1 1 16-bit timer mode 8-bit THx + 8-bit TLx
1 0 2 8-bit auto reload 8-bit auto reload timer/counter; THx holds
 a value which is to be reloaded into TLx each time it
overflows.
1 1 3 Split timer mode

TCON REGISTER

 Timer control register TMOD is a 8-bit register which is bit addressable and in which
Upper nibble is for timer/counter,
 lower nibble is for interrupts
 TR (Timer run control bit)
TR0 for Timer/counter 0; TR1 for Timer/counter 1.
TR is set by programmer to turn timer/counter on/off.
TR=0 : off (stop)
TR=1 : on (start)
 TF (timer flag, control flag)
TF0 for timer/counter 0; TF1 for timer/counter 1.
TF is like a carry. Originally, TF=0. When TH-TL roll over to 0000 from FFFFH, the TF is
set to 1.
TF=0 : not reach
TF=1: reach
If we enable interrupt, TF=1 will trigger ISR.

Operation Modes
Mode 0
13-bit counter, an interrupt is generated when counter overflows.
It takes 8192 input pulses to generate the next interrupt.
Mode 1
16-bit counter, similar to mode 0, but take 65536 input pulses
Mode 2
8-bit reload
TL1 operates as timer/counter
TH1store a number and reload to TL1 when overflows
Mode 3
Timer 1 is inactive, hold count value.
TL0 and TH0 operate as two separate 8-bit timer/counter
TL0 control by timer 0 control bits
TH0 operate as timer driven by system clock, prescaled by 12 and cause timer 1 interrupt
Overflows

Working of Timer Mode 1

let us consider timer 0 as an example.

 16-bit timer (TH0 and TL0)
 TH0-TL0 is incremented continuously when TR0 is set to 1.
 8051 stops to increment TH0-TL0 when TR0 is cleared.
 The timer works with the internal system clock. In other words, the timer counts up
each machine cycle.
 When the timer (TH0-TL0) reaches its maximum of FFFFH, it rolls over to 0000, and
TF0 is raised.
 Programmer should check TF0 and stop the timer 0.
 1. Choose mode 1 timer 0

MOV TMOD,#01H

 2. Set the original value to TH0 and TL0.

MOV TH0,#FFH

MOV TL0,#FCH

 3. You better to clear the TF: TF0=0.

CLR TF0
  4. Start the timer.

SETB TR0

Steps of Mode 1

The 8051 starts to count up by incrementing the TH0-TL0

TH0-TL0= FFFCH,FFFDH,FFFEH,FFFFH,0000H

• When TH0-TL0 rolls over from FFFFH to 0000, the 8051 set TF0=1.

TH0-TL0= FFFE H, FFFF H, 0000 H (Now TF0=1)

• Keep monitoring the timer flag (TF) to see if it is raised.

AGAIN: JNB TF0, AGAIN

• Clear TR0 to stop the process.

CLR TR0

• Clear the TF flag for the next round.

CLR TF0

8051- SERIAL COMMUNICATION

Types of Serial communications

 The 8051 has two pins for transferring and receiving data by serial communication.
 These two pins are part of the Port3(P3.0 &P3.1)
 These pins are TTL compatible and hence they require a line driver to make them
RS232 compatible
 Max232 chip is one such line driver in use.
 Serial communication is controlled by an 8-bit register called SCON register; it is a
bit addressable register.
Interfacing to PC

SCON (Serial control) register

 These two bits of SCON register determine the framing of data by specifying the
number of bits per character and start bit and stop bits. There are 4 serial modes.

SM0 SM1

0 0 Serial Mode 0

0 1 Serial Mode 1, 8 bit data,1 stop bit, 1 Start bit

1 0 Serial Mode 2

1 1 Serial Mode 3

 REN (Receive Enable) also referred as [Link] it is high; it allows the 8051 to
receive data on the RxD pin. So to receive and transfer data REN must be set to
[Link] REN=0, the receiver is disabled. This is achieved as below

SETB SCON.4

& CLR SCON.4

 TI (Transmit interrupt) is the D1 bit of SCON register. When 8051 finishes the
transfer of 8-bit character, it raises the TI flag to indicate that it is ready to transfer
another byte. The TI bit is raised at the beginning of the stop bit.

 RI (Receive interrupt) is the D0 bit of the SCON register. When the 8051 receives
data serially, viaRxD, it gets rid of the start and stops bits and places the byte in the
 SBUF register. Then it raises the RI flag bit to indicate that a byte has been received
and should be picked up before it is lost. RI is raised halfway through the stop bit.

MODULE III

INTEL 8051 PROGRAMMING

Instruction Set- Data Transfer Instruction-Arithmetic and Logical Instruction- Jump Loop and

Call Instruction-Simple Programs.

8051 Microcontroller Instruction Set

INTRODUCTION

Writing a Program for any Microcontroller consists of giving commands to the

microcontroller in a particular order in which they must be executed in order to perform a
specific task. The commands to the Microcontroller are known as a Microcontroller’s
Instruction [Link] as our sentences are made of words, a Microcontroller’s (for that matter,
any computer) program is made of Instructions. Instructions written in a program tell the
Microcontroller which operation to carry [Link] Instruction Set is unique to a family of
computers. This tutorial introduces the 8051 Microcontroller Instruction Set also called as the
MCS-51 Instruction [Link] the 8051 family of Microcontrollers are 8-bit processors, the 8051
Microcontroller Instruction Set is optimized for 8-bit control applications. As a typical 8-bit
processor, the 8051 Microcontroller instructions have 8-bit Opcode. As a result, the 8051
Microcontroller instruction set can have up to 28 = 256 Instructions.

The instructions of 8051 Microcontroller can be classified into five different groups. These
groups are like below
 Data Transfer Group
 Arithmetic Group
 Logical Group
 Program Branch Group
 Bit Processing Group
This Bit-Processing group is also known as Boolean Variable Manipulation.
Like 8086, some instruction has two operands. The first operand is the Destination, and the
second operator is Source. The following table shows the 8051 Instruction Groups and
Instructions in each group. There are 49 Instruction Mnemonics in the 8051 Microcontroller
Instruction Set and these 49 Mnemonics are divided into five groups.

PROGRAM
DATA TRANSFER ARITHMETIC LOGICAL BOOLEAN
BRANCHING

MOV ADD ANL CLR LJMP

MOVC ADDC ORL SETB AJMP

MOVX SUBB XRL MOV SJMP

PUSH INC CLR JC JZ

POP DEC CPL JNC JNZ

XCH MUL RL JB CJNE

XCHD DIV RLC JNB DJNZ

DA A RR JBC NOP

RRC ANL LCALL

 SWAP ORL ACALL

CPL RET

RETI

JMP

Data Transfer Instructions

The Data Transfer Instructions are associated with transfer with data between registers or
external program memory or external data memory. The Mnemonics associated with Data
Transfer are given below. It is also possible to transfer data between the internal and external
RAM by using indirect addressing .The upper 128 bytes of data RAM are accessed only by
indirect addressing and the SFRs are accessed only by direct addressing. Data transfer
instructions are used to transfer data between an internal RAM location and SFR location
without going through the accumulator. Data can also be transferred between the internal and
external RAM by using indirect addressing.

 MOV
 MOVC
 MOVX
 PUSH
 POP
 XCH
 XCHD
The following table lists out all the possible data transfer instruction along with other details
like addressing mode, size occupied and number machine cycles it takes.
Arithmetic Instructions

Using Arithmetic Instructions, you can perform addition, subtraction, multiplication and
division. The arithmetic instructions also include increment by one, decrement by one and a
special instruction called Decimal Adjust [Link] Mnemonics associated with the
Arithmetic Instructions of the 8051 Microcontroller Instruction Set are:

 ADD
 ADDC
  SUBB
 INC
 DEC
 MUL
 DIV
 DA A

The arithmetic instructions have no knowledge about the data format i.e. signed, unsigned,
ASCII, BCD, etc. Also, the operations performed by the arithmetic instructions affect flags
like carry, overflow, zero, etc. in the PSW [Link] the possible Mnemonics associated
with Arithmetic Instructions are mentioned in the following table.
Logical Instructions

The next group of instructions are the Logical Instructions, which perform logical operations
like AND, OR, XOR, NOT, Rotate, Clear and Swap. Logical Instruction are performed on
Bytes of data on a bit-by-bit basis.

Mnemonics associated with Logical Instructions are as follows:

 ANL
 ORL
 XRL
 CLR
 CPL
 RL
 RLC
 RR
 RRC
 SWAP

The following table shows all the possible Mnemonics of the Logical Instructions.
Boolean or Bit Manipulation Instructions

As the name suggests, Boolean or Bit Manipulation Instructions will deal with bit variables.
We know that there is a special bit-addressable area in the RAM and some of the Special
Function Registers (SFRs) are also bit addressable.

The Mnemonics corresponding to the Boolean or Bit Manipulation instructions are:

  CLR
 SETB
 MOV
 JC
 JNC
 JB
 JNB
 JBC
 ANL
 ORL
 CPL

These instructions can perform set, clear, and, or, complement etc. at bit level. All the
possible mnemonics of the Boolean Instructions are specified in the following table.
Program Branching Instructions

The last group of instructions in the 8051 Microcontroller Instruction Set are the Program
Branching Instructions. These instructions control the flow of program logic. The mnemonics
of the Program Branching Instructions are as follows.

 LJMP
 AJMP
 SJMP
 JZ
 JNZ
 CJNE
 DJNZ
 NOP
 LCALL
 ACALL
 RET
 RETI
 JMP

All these instructions, except the NOP (No Operation) affect the Program Counter (PC) in
one way or other. Some of these instructions have decision making capability before
transferring control to other part of the program.

The following table shows all the mnemonics with respect to the program branching
instructions.
8051 ADDRESSING MODES

An Addressing Mode is a way to locate a target Data, which is also called as Operand. The
8051 Family of Microcontrollers allows five types of Addressing Modes for addressing the
Operands. They are:

 Immediate Addressing
 Register Addressing
 Direct Addressing
 Register – Indirect Addressing
 Indexed Addressing

Immediate Addressing

In Immediate Addressing mode, the operand, which follows the Opcode, is a constant data of
either 8 or 16 bits. The name Immediate Addressing came from the fact that the constant data
to be stored in the memory immediately follows the Opcode.
The constant value to be stored is specified in the instruction itself rather than taking from a
register. The destination register to which the constant data must be copied should be the
same size as the operand mentioned in the instruction.
Example: MOV A, #030H
Here, the Accumulator is loaded with 30 (hexadecimal). The # in the operand indicates that it
is a data and not the address of a Register.
Immediate Addressing is very fast as the data to be loaded is given in the instruction itself.

Register Addressing

In the 8051 Microcontroller Memory Organization Tutorial, we have seen the organization of
RAM and four banks of Working Registers with eight Registers in each bank.
In Register Addressing mode, one of the eight registers (R0 – R7) is specified as Operand in
the Instruction.
It is important to select the appropriate Bank with the help of PSW Register. Let us see a
example of Register Addressing assuming that Bank0 is selected.
Example: MOV A, R5
Here, the 8-bit content of the Register R5 of Bank0 is moved to the Accumulator.

Direct Addressing

In Direct Addressing Mode, the address of the data is specified as the Operand in the
instruction. Using Direct Addressing Mode, we can access any register or on-chip variable.
This includes general purpose RAM, SFRs, I/O Ports, Control registers.
Example: MOV A, 47H
Here, the data in the RAM location 47H is moved to the Accumulator.

Register Indirect Addressing

In the Indirect Addressing Mode or Register Indirect Addressing Mode, the address of the
Operand is specified as the content of a Register. This will be clearer with an example.
Example: MOV A, @R1
The @ symbol indicates that the addressing mode is indirect. If the contents of R1 is 56H, for
example, then the operand is in the internal RAM location 56H. If the contents of the RAM
location 56H is 24H, then 24H is moved into accumulator.
Only R0 and R1 are allowed in Indirect Addressing Mode. These register in the indirect
addressing mode are called as Pointer registers.

Indexed Addressing Mode

With Indexed Addressing Mode, the effective address of the Operand is the sum of a base
register and an offset register. The Base Register can be either Data Pointer (DPTR) or
Program Counter (PC) while the Offset register is the Accumulator (A).
In Indexed Addressing Mode, only MOVC and JMP instructions can be used. Indexed
Addressing Mode is useful when retrieving data from look-up tables.
Example: MOVC A, @A+DPTR
Here, the address for the operand is the sum of contents of DPTR and Accumulator.

MODULE IV

PERIPHERAL INTERFACING
Parallel I/O (8255) Programmable Interval Timer (8253/8254)-Keyboard/Display Controller

8279) - Serial I/O (8251) using 8086 Microprocessor. A/D and D/A Interfacing -Temperature

Sensor Interfacing - Stepper Motor Interfacing using 8051 Microcontroller.

PERIPHERAL INTERFACING

PROGRAMMABLE INTERVAL TIMER/COUNTER 8254

The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for
microprocessors to perform timing and counting functions using three 16-bit registers. Each
counter has 2 input pins, i.e. Clock & Gate, and 1 pin for “OUT” output. To operate a
counter, a 16-bit count is loaded in its register. On command, it begins to decrement the
count until it reaches 0, then it generates a pulse that can be used to interrupt the CPU.

DIFFERENCE BETWEEN 8253 AND 8254

The following table differentiates the features of 8253 and 8254 −

8253 8254

Its operating frequency is 0 - 2.6 MHz Its operating frequency is 0 - 10 MHz

It uses N-MOS technology It uses H-MOS technology

Read-Back command is not available Read-Back command is available

Reads and writes of the same counter cannot be Reads and writes of the same counter can be
interleaved. interleaved.

FEATURES OF 8253 / 54

The most prominent features of 8253/54 are as follows −

 It has three independent 16-bit down counters.
 It can handle inputs from DC to 10 MHz.
 These three counters can be programmed for either binary or BCD count.
  It is compatible with almost all microprocessors.
 8254 has a powerful command called READ BACK command, which allows the user
to check the count value, the programmed mode, the current mode, and the current
status of the counter.

8254 PIN DESCRIPTION

Here is the pin diagram of 8254 −

8254 ARCHITECTURE

The architecture of 8254 looks as follows −

In the above figure, there are three counters, a data bus buffer, Read/Write control logic, and
a control register. Each counter has two input signals - CLOCK & GATE, and one output
signal - OUT.

Data Bus Buffer

It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the
system data bus. It has three basic functions −

 Programming the modes of 8253/54.

 Loading the count registers.

 Reading the count values.

Read/Write Logic

It includes 5 signals, i.e. RD, WR, CS, and the address lines A 0 & A1. In the peripheral I/O
mode, the RD and WR signals are connected to IOR and IOW, respectively. In the memory
mapped I/O mode, these are connected to MEMR and MEMW.
Address lines A0 & A1 of the CPU are connected to lines A 0 and A1 of the 8253/54, and CS is
tied to a decoded address. The control word register and counters are selected according to
the signals on lines A0 & A1.

A1 A0 Result

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control Word Register

X X No Selection

Control Word Register

This register is accessed when lines A 0 & A1 are at logic 1. It is used to write a command
word, which specifies the counter to be used, its mode, and either a read or write operation.
Following table shows the result for various control inputs.

A1 A0 RD WR CS Result

0 0 1 0 0 Write Counter 0

0 1 1 0 0 Write Counter 1

1 0 1 0 0 Write Counter 2

1 1 1 0 0 Write Control Word

0 0 0 1 0 Read Counter 0

0 1 0 1 0 Read Counter 1
 1 0 0 1 0 Read Counter 2

1 1 0 1 0 No operation

X X 1 1 0 No operation

X X X X 1 No operation

COUNTERS

Each counter consists of a single, 16 bit-down counter, which can be operated in either
binary or BCD. Its input and output is configured by the selection of modes stored in the
control word register. The programmer can read the contents of any of the three counters
without disturbing the actual count in process.

8253/54 can be operated in 6 different modes. In this chapter, we will discuss these
operational modes.

Mode 0 ─ Interrupt on Terminal Count

 It is used to generate an interrupt to the microprocessor after a certain interval.

 Initially the output is low after the mode is set. The output remains LOW after the
count value is loaded into the counter.
 The process of decrementing the counter continues till the terminal count is reached,
i.e., the count become zero and the output goes HIGH and will remain high until it
reloads a new count.
 The GATE signal is high for normal counting. When GATE goes low, counting is
terminated and the current count is latched till the GATE goes high again.

Mode 1 – Programmable One Shot

 It can be used as a mono stable multi-vibrator.

 The gate input is used as a trigger input in this mode.
 The output remains high until the count is loaded and a trigger is applied.

Mode 2 – Rate Generator

 The output is normally high after initialization.

 Whenever the count becomes zero, another low pulse is generated at the output and
the counter will be reloaded.
Mode 3 – Square Wave Generator

 This mode is similar to Mode 2 except the output remains low for half of the timer
period and high for the other half of the period.

Mode 4 − Software Triggered Mode

 In this mode, the output will remain high until the timer has counted to zero, at which
point the output will pulse low and then go high again.
 The count is latched when the GATE signal goes LOW.
 On the terminal count, the output goes low for one clock cycle then goes HIGH. This
low pulse can be used as a strobe.

Mode 5 – Hardware Triggered Mode

 This mode generates a strobe in response to an externally generated signal.

 This mode is similar to mode 4 except that the counting is initiated by a signal at the
gate input, which means it is hardware triggered instead of software triggered.
 After it is initialized, the output goes high.
 When the terminal count is reached, the output goes low for one clock cycle.
8255A - PROGRAMMABLE PERIPHERAL INTERFACE
The 8255A is a general purpose programmable I/O device designed to transfer the data from
I/O to interrupt I/O under certain conditions as required. It can be used with almost any
[Link] consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be
configured as per the requirement.

Ports of 8255A

8255A has three ports, i.e., PORT A, PORT B, and PORT C.

 Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
 Port B is similar to PORT A.
 Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper
(PC7-PC4) by the control word.
These three ports are further divided into two groups, i.e. Group A includes PORT A and
upper PORT C. Group B includes PORT B and lower PORT C. These two groups can be
programmed in three different modes, i.e. the first mode is named as mode 0, the second
mode is named as Mode 1 and the third mode is named as Mode 2.

Operating Modes

8255A has three different operating modes −

 Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-
bit ports. Each port can be programmed in either input mode or output mode where
outputs are latched and inputs are not latched. Ports do not have interrupt capability.
 Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can be
configured as either input or output ports. Each port uses three lines from port C as
handshake signals. Inputs and outputs are latched.
 Mode 2 − In this mode, Port A can be configured as the bidirectional port and Port B
either in Mode 0 or Mode 1. Port A uses five signals from Port C as handshake
signals for data transfer. The remaining three signals from Port C can be used either
as simple I/O or as handshake for port B.

Features of 8255A

The prominent features of 8255A are as follows −

 It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
 Address/data bus must be externally demux'd.
 It is TTL compatible.
 It has improved DC driving capability.

8255 ARCHITECTURE

The following figure shows the architecture of 8255A

Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data
bus. Data is transmitted or received by the buffer as per the instructions by the CPU. Control
words and status information is also transferred using this bus.

Read/Write Control Logic

This block is responsible for controlling the internal/external transfer of data/control/status

word. It accepts the input from the CPU address and control buses, and in turn issues
command to both the control groups.

CS

It stands for Chip Select. A LOW on this input selects the chip and enables the
communication between the 8255A and the CPU. It is connected to the decoded address,
and A0 & A1 are connected to the microprocessor address lines.

Their result depends on the following conditions −

CS A1 A0 Result

0 0 0 PORT A

0 0 1 PORT B

0 1 0 PORT C

0 1 1 Control Register

1 X X No Selection
WR

It stands for write. This control signal enables the write operation. When this signal goes
low, the microprocessor writes into a selected I/O port or control register.

RESET

This is an active high signal. It clears the control register and sets all ports in the input mode.

RD

It stands for Read. This control signal enables the Read operation. When the signal is low,
the microprocessor reads the data from the selected I/O port of the 8255.

A0 and A1

These input signals work with RD, WR, and one of the control signal. Following is the table
showing their various signals with their result.

A1 A0 RD WR CS Result

0 0 0 1 0 Input Operation
PORT A → Data Bus

0 1 0 1 0 PORT B → Data Bus

1 0 0 1 0 PORT C → Data Bus

Output Operation
0 0 1 0 0
Data Bus → PORT A

0 1 1 0 0 Data Bus → PORT A

1 0 1 0 0 Data Bus → PORT B

 1 1 1 0 0 Data Bus → PORT D

INTERFACING OF PPI 8255 WITH 8086 MICROPROCESSOR

 8255 is a programmable peripheral interface. It is used to interface microprocessor

with I/O devices via three ports: PA, PB and PC.
 All ports are 8-bit and bidirectional. 8255 transfers data with the microprocessor
through its 8-bit data bus. The two address lines A1 and A0 are used to make internal
selection in 8255.
 D7-D0 is connected to data lines of 8086, (RD) ̅ and (WR) ̅ is connected to (IOR) ̅ and
(IOW) ̅.
 A1 and A0 are connected with A2 and A1 of 8086 processor and A0 of 8086 is used
bank selection along with BHE.
 They can have 4 options, selecting PA, PB, PC or the control word. The ports are
selected to transfer data. The Control word is selected to send commands. Two
commands can be sent to 8255, called the I/O command and the BSR command.
 I/O command is used to initialize the mode and direction of the ports.
  BSR command is used to set or reset a single line of Port C.

Control word format for 8255A

8251 USART
8251 universal synchronous asynchronous receiver transmitter (USART) acts as a mediator
between microprocessor and peripheral to transmit serial data into parallel form and vice
versa.
1. It takes data serially from peripheral (outside devices) and converts into parallel data.
2. After converting the data into parallel form, it transmits it to the CPU.
3. Similarly, it receives parallel data from microprocessor and converts it into serial form.
4. After converting data into serial form, it transmits it to outside device (peripheral).

BLOCK DIAGRAM OF 8251 USART –

It contains the following blocks:
1. Data bus buffer –
This block helps in interfacing the internal data bus of 8251 to the system data bus. The
data transmission is possible between 8251 and CPU by the data bus buffer block.
2. Read/Write control logic –
It is a control block for overall device. It controls the overall working by selecting the
operation to be done. The operation selection depends upon input signals as:
 In this way, this unit selects one of the three registers- data buffer register, control
register, status register.

3. Modem control (modulator/demodulator) –

A device converts analog signals to digital signals and vice-versa and helps the
computers to communicate over telephone lines or cable wires. The following are
active-low pins of Modem.
1. DSR: Data Set Ready signal is an input signal.
2. DTR: Data terminal Ready is an output signal.
3. CTS: It is an input signal which controls the data transmit circuit.
RTS: It is an output signal which is used to set the status RTS.
4. Transmit buffer –
This block is used for parallel to serial converter that receives a parallel byte for
conversion into serial signal and further transmission onto the common channel.
1. TXD: It is an output signal, if its value is one, means transmitter will transmit
the data.
5. Transmit control –
This block is used to control the data transmission with the help of following pins:
1. TXRDY: It means transmitter is ready to transmit data character.
2. TXEMPTY: An output signal which indicates that TXEMPTY pin has
transmitted all the data characters and transmitter is empty now.
3. TXC: An active-low input pin which controls the data transmission rate of
transmitted data.
6. Receive buffer –
This block acts as a buffer for the received data.
1. RXD: An input signal which receives the data.
7. Receive control –
This block controls the receiving data.
1. RXRDY: An input signal indicates that it is ready to receive the data.
2. RXC: An active-low input signal which controls the data transmission rate of
received data.
3. SYNDET/BD: An input or output terminal. External synchronous mode-input
terminal and asynchronous mode-output terminal.
INTERFACING 8251A TO 8086 PROCESSOR

• The chip select for I/O mapped devices are generated by using a 3-to-8 decoder.

• The address lines A5, A6 and A7 are decoded to generate eight chip select signals (IOCS-0 to IOCS-
7) and in this, the chip select signal IOCS-2 is used to select 825lA.

• The address line A0 and the control signal M/IO(low) are used as enable for decoder.

• The line A1 of 8086 is connected to C/D(low) of 8251A to provide the internal addresses.

• The lines D0 – D7 connected to D0 – D7 of the processor to achieve parallel data transfer.

• The RESET and clock signals are supplied by 8284 clock generator. Here the processor clock is
directly connected to 8251A. This clock controls the parallel data transfer between the processor and
825lA.

• 8251A in I/O mapped in the system is shown in the figure.

 The peripheral clock (PCLK) supplied by 8284, is divided by suitable clock dividers
like programmable timer 8254 and then used as clock for serial transmission and
reception.
  In 8251A the transmission and reception baud rates can be different or same.
 The TTL logic levels of the serial data lines and the control signals necessary for
serial transmission and reception are converted to RS232 logic levels using MAX232
and then terminated on a standard 9-pin [Link] connector.
 The device, which requires serial communication with processor, can be connected to
this 9-pin D-type connector using 9-core cable
 The signals TxEMPTY, TxRDY and RxRDY can be used as interrupt signals to
initiate interrupt driven data transfer scheme between processor and 8251 A.
 The I/O addresses allotted to the internal devices of 8251A are listed in table.

8279 - PROGRAMMABLE KEYBOARD

8279 programmable keyboard/display controller is designed by Intel that interfaces a

keyboard with the CPU. The keyboard first scans the keyboard and identifies if any key has
been pressed. It then sends their relative response of the pressed key to the CPU and vice-a-
versa.

How Many Ways the Keyboard is Interfaced with the CPU?

The Keyboard can be interfaced either in the interrupt or the polled mode. In the Interrupt
mode, the processor is requested service only if any key is pressed, otherwise the CPU will
continue with its main task.

In the Polled mode, the CPU periodically reads an internal flag of 8279 to check whether
any key is pressed or not with key pressure.

How Does 8279 Keyboard Work?

The keyboard consists of maximum 64 keys, which are interfaced with the CPU by using the
key-codes. These key-codes are de-bounced and stored in an 8-byte FIFORAM, which can
be accessed by the CPU. If more than 8 characters are entered in the FIFO, then it means
more than eight keys are pressed at a time. This is when the overrun status is set.

If a FIFO contains a valid key entry, then the CPU is interrupted in an interrupt mode else
the CPU checks the status in polling to read the entry. Once the CPU reads a key entry, then
FIFO is updated, and the key entry is pushed out of the FIFO to generate space for new
entries.

ARCHITECTURE AND DESCRIPTION

I/O Control and Data Buffer

This unit controls the flow of data through the microprocessor. It is enabled only when D is
low. Its data buffer interfaces the external bus of the system with the internal bus of the
microprocessor. The pins A0, RD, and WR are used for command, status or data read/write
operations.

Control and Timing Register and Timing Control

This unit contains registers to store the keyboard, display modes, and other operations as
programmed by the CPU. The timing and control unit handles the timings for the operation
of the circuit.

Scan Counter

It has two modes i.e. Encoded mode and Decoded mode. In the encoded mode, the counter
provides the binary count that is to be externally decoded to provide the scan lines for the
keyboard and display.

In the decoded scan mode, the counter internally decodes the least significant 2 bits and
provides a decoded 1 out of 4 scan on SL0-SL3.

Return Buffers, Keyboard Debounce, and Control

This unit first scans the key closure row-wise, if found then the keyboard debounce unit
debounces the key entry. In case, the same key is detected, then the code of that key is
directly transferred to the sensor RAM along with SHIFT & CONTROL key status.

FIFO/Sensor RAM and Status Logic

This unit acts as 8-byte first-in-first-out (FIFO) RAM where the key code of every pressed
key is entered into the RAM as per their sequence. The status logic generates an interrupt
request after each FIFO read operation till the FIFO gets empty.

In the scanned sensor matrix mode, this unit acts as sensor RAM where its each row is
loaded with the status of their corresponding row of sensors into the matrix. When the
sensor changes its state, the IRQ line changes to high and interrupts the CPU.

Display Address Registers and Display RAM

This unit consists of display address registers which holds the addresses of the word
currently read/written by the CPU to/from the display RAM.

8279 − PIN DESCRIPTION

The following figure shows the pin diagram of 8279 −

Data Bus Lines, DB0 - DB7

These are 8 bidirectional data bus lines used to transfer the data to/from the CPU.

CLK

The clock input is used to generate internal timings required by the microprocessor.

RESET

As the name suggests this pin is used to reset the microprocessor.

CS Chip Select

When this pin is set to low, it allows read/write operations, else this pin should be set to
high.

A0

This pin indicates the transfer of command/status information. When it is low, it indicates
the transfer of data.

RD, WR

This Read/Write pin enables the data buffer to send/receive data over the data bus.

IRQ

This interrupt output line goes high when there is data in the FIFO sensor RAM. The
interrupt line goes low with each FIFO RAM read operation. However, if the FIFO RAM
further contains any key-code entry to be read by the CPU, this pin again goes high to
generate an interrupt to the CPU.

Vss, Vcc

These are the ground and power supply lines of the microprocessor.

SL0 − SL3

These are the scan lines used to scan the keyboard matrix and display the digits. These lines
can be programmed as encoded or decoded, using the mode control register.

RL0 − RL7

These are the Return Lines which are connected to one terminal of keys, while the other
terminal of the keys is connected to the decoded scan lines. These lines are set to 0 when any
key is pressed.

SHIFT

The Shift input line status is stored along with every key code in FIFO in the scanned
keyboard mode. Till it is pulled low with a key closure, it is pulled up internally to keep it
high
CNTL/STB - CONTROL/STROBED I/P Mode

In the keyboard mode, this line is used as a control input and stored in FIFO on a key
closure. The line is a strobe line that enters the data into FIFO RAM, in the strobed input
mode. It has an internal pull up. The line is pulled down with a key closure.

BD

It stands for blank display. It is used to blank the display during digit switching.

OUTA0 – OUTA3 and OUTB0 – OUTB3

These are the output ports for two 16x4 or one 16x8 internal display refresh registers. The
data from these lines is synchronized with the scan lines to scan the display and the
keyboard.

OPERATIONAL MODES OF 8279

There are two modes of operation on 8279 − Input Mode and Output Mode.

Input Mode

This mode deals with the input given by the keyboard and this mode is further classified into
3 modes.

 Scanned Keyboard Mode − In this mode, the key matrix can be interfaced using
either encoded or decoded scans. In the encoded scan, an 8×8 keyboard or in the
decoded scan, a 4×8 keyboard can be interfaced. The code of key pressed with
SHIFT and CONTROL status is stored into the FIFO RAM.
 Scanned Sensor Matrix − In this mode, a sensor array can be interfaced with the
processor using either encoder or decoder scans. In the encoder scan, 8×8 sensor
matrix or with decoder scan 4×8 sensor matrix can be interfaced.
 Strobed Input − In this mode, when the control line is set to 0, the data on the return
lines is stored in the FIFO byte by byte.

Output Mode

This mode deals with display-related operations. This mode is further classified into two
output modes.
  Display Scan − This mode allows 8/16 character multiplexed displays to be
organized as dual 4-bit/single 8-bit display units.
 Display Entry − This mode allows the data to be entered for display either from the
right side/left side.

INTERFACING ADC TO 8051

ADC (Analog to digital converter) forms a very essential part in many embedded projects and
this article is about interfacing an ADC to 8051 embedded controller. ADC 0804 is the ADC
used here and before going through the interfacing procedure, we must neatly understand
how the ADC 0804 works.

ADC 0804.

ADC receives analog signal from the source. This analog signal is received from one of the 8
input channels of ADC0804. Then this signal is processed accordingly and converted to
corresponding digital signal. This signal is then sent to the microcontroller and the output is
displayed using Light Emitting Diode (LED)[5].
Block diagram for interfacing ADC with 8051 microcontroller

ADC0804 is an 8 bit successive approximation analogue to digital

converter from National semiconductors. The features of ADC0804
are differential analogue voltage inputs, 0-5V input voltage range,
no zero adjustment, built in clock generator, reference voltage can
be externally adjusted to convert smaller analogue voltage span to 8
bit resolution etc. The pin out diagram of ADC0804 is shown in the
figure below.
The voltage at Vref/2 (pin9) of ADC0804 can be externally adjusted to convert smaller input
voltage spans to full 8 bit resolution. Vref/2 (pin9) left open means input voltage span is 0-5V
and step size is 5/255=19.6mV. Have a look at the table below for different Vref/2 voltages
and corresponding analogue input voltage spans.

Vref/2 (pin9) (volts) Input voltage span (volts) Step size (mV)

Left open 0–5 5/255 = 19.6

2 0–4 4/255 = 15.69

1.5 0–3 3/255 = 11.76

1.28 0 – 2.56 2.56/255 = 10.04

1.0 0–2 2/255 = 7.84

0.5 0–1 1/255 = 3.92

ALGORITHM FOR PROGRAMMING ADC

 Make CS=0 and send a low to high pulse to WR pin to start the conversion.

 Now keep checking the INTR pin. INTR will be 1 if conversion is not finished and
INTR will be 0 if conversion is finished.

 If conversion is not finished (INTR=1) , poll until it is finished.

 If conversion is finished (INTR=0), go to the next step.

 Make CS=0 and send a high to low pulse to RD pin to read the data from the ADC.

 The entire circuit can be powered from 5V DC.

 ADC 0804 has active low outputs and the instruction CPL A complements it t0 have a
straight forward display. For example, if input is 5V then the output will be 11111111
and if CPL A was not used it would have been 00000000 which is rather awkward to
see.

INTERFACING DAC WITH 8051 MICROCONTROLLER

The Digital to Analog converter (DAC) is a device, which is widely used for converting
digital pulses to analog signals. There are two methods of converting digital signals to
Analog signals. These two methods are binary weighted method and R/2R ladder method. In
this article we will use the MC1408 (DAC0808) Digital to Analog Converter. This chip uses
R/2R ladder method. This method can achieve a much higher degree of precision. DACs are
judged by its resolution. The resolution is a function of the number of binary inputs. The most
common input counts are 8, 10, 12 etc. Number of data inputs decides the resolution of DAC.
So if there are n digital input pin, there are 2 n analog levels. So 8 inputs DAC has 256 discrete
voltage levels.

The MC1408 DAC (or DAC0808)

In this chip the digital inputs are converted to current. The output current is known as Iout by
connecting a resistor to the output to convert into voltage. The total current provided by
the Iout pin is basically a function of the binary numbers at the input pins D 0 - D7 (D0 is the
LSB and D7 is the MSB) of DAC0808 and the reference current I ref. The following formula is
showing the function of Iout

The Iref is the input current. This must be provided into the pin 14. Generally 2.0mA is used
as Iref. We connect the Iout pin to the resistor to convert the current to voltage. But in real life it
may cause inaccuracy since the input resistance of the load will also affect the output voltage.
So practically Iref current input is isolated by connecting it to an Op-Amp with R f = 5KΩ as
feedback resistor. The feedback resistor value can be changed as per requirement.

Generating Sinewave using DAC and 8051 Microcontroller

For generating sine wave, at first we need a look-up table to represent the magnitude of the
sine value of angles between 0° t 360°. The sine function varies from -1 to +1. In the table
only integer values are applicable for DAC input. In this example we will consider 30°
increments and calculate the values from degree to DAC input. We are assuming full-scale
voltage of 10V for DAC output. We can follow this formula to get the voltage ranges.
Vout = 5V + (5 ×sinθ)

Angle(in θ ) Sinθ Vout (Voltage Magnitude) Values sent to DAC

0 0 5 128

30 0.5 7.5 192

60 0.866 9.33 238

90 1.0 10 255

120 0.866 9.33 238

150 0.5 7.5 192

180 0 5 128

210 -0.5 2.5 64

240 -0.866 0.669 17

270 -1.0 0 0

300 -0.866 0.669 17

330 -0.5 2.5 64

360 0 5 128

Output
The output will look like this −
INTERFACING STEPPER MOTOR WITH 8051MICROCONTROLLER

Stepper Motor
Stepper motors are used to translate electrical pulses into mechanical movements. In some
disk drives, dot matrix printers, and some other different places the stepper motors are used.
The main advantage of using the stepper motor is the position control. Stepper motors
generally have a permanent magnet shaft (rotor), and it is surrounded by a stator.

Normal motor shafts can move freely but the stepper motor shafts move in fixed repeatable
increments.
Some parameters of stepper motors −

 Step Angle − The step angle is the angle in which the rotor moves when one pulse is
applied as an input of the stator. This parameter is used to determine the positioning
of a stepper motor.
 Steps per Revolution − This is the number of step angles required for a complete
revolution. So the formula is 360° /Step Angle.
 Steps per Second − This parameter is used to measure a number of steps covered in
each second.
 RPM − The RPM is the Revolution Per Minute. It measures the frequency of
rotation. By this parameter, we can measure the number of rotations in one minute.

The relation between RPM, steps per revolution, and steps per second is like below:

Steps per Second = rpm x steps per revolution / 60

INTERFACING STEPPER MOTOR WITH 8051 MICROCONTROLLER

We are using Port P0 of 8051 for connecting the stepper motor. HereULN2003 is used. This
is basically a high voltage, high current Darlington transistor array. Each ULN2003 has seven
NPN Darlington pairs. It can provide high voltage output with common cathode clamp diodes
for switching inductive loads.
The Unipolar stepper motor works in three modes.
 Wave Drive Mode − In this mode, one coil is energized at a time. So all four coils are
energized one after another. This mode produces less torque than full step drive mode.

The following table is showing the sequence of input states in different windings.

Steps Winding A Winding B Winding C Winding D

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

 Full Drive Mode − In this mode, two coils are energized at the same time. This mode
produces more torque. Here the power consumption is also high

The following table is showing the sequence of input states in different windings.

Steps Winding A Winding B Winding C Winding D

1 1 1 0 0

2 0 1 1 0

3 0 0 1 1

4 1 0 0 1
  Half Drive Mode − In this mode, one and two coils are energized alternately. At first,
one coil is energized then two coils are energized. This is basically a combination of
wave and full drive mode. It increases the angular rotation of the motor.

The following table is showing the sequence of input states in different windings.

Steps Winding A Winding B Winding C Winding D

1 1 0 0 0

2 1 1 0 0

3 0 1 0 0

4 0 1 1 0

5 0 0 1 0

6 0 0 1 1

7 0 0 0 1

8 1 0 0 1

MEASURING TEMPERATURE WITH LM35 USING 8051:

Sometimes people find it difficult to read temperature from analog thermometer because of
fluctuations. So here we are going to build a simple Digital thermometer using 8051
microcontroller in which LM35 sensor is used for measuring the [Link] will also
serve as a proper interfacing of ADC0804 with 8051 and 16*2 LCD with 8051
microcontroller. Microcontroller is a 8 bit microcontroller which has 128 bytes of on
chip RAM , 4K bytes of on chip ROM, two timers, one serial port and four 8bit ports.

Components Required:
 8051 development board
 ADC0804 board
 16*2 LCD display
 LM35 sensor
 Potentiometer
 Jumper wires

Block diagram

16x2 LCD:
16*2 LCD is a widely used display for embedded applications. Here is the brief explanation
about pins and working of 16*2 LCD display. There are two very important registers inside
the LCD. They are data register and command register. Command register is used to send
commands such as clear display, cursor at home etc., data register is used to send data which
is to be displayed on 16*2 LCD. Below table shows the pin description of 16*2 LCD.

Symbo
Pin I/O Description
l

1 Vss - Ground

2 Vdd - +5V power supply

Power supply to control

3 Vee -
contrast

RS=0 for command

4 RS I
register , RS=1 for data register

R/W=0 for write , R/W=1 for

5 RW I
read

6 E I/O Enable

7 D0 I/O 8-bit data bus(LSB)

8 D1 I/O 8-bit data bus

9 D2 I/O 8-bit data bus

 10 D3 I/O 8-bit data bus

11 D4 I/O 8-bit data bus

12 D5 I/O 8-bit data bus

13 D6 I/O 8-bit data bus

14 D7 I/O 8-bit data bus(MSB)

15 A - +5V for backlight

16 K - Ground

The below table shows frequently used LCD command codes.

Code(hex
Description
)

01 Clear display screen

06 Increment cursor (right shift)

0A Display off , cursor on

0C Display on , cursor off

 0F Display on , cursor blinking

80 Force the cursor to beginning of 1st line

C0 Force the cursor to beginning of 2nd line

38 2 lines and 5*7 matrix

ADC0804 IC:

The ADC0804 IC is an 8-bit parallel ADC in the family of the ADC0800 series from
National Semiconductor. It works with +5 volts and has a resolution of 8bits. The step size
and Vin range varies for different values of Vref/2. The table below shows the relation
between Vref/2 and Vin range.

Vref/2 (V) Vin (V) Step size (mV)

open 0 to 5 19.53

2.0 0 to 4 15.62

1.5 0 to 3 11.71

0 to
1.28 10
2.56
In our case Vref/2 is connected to 1.28 volts, so step size is 10mV. For ADC0804 step size is
calculated as (2 * Vref / 2) / 256.

Following formula is used to calculate output voltage:

Dout = Vin / step size

Where Dout is digital data output in decimal, Vin = analog input voltage and step size
(resolution) is the smallest change. Learn more about ADC0804 here, also check interfacing
of ADC0808 with 8051.

LM35 Temperature Sensor:

The LM35 is a temperature sensor whose output voltage is linearly proportional to Celsius
temperature. The LM35 comes already calibrated hence requires no external calibration. It
outputs 10mV for each degree of Celsius temperature.

LM35 sensor produces voltage corresponding to temperature. This voltage is converted to

digital (0 to 256) by ADC0804 and it is fed to 8051 microcontroller. 8051 microcontroller
converts this digital value into temperature in degree Celsius. Then this temperature is
converted into ascii form which is suitable for displaying. This ascii values are fed to 16*2
lcd which displays the temperature on its screen. This process is repeated after specified
interval.

MODULE V

ADVANCED MICROPROCESSOR AND MICROCONTROLLER

Architecture of AVR , PIC and ARM Microcontrollers - JTAG Concepts and Boundary Scan

Architecture - Core 2 duo Processor - i7 Core Processor(Qualitative Study).

ADVANCED MICROPROCESSOR & MICROCONTROLLER

ARM MICROCONTROLLER
The ARM microcontroller stands for Advance Risk Machine; it is one of the extensive and
most licensed processor cores in the world. The first ARM processor was developed in the
year 1978 by Cambridge University, and the first ARM RISC processor was produced by the
Acorn Group of Computers in the year 1985. These processors are specifically used in
portable devices like digital cameras, mobile phones, home networking modules and wireless
communication technologies and other embedded systems due to the benefits, such as low
power consumption, reasonable performance, etc. This article gives an overview of ARM
architecture with each module’s principle of working.

ARM ARCHITECTURE

The ARM architecture processor is an advanced reduced instruction set computing [RISC]
machine and it’s a 32bit reduced instruction set computer (RISC) microcontroller. It was
introduced by the Acron computer organization in 1987. This ARM is a family of
microcontroller developed by makers like ST Microelectronics,Motorola, and so on. The
ARM architecture comes with totally different versions like ARMv1, ARMv2, etc., and, each
one has its own advantage and disadvantages.

The ARM cortex microcontroller is an advanced microcontroller in the ARM family, which
is developed by the ARMv7 architecture. The ARM cortex family divided into three sub-
families such as;

 ARM-Cortex Ax-series
 ARM-Cortex Rx-series
 ARM-Cortex Mx-series
ARM Coretex-M3 Microcontroller Architecture

The cortex-M3 ARM processor is a high performance 32-bit processor, which offers the
significant benefits to the developers. The ARM architecture is a ‘Harward architecture’
which offers separate data and instruction buses for communicating with the ROM and RAM
memories. It consist a 3-stage pipeline to fetch, decode and execute the instructions
sequentially. The Cortex processor is a cost sensitive device which is used to reduce the
processor area and has extensive improving interrupt handling and system debug capabilities.

ARM Coretex-M3 Microcontroller Architecture

The cortex-M3 arm processors are implemented by THUMB instruction set based on
THUMB-2 technology, therefore, ensures high code density and reduce the program memory
requirement. The cortex-m3 instruction set provides the excellent performance due to modern
32-bit architecture. The ARM processor core-m3 is closely integrated to Nested Vector
Interrupt Controller (NVIC) to provide the good interrupt [Link] debug access port
(DAP) is part of the ARM emulation logic and enabes an external debugger to directly access
the entire memory space of the device without requiring the processor to enter the debug state
and be programmed with load or store instruction.
Additional Features of the Cortex-M3 Processor

It is a RISC Controller

 32-bit high performance CPU

 3-stage pipeline and compact one

It has THUMB-2 technology

 Optimal merges of 16/32 bit instructions

 High performance

It supports tools and RTOS and It has core Sight debug and trace

 JTAG or 2-pin serial wire debug connection

 Support for multiple processors

Low power Modes

 It supports sleep modes

 Control the software
 Multiple power domains

Nested vectored interrupt controller (NVIC)

 Low latency, low jitter interrupts response

 No need for assembly programming

ARM Microcontroller Register Modes

An ARM micrOcontroller is a load store reducing instruction set computer architecture

means the core cannot directly operate with the memory. The data operations must be done
by the registers and the information is stored in the memory by an address. The ARM cortex-
M3 consists of 37 register sets wherein 31 are general purpose registers and 6 are status
registers. The ARM uses seven processing modes to run the user task.

 USER Mode
 FIQ Mode
  IRQ Mode
 SVC Mode
 UNDEFINED Mode
 ABORT Mode
 Monitor Mode

ARM Microcontroller Register Modes

USER Mode: The user mode is a normal mode, which has the least number of registers. It
doesn’t have SPSR and has limited access to the CPSR.
FIQ and IRQ: The FIQ and IRQ are the two interrupt caused modes of the CPU. The FIQ is
processing interrupt and IRQ is standard interrupt. The FIQ mode has additional five banked
registers to provide more flexibility and high performance when critical interrupts are
handled.
SVC Mode: The Supervisor mode is the software interrupt mode of the processor to start up
or reset.
Undefined Mode: The Undefined mode traps when illegal instructions are executed. The
ARM core consists of 32-bit data bus and faster data flow.
THUMB Mode: In THUMB mode 32-bit data is divided into 16-bits and increases the
processing speed.
THUMB-2 Mode: In THUMB-2 mode the instructions can be either 16-bit or 32-bit and it
increases the performance of the ARM cortex –M3 microcontroller. The ARM cortex-m3
microcontroller uses only THUMB-2 instructions.
Some of the registers are reserved in each mode for the specific use of the core. The reserved
registers are

 Stack Pointer (SP).

 Link Register (LR).
 Program Counter (PC).
 Current Program Status Register (CPSR).
 Saved Program Status Register (SPSR).

The reserved registers are used for specific functions. The SPSR and CPSR contain the status
control bits which are used to store the temporary data. The SPSR and CPSR register have
some properties that are defined operating modes, Interrupt enable or disable flags and ALU
status flag. The ARM core operates in two states 32-bit state or THUMBS state.

AVR MICROCONTROLLER

AVR Microcontrollers are extremely popular MCUs used in various application specially in
project prototyping and embedded devices. AVR is a 8 bit RISC architecture (reduced
instruction set computing) microcontroller in market since 1996 which is having on-chip
programmable flash memory, SRAM ,IO data space & [Link] is the first MCU in
market which has on-chip flash storage.
Data BUS 8 bit :Its an 8-bit parallel data lines by which the data travels inside the MCU
(NOTE: this is the reason why AVR is an 8-bit MCU).

ALU: Arithmetic Logic Unit, the core/heart of the entire system where typically all
commandsget executed.

Data SRAM: It basically pretty similar to the RAM (Random access memory) we see inside
our computers.
EEPROM: (Electrically Erasable Programmable Read Only Memory) its very similar to
another component in our computer namely HardDisk, i.e. a permanent storage.

I/O lines: These are the bunch of registers which is used as a switches or controls for
different features of AVR.

32X8 GPR (General Purpose Registers): This are 32 registers each having 8-bit which is a
general storage space for data. But, remember, SRAM is also a temporary storage but these
registers have some specialty among all.

Status &Control : A couple of registers which are very special to the MCU & to us also.

Program Counter: This is a register which has a responsibility to track the position of the
program that is currently executing.

Flash Memory: It is also a permanent storage but its only for storing the program we write to
it.

Instruction Register & Decoder: These are import for the MCU but not too much to us.

PIC MICROCONTROLLER

PIC is a Peripheral Interface Microcontroller which was developed in the year 1993 by the
General Instruments Microcontrollers. It is controlled by software and programmed in such a
way that it performs different tasks and controls a generation line. PIC microcontrollers are
used in different new applications such as smart phones, audio accessories, and advanced
medical devices.
 PIC Microcontrollers

There are many PICs available in the market ranging from PIC16F84 to PIC16C84. These
types of PICs are affordable flash PICs. Microchip has recently introduced flash chips with
different types, such as 16F628, 16F877, and 18F452. The 16F877 costs twice the price of
the old 16F84, but it is eight times more than the code size, with more RAM and much more
I/O pins, a UART, A/D converter and a lot more features.

PIC Microcontrollers Architecture

The PIC microcontroller is based on RISC architecture. Its memory architecture follows the
Harvard pattern of separate memories for program and data, with separate buses.
 PIC microcontroller architecture

1. Memory Structure

The PIC architecture consists of two memories: Program memory and Data memory.

Program Memory: This is a 4K*14 memory space. It is used to store 13-bit instructions or
the program code. The program memory data is accessed by the program counter register that
holds the address of the program memory. The address 0000H is used as reset memory space
and 0004H is used as interrupt memory space.

Data Memory: The data memory consists of the 368 bytes of RAM and 256 bytes of
EEPROM. The 368 bytes of RAM consists of multiple banks. Each bank consists of general-
purpose registers and special function registers.
The special function registers consist of control registers to control different operations of the
chip resources like Timers, Analog to Digital Converters, Serial ports, I/O ports, etc. For
example, the TRISA register whose bits can be changed to alter the input or output operations
of the port A. The general-purpose registers consist of registers that are used to store
temporary data and processing results of the data. These general-purpose registers are each 8-
bit registers.

Working Register: It consists of a memory space that stores the operands for each
instruction. It also stores the results of each execution.

Status Register: The bits of the status register denotes the status of the ALU (arithmetic
logic unit) after every execution of the instruction. It is also used to select any one of the 4
banks of the RAM.

File Selection Register: It acts as a pointer to any other general-purpose register. It consists
of a register file address, and it is used in indirect addressing.
Another general-purpose register is the program counter register, which is a 13-bit register.
The 5 upper bits are used as PCLATH (Program Counter Latch) to independently function as
any other register, and the lower 8-bits are used as the program counter bits. The program
counter acts as a pointer to the instructions stored in the program memory.

EEPROM: It consists of 256 bytes of memory space. It is a permanent memory like ROM,
but its contents can be erased and changed during the operation of the microcontroller. The
contents into EEPROM can be read from or written to, using special function registers like
EECON1, EECON, etc.

2. I/O Ports

PIC16 series consists of five ports, such as Port A, Port B, Port C, Port D, and Port E.

Port A: It is a 16-bit port, which can be used as an input or output port based on the status of
the TRISA register.
Port B: It is an 8-bit port, which can be used as both an input and output port. 4 of its bits,
when used as input, can be changed upon interrupt signals.
Port C: It is an 8-bit port whose operation (input or output) is determined by the status of the
TRISC register.
Port D: It is an 8-bit port, which apart from being an I/O port, acts as a slave port for
connection to the microprocessor bus.
Port E: It is a 3-bit port that serves the additional function of the control signals to the A/D
converter.

3. Timers

PIC microcontrollers consist of 3 timers, out of which the Timer 0 and Timer 2 are 8-bit
timers and the Time-1 is a 16-bit timer, which can also be used as a counter.
4. A/D Converter

The PIC Microcontroller consists of 8-channels, 10-bit Analog to Digital Converter. The
operation of the A/D converter is controlled by these special function registers: ADCON0
and ADCON1. The lower bits of the converter are stored in ADRESL (8 bits), and the upper
bits are stored in the ADRESH register. It requires an analog reference voltage of 5V for its
operation.

5. Oscillators

Oscillators are used for timing generation. PIC microcontrollers consist of external oscillators
like crystals or RC oscillators. In the case of crystal oscillators, the crystal is connected
between two oscillator pins, and the value of the capacitor connected to each pin determines
the mode of operation of the oscillator. The different modes are low-power mode, crystal
mode, and the high- speed mode. In the case of RC oscillators, the value of the Resistor and
Capacitor determines the clock frequency. The clock frequency ranges from 30 kHz to 4
MHz.

6. CCP module:

A CCP module works in the following three modes:

Capture Mode: This mode captures the time of arrival of a signal, or in other words,
captures the value of the Timer1 when the CCP pin goes high.
Compare Mode: It acts as an analog comparator that generates an output when the timer1
value reaches a certain reference value.
PWM Mode: It provides pulse width modulated output with a 10-bit resolution and
programmable duty cycle.
Other special peripherals include a Watchdog timer that resets the microcontroller in case of
any software malfunction and a Brownout reset that resets the microcontroller in case of any
power fluctuation and others. For a better understanding of this PIC microcontroller, we are
giving one practical project which uses this controller for its operation.

BOUNDARY SCAN

Introduction
Boundary-scan is an integrated method for testing interconnects on printed circuit boards
(PCBs) that are implemented at the integrated circuit (IC) level. Boundary Scanis commonly
referred to as JTAG and defined by the Institute of Electrical and Electronic Engineers
(IEEE) 1149.1, which originally began as an integrated method for testing interconnects on
printed circuit boards (PCBs) implemented at the integrated circuit (IC) level. Since its
introduction as an industry standard in 1990, boundary-scan (also known as JTAG) has
enjoyed growing popularity for board level manufacturing test applications. Boundary-scan
has rapidly become the technology of choice for building reliable high technology electronic
products with a high degree of testability. Due to the low-cost and IC level access capabilities
of boundary-scan, its use has expanded beyond traditional board test applications into product
design and service.

Boundary-scan, as defined by the IEEE Std.-1149.1 standard, is an integrated method for

testing interconnects on printed circuit boards (PCBs) that are implemented at the integrated
circuit (IC) level. The inability to test highly complex and dense printed circuit boards using
traditional in-circuit testers and bed of nail fixtures was already evident in the mid-eighties.
Due to physical space constraints and loss of physical access to fine pitch components and
BGA devices, fixturing cost increased dramatically while fixture reliability decreased at the
same time.

A Brief History of Boundary-Scan

In the 1980s, the Joint Test Action Group (JTAG) developed a specification for boundary-
scan testing that was standardized in 1990 as the IEEE Std. 1149.1-1990. In 1993 a new
revision to the IEEE Std. 1149.1 standard was introduced (titled 1149.1a) and it contained
many clarifications, corrections, and enhancements. In 1994, a supplement containing a
description of the Boundary-Scan Description Language (BSDL) was added to the standard.
Since that time, this standard has been adopted by major electronics companies all over the
world. Applications are found in high volume, high-end consumer products,
telecommunication products, defence systems, computers, peripherals, and avionics. In fact,
due to its economic advantages, some smaller companies that cannot afford expensive in-
circuit testers are using boundary-scan.
The boundary-scan test architecture provides a means to test interconnects between integrated
circuits on a board without using physical test probes. It adds a boundary-scan cell that
includes a multiplexer and latches to each pin on the device. Boundary-scan cells in a device
can capture data from pin or core logic signals, or force data onto pins. Captured data is
serially shifted out and externally compared to the expected results. Forced test data is
serially shifted into the boundary-scan cells. All of this is controlled from a serial data path
called the scan path or scan chain. Figure 1 depicts the main elements of a boundary-scan
cell. By allowing direct access to nets, boundary-scan eliminates the need for a large number
of test vectors, which are normally needed to properly initialize sequential logic. Tens or
hundreds of vectors may do the job that had previously required thousands of vectors.
Potential benefits realized from the use of boundary-scan are shorter test times, higher test
coverage, increased diagnostic capability and lower capital equipment cost.
Figure 1 – Typical Boundary-Scan Cell

The principles of interconnect test using boundary-scan are illustrated in Figure 2. Figure 2
depicts two boundary-scan compliant devices, U1 and U2, which are connected with four
nets. U1 includes four outputs that are driving the four inputs of U2 with various values. In
this case, we assume that the circuit includes two faults: a short between Nets 2 and 3, and an
open on Net 4. We will also assume that a short between two nets behaves as a wired-AND
and an open is sensed as logic 1. To detect and isolate the above defects, the tester is shifting
into the U1 boundary-scan register the patterns shown in Figure 2 and applying these patterns
to the inputs of U2. The inputs values of U2 boundary-scan register are shifted out and
compared to the expected results. In this case, the results (marked in red) on Nets 2, 3, and 4
do not match the expected values and, therefore, the tester detects the faults on Nets 2, 3, and
4.

Boundary-scan tool vendors provide various types of stimulus and sophisticated algorithms,
not only to detect the failing nets, but also to isolate the faults to specific nets, devices, and
pins.
 Figure 2 – Interconnect Test Example
Boundary-Scan Chip Architecture
The IEEE-1149.1 standard defines test logic in an integrated circuit which provides
applications to perform:Chain integrity testing

 Interconnection testing between devices

 Core logic testing (BIST)
 In-system programming
 In-Circuit EmulationFunctional testing
Boundary-Scan Chain with Multiple Chips

Boundary-Scan Test Vectors

 JTAG TAP Interface Signals

Required Test Instructions

Working in conjunction with the TAP controller is an IR (Instruction Register) providing
which type of test to perform? The 1149.1 Standard requires that all compliant devices must
perform the following three instructions:
 EXTEST Instruction
The EXTEST instruction performs a PCB interconnect test, places an IEEE 1149.1 compliant
device into an external boundary test mode, and selects the boundary scan register to be
 connected between TDI and TDO. During EXTEST instruction, the boundary scan cells
associated with outputs are preloaded with test patterns to test downstream devices. The input
boundary cells are set up to capture the input data for later analysis.

 SAMPLE/PRELOAD Instruction

The SAMPLE/PRELOAD instruction allows an IEEE 1149.1 compliant device to remain in

its functional mode and selects the boundary scan register to be connected between the TDI
and TDO pins. During SAMPLE/PRELOAD instruction, the boundary scan register can be
accessed through a data scan operation, to take a sample of the functional data input/output of
the device. Test data can also be preloaded into the boundary-scan register prior to loading an
EXTEST instruction.

 BYPASS Instruction

Using the BYPASS instruction, a device’s boundary scan chain can be skipped, allowing the
data to pass through the bypass register. This allows efficient testing of a selected device
without incurring the overhead of traversing through other devices. The BYPASS instruction
allows an IEEE 1149.1 compliant device to remain in a functional mode and selects the
bypass register to be connected between the TDI and TDO pins. Serial data is allowed to be
transferred through a device from the TDI pin to the TDO pin without affecting the operation
of the device.

Boundary-Scan Applications

While it is obvious that boundary-scan based testing can be used in the production phase of a
product, new developments and applications of the IEEE-1149.1 standard have enabled the
use of boundary-scan in many other product life cycle phases. Specifically, boundary-scan
technology is now applied to product design, prototype debugging and field service as
depicted in Figure 3. This means the cost of the boundary-scan tools can be amortized over
the entire product life cycle, not just the production phase.
Figure 3 – Product Life Cycle Support
To facilitate this product life cycle concept, boundary-scan tool vendors such as Corelis offer
an integrated family of software and hardware solutions for all phases of a product’s life-
cycle. All of these products are compatible with each other, thus protecting the user’s
investment.

CORE 2 DUO NOTEBOOK PROCESSOR (CPU)

The Intel Core 2 Duo (also known as Core2 Duo) notebook processor is a 64 bit dual core
processor. This means two processor cores work inside a Core 2 Duo in [Link] Core 2
Duo, which was introduced on July 27 2006, is the direct successor of the Core Duo. Each
core is based on the Pentium M micro architecture. Compared with the old Netburst
architecture of the Pentium 4, the cores in the Core 2 Duo have shorter pipelines. As a
result, the maximum clock rate is lower but the performance per clock is significantly higher.
Thus a Pentium 4M with the same clock rate is up to 40% [Link], the notebook Core 2
Duo and the desktop Core 2 Duo are based on the same processor. However, the notebook
version runs with a lower voltage (0.95 to 1.188 volt) and a lower front side bus (1066 vs.
667 MHz). As a result (and because of slower laptop hard discs) the performance of
notebooks is about 20% lower than their desktop counterparts with the same clock rate.

Key Features

 64 bit support
 Dual core processor with shared level 2 cache
 Execute Disable Bit
 Partially Intel Virtualization Technology (VT)
 Socket M (starting from Santa Rosa socket P)
 291 million transistors

Performance

The performance of the Core 2 Duo processor in comparison with its direct competitor, the
AMD Turion 64 X2, is very good. The Core 2 Duo beats the AMD Turion 64 X2 with the
same clock rate in virtually all applications (on average by 15%). The energy consumption is
similar in both processors. In comparison with the predecessor Core Duo, the Core 2 Duo is
about 10% faster and consumes a bit more energy.

Specifications
The Core 2 Duo processors are produced in 65 nm (and later in 45nm), contain 14 stages
pipelines and 2-4 MB level 2 cache (depending on the model). The features of the Core 2
Duo are:
x86 architecture
The Intel Core 2 Duo uses the x86 instruction set, which was introduced in 1978 with the
8086/8088 processor. Furthermore it supports the multimedia extension MMX, SSE2, SSE3
and SSE4.
Dual core technology
Two processor cores run with the same frequency in the same processor building block and
share the level 2 cache as well as the front side bus (FSB).
Execute Disable Bit
Prevents security problems through buffer overflows, if the operation system supports it and
if it is activated.
Wide Dynamic Execution
Every core can execute four complete commands simultaneously.
Smart-Memory-Access
Shorter idle times, improved data transfer and faster out-of-order command execution lead to
better usage of the pipeline and as a result to higher performance.
Advanced-Smart-Cache
Like the Core Duo, the Core 2 Duo has shared level 2 cache and each core receives the same
amount of cache. Intel doubled the bandwidth to the level 1 cache though.
Advanced-Digital-Media-Boost
One 128-Bit SSE command is now output per clock cycle.
Virtualisation technology (VT)
The Intel VT offers hardware support for virtual systems on one computer (use of several
isolated operation systems at the same time e.g. through Xen or VMWare)
64 bit support
Support of 64 bit wide words in the CPU. This means the processor can handle 64 bit data
packets. The Intel Core 2 Duo supports the AMD64 extension (licensed), through which 32
and 64 bit programs can run on the CPU (if a 64 bit operation system is used).
Theoretically, a 64 bit processor can access more than 4 GB of memory, but this is usually
limited by the chip set used.
Energy saving functions

Like with the previous version, the clock rate and voltage can be set dynamically and
individually for each core (Speedstep). Under light load the processor can save energy
by lowering the clock speed (to 1200 MHz respectively 800 MHz with the Santa Rosa) and
the core voltage (from 1.3 Volt to 1.0375 Volt). This happens with virtually no performance
losses, thanks to the automatic adjustment of the clock speed. Additionally, the processor
can turn off parts of the CPU which are not used, to save energy.
Intel Dynamic Power Coordination
Coordinates the Enhanced Intel SpeedStep technology and the Idle Power-Management State
(C-state) transitions independent of the core.
Enhanced Intel Deeper Sleep with Dynamic Cache Sizing
Writes data from the cache to the main memory during inactivity. As a result, the CPU
voltage can be lowered which saves energy.
Intel Dynamic Bus Parking
Allows the chip set to shut down during inactivity to save energy.
Advanced Power Gating
Parts of the CPU core can be shut down through "Advanced Power Gating". This can even
happen if performance is required, to improve the performance per watt ratio.
Enhanced Deep C4 Sleep State
The core voltage can be further reduced, if the level 2 cache is turned off.
Split Bus Array
Buses and arrays are separated in order to set them individually into energy saving mode
during certain operation states.

Santa Rosa update

On Mai 9th 2007 the Core 2 Duo processor was upgraded for the 4th Centrino generation
called Santa Rosa. The processor is still based on the Merom core, but some energy saving
functions and optimisations were added. Furthermore, it now needs the socket P with 478
pins, which isn't compatible with the socket M of the older Core 2 Duo.
In contrast with its predecessor, the new Core 2 Duo processors now run with a 800 MHz
FSB (200 MHz quad-pumped) instead of 667 MHz (133 MHz quad-pumped).
The FSB now supports "Dynamic front side bus switching", whereas the FSB can be
lowered from 200 MHz to 100 MHz under light processor load, to save energy. This drop
only affects the chipset and CPU and is thus called "virtual". With speedstep, the Core 2 Duo
can slow down to a minimum of 1.2 GHz. Thanks to the lower (virtual) FSB, the "Santa
Rosa" Core 2 Duo can drop even more, to 800 MHz, to save even more energy.

Another new feature is the dynamically overclocking of the core, called "Dynamic
Acceleration". If only one core is used, it can be dynamically overclocked, while the second
core stays in the energy saving C3-modus. Therefore the overclocked core can work with the
clock speed of the next higher model (e.g. 2.2 instead of 2.0 GHz with the T7300), without
any change in the TDP (thermal design power) and without the need for more cooling.
If idle, the processor will start one of the various saving modes (C1 to C4/DC4). The chipset
of the Santa Rosa keeps the processor as long as possible in energy saving mode (e.g. by
preventing memory acces)

Penryn Update

In Jannuary 2008 Intel introduced the new T9xxx and T8xxx Core 2 Duo processors of the
new "Penryn" core. These CPUs are produced in 45nm (instead of the 65nm before) and offer
a bigger Level 2 Cache (3 and 6 MB versus 2 and 4 before). Furthermore, the Penryn core has
a faster division engine and 47 new SSE instructions (SSE4). Due to the 45 nm process, Intel
was able to increase the core speed without increasing the current consumption.
Compared to a similar clocked Merom Core 2 Duo, the Penryn is on average between 5-10%
faster. The speed increase is mostly because of the bigger L2 Cache. Detailled benchmarks of
the new Penryn CPUs can be found in our Intel Core 2 Duo Penryn review.

Downward compatibility

The Core 2 Duo prior to the introduction of Santa Rosa is, like its predecessor, still based on
the PGA socket-M interface. It is thus possible, to upgrade some notebooks from Core Duo
to Core 2 Duo. However, a Bios which supports the Core 2 Duo is necessary and the
processor must not be soldered to the Mainboard (which is the case with the BGA - ball grid
array - case).
INTEL CORE I7-3920XM 3RD GENERATION PROCESSOR

The intel core i7-3920XM is an appreciable 3rd generation processor with 4 cores and 8
threads. It comes with advanced features and this extreme edition gives maximum turbo
frequency of 3.8GHz. Let us first have a precise comparison of intel’s Core i7, core i5 and
core i3 processors.

This quad-core third generation processor is based on the latest ivy bridge architecture. The
advanced Hyper-threading technology helps in the maximum utilization of CPU. Each of the
CPU core can offer clock speed up to 3.6GHz. Overclocking is made easy with the help of an
unlocked multiplicator.

What is Ivy Bridge Architecture?

The Ivy Bridge marks the start of tri-gate transistors and the 22-nm die shrink of the previous
architecture (Sandy Bridge) offers optimum performance. A change from 32nm to 22nm is
highly beneficial in term of efficiency and power consumption. The 3920XM processor is a
mobile processor with this architecture.
Intel Core i7-3920XM Processor Specs
The specifications can be outlined as:
 Intel Smart Cache – 8 MB,Clock Speed – 2.9 GHz
 Instruction Set – 64-bit
 Lithography – 22 nm
 Max Memory Size – 32 GB (dependent on memory type)
 Graphics Max Dynamic Frequency – 1.3 GHz
 Graphics Base Frequency – 650 MHz
 Processor Graphics – Intel HD Graphics 4000
 Memory Types – DDR3/L/-RS 1333/1600
 Max Memory Bandwidth – 25.6 GB/s
 Memory Channels – 2
Advanced Technologies:
 Intel Turbo Boost Technology – 2.0
 Intel Virtualization Technology (VT-x)
 Intel Hyper-Threading Technology
 Intel Trusted Execution Technology
 Intel® Anti-Theft Technology
 4G WiMAX Wireless Technology

APPLICATION

 TRAFFIC LIGHT CONTROLLER USING 8086 MICROPROCESSOR

Traffic light controller interface module is designed to simulate the function of four way
traffic light controller.
Combinations of red, amber and green LED’s are provided to indicate Halt, Wait and Go
signals for vehicles.
Combination of red and green LED’s are provided for pedestrian crossing. 36 LED’s are
arranged in the form of an intersection.
A typical junction is represented on the PCB with comprehensive legend printing.
At the left corner of each road, a group of five LED’s (red, amber and 3 green) are arranged
in the form of a T-section to control the traffic of that road.
Each road is named North (N), South(S), East (E) and West (W). LED’s L1, L10, L19 & L28
(Red) are for the stop signal for the vehicles on the road N, S, W, & E respectively.

L2, L11, L20 & L29 (Amber) indicates wait state for vehicles on the road N, S, W, & E
respectively. L3, L4 & L5 (Green) are for left, strait and right turn for the vehicles on road S.
similarly L12-L13-L14, L23-L22-L21 & L32-L31-L30 simulates same function for the roads
E, N, W respectively.
A total of 16 LED’s (2 Red & 2 Green at each road) are provided for pedestrian crossing.

L7-L9.L16-L18, L25-L27 & L34-L36 (Green) when on allows pedestrians to cross and L6-
L8, L15-L17, L24-L26 & L33-L35 (Red) when on alarms the pedestrians to wait.

To minimize the hardware pedestrian’s indicator LED’s (both red and green are
connected to same port lines (PC4 to PC7) with red inverted.
Red LED’s L10 & L28 are connected to port lines PC2 & PC3 while L1 & L19
are connected to lines PC0 & PC1 after inversion. All other LED’s (amber and green) are
connected to port A & B.

 Working:- 8255 is interfaced with 8086 in I/O mapped I/O and all ports
are
output ports. The basic operation of the interface is explained with the help of the enclosed
program. The enclosed program assumes no entry of vehicles from North to West, from
road East to South.
At the beginning of the program all red LED’s are switch ON, and all other LED‘s are
switched OFF. Amber LED is switched ON before switching over to proceed state from Halt
state.
The sequence of traffic followed in the program is given below.

a) From road north to East From road east to north From road south to west From road
west to south From road west to north

b) From road north to East From road south to west From road south to north From road
south to east From road north to south From road south to north

Pedestrian crossing at roads west & east d) From road east to west

From road west to east

Pedestrian crossing at roads north & south

 GENERATION OF SQUARE WAVE WITH PORTS USING 8051

MICROCONTROLLER

HERE : SETB P1.0 (Make bit of Port 0 High)

LCALL DELAY

CLR P1.0

LCALL DELAY

SJMP HERE : Keep doing it

DELAY:

MOV A,#FF
 L1 DCR A

JNZ LI

RET

 Generation of square wave with Timer using 8051 microcontroller

Square wave of 50% duty on P1.5 Timer 0 is used

MOV TMOD,#01 Timer 0,mode 1(16-bit)

HERE: MOV TL0,#0F2H Timer value = FFF2H

MOV TH0,#0FFH

CPL P1.5

ACALL DELAY

SJMP HERE

DELAY:

SETB TR0 start the timer 0

AGAIN: JNB TF0,AGAIN

CLR TR0 stop timer 0

CLR TF0 clear timer 0 flag

 RET

 WASHING MACHINE CONTROL INTERFACING WITH 8051

MICRO CONTROLLER

Washing Machine Control

Many washing machine sells in the market has mechanical controlled sequence for
activated the timer and the sequence back and forth for their motor; washing motor or
spinning motor. Spinning motor control only has one direction only, and its simple could be
changed to the discrete mechanical timer which sells on the market. But washing motor
control has 2 direction for this purpose, it means to squeeze the clothes, it must go to forward
and then reversed. The sequence is like this:

ü First, go to forward direction for about a few seconds

ü Than stop, while the chamber is still rotate

ü Second, go back to reverse direction for about a few seconds

ü Than stop, while the chamber is still rotate

ü And so on, back and forth, until the the timer elapsed
Schematic

Timing sequence like the above description, can be implemented with many way, by
using discrete electronic components, timer, using a program or a microcontroller or
microprocessor, etc. Because I am learning the PIC microcontroller for right now, I will
implement this function using this microcontroller, but for you who familiar with another
kind of microcontroller my adapted it to your purpose. By using PIC micro, it can be made
more compact. First I plan to make 2 buttons, 1 for set the timer and another for reset the
timer or for the emergency stop push button. Then to know the timer works or not, I need a
visual display.

For this purpose I will use 7-segmen display showing the rest of the timer. To run the
motor sequence of course I need a pair of relays (power relays, about 3 Amperes output), one
for forward and another for reverse option. I will use the very common family of PIC micro,
ie : 16F84A, because this is the most popular type and very simples used and very much
used. Also can be obtained easily in the market. But this is the medium type of PIC micro
family. It has 1kByte of memory (EEPROM type) and 13 I/O pins. It can be reprogrammable
thousands times. Because the I/O just only 13 pins, I used a BCD to 7-segmen chip. So it will
left a few I/O pins for expanded in the future. You can omitted this chip for timing sequence
purpose and save one IC price, because the I/O just exactly enough.

ü I/O port A-0 = SET push button

ü I/O port A-1 = RST push button

ü I/O port A-2 = Reserved

ü I/O port A-3 = Reserved

ü I/O port A-4 = Reserved

ü I/O port B-0 = Forward Relay (Run motor forward)

ü I/O port B-1 = Reverse Relay (Run motor reverse)

ü I/O port B-2 = Activated unit 7-segmen (multiplexed)

ü I/O port B-3 = Activated ten 7-segmen (multiplexed)

 ü I/O port B-4 = BCD data A (for 7-segmen)

ü I/O port B-5 = BCD data B (for 7-segmen)

ü I/O port B-6 = BCD data C (for 7-segmen)

ü I/O port B-7 = BCD data D (for 7-segmen)

ü Also integrated power supply to run it modularly

The I/O can be configured as input pin or output pin bit-ly. It is up to you to choose
the I/O pin number goes to what function, but it infect the program firmware of course. Once
you choose, then it is just like that, except you also change both, the program and the
hardware.

Working of Washing Machine

The direction of rotation can be controlled when switchS1 is in position A, coil L1 of

the motor receives the current directly, whereas coil L2 receives the current with a phase shift
due to capacitor C. So the rotor rotates in clockwise direction (see Fig. 2(a)). When switch S1
is in position B, the reverse happens and the rotor rotates in anti-clock wise direction Thus
switch S1 can change the rotation direction. The motor cannot be reversed instantly. It needs
a brief pause between switching directions, or else it may get damaged. For this purpose,
another spin direction control timer (IC2) is employed. It is realised with an IC 555. This
timer gives an alternate „on‟ and „off‟ time duration of 10 seconds and 3 seconds,
respectively. So after every l0 seconds of running (either in clockwise or anti clockwise
direction), the motor stops for a brief duration of 3 seconds. The values of R3 and R4 are
calculated accordingly. The master timer is realised with monostable IC555 (IC1) and its
„on‟ time is decided by the resistance of 1-mega- ohm potmeter VR. A 47-kilo-ohm resistor
is added in series so that even when the VR knob is in zero resistance position, the net series
resistance is not zero
POST TEST
1) Which flag is set to 1 when the result of arithmetic or logical operation is zero else it is set
to 0?

a) Binary bit c) Zero flag c) Sign flag d) Overflow flag

ans b

2)The intel 8086 microprocessor is a

a) 8bit processorb) 16 bitprocessor c) 32 bitprocessor d) 4 bitprocessor

and b

3) In 8086 microprocessor, the address bus is

a) 12 bit b) 10 bit c) 16 bit d) 20 bit

ans d

4) Which is not the control bus signal

a) read b) write c)reset d) none of these

b) ans a

5) BIU stands for

a) bus interface unit b) bus indicate unit c) busy interface unit d) none of these

ans a

6)8051 series has how many 16 bit registers?

a) 2 b) 3 c) 1 d) 0

Ans a

7)What is the bit size of the 8051 microcontroller?

a) 8-bit b) 4-bit c) 16-bit d) 32-bit

Ans a

8)Number of I/O ports in the 8051 microcontroller?

a) 3 ports
b) 4 ports
c) 5 ports
d) 4 ports with last port having 5 pins

Ans b

9)SCON in serial port is used for which operation?

a) Transferring data
b) Receiving data
c) Controlling
d) Controlling and transferring

Ans c

10) Program counter stores what?

a) Address of before instruction
b) Address of the next instruction
c) Data of the before execution to be executed
d) Data of the execution instruction

Ans b

11)External Access is used to permit ____________

a) Peripherals
b) Power supply
c) ALE
d) Memory interfacing
Ans d

12) What is the address range of SFRs?

a) 80h to feh
b) 00h to ffh
c) 80h to ffh
d) 70h to 80h

Ans c

13)How many interrupts are there in micro controller?

a) 3
b) 6
c) 4
d) 5

Ans d

14)Timer 0 is a ________ bit register.

a) 32-bit
b) 8-bit
c) 16-bit
d) 10-bit

Ans c

15) Number of pins in 8051 microcontroller with ________ package.

a) 40 pin with LLC
b) 60 Pin with QFP
c) 40 pin with DIP
d) 60 pin with QFP

Ans c

16)How are the status of the carry, auxiliary carry and parity flag affected if the write
instruction
MOV A,#9C
ADD A,#64H
a) CY=0,AC=0,P=0 b) CY=1,AC=1,P=0 c) CY=0,AC=1,P=0 d) CY=1,AC=1,P=1

Ans b

17)Find the number of times the following loop will be executed

MOV R6,#200
BACK:MOV R5,#100
HERE:DJNZ R5, HERE
DJNZ R6,BACK
END
a) 100b) 200c) 20000 d) 2000
Ans c

18) Which of the following comes under the indexed addressing mode?
a) MOVX A, @DPTRb) MOVC @A+DPTR,Ac) MOV A,R0
d) MOV @R0,A

Ans b

19) XRL, ORL, ANL commands have

a) accumulator as the destination address and any register, memory or any immediate
data as the source address
b) accumulator as the destination address and any immediate data as the source
address
c) any register as the destination address and accumulator, memory or any immediate
data as the source address
d) any register as the destination address and any immediate data as the source
address

Ans a

20)Which of the following instruction perform as of indirect RAM to accumulator?

a) MOV A, Rn b) MOV @Ri, A c) MOV A, @Ri d) MOV Rn, A

Ans c

21)In 8279,the keyboard entries are debounced and stored in an

a) 8 bit FIFO b) 8 byte FIFO c) 16 byte FIFO d) 16 bit FIFO

Ans b

22)Intel 8279 is a

a) Programmable interrupt controller b)programmable keyboard/display interface

b) Programmable peripheral interface d) programmable interval timer
Ans b

23)8251 is a
 a)UART b)USART c) programmable peripheral interface d) ADC interface
ans b

24) The main importance of ARM micro-processors is providing operation with

a) Low cost and low power consumption b) Higher degree of multi-tasking
c) Lower error or glitches d) Efficient memory management

Ans a

25) Which operational feature of PIC allows it to reset especially when the power supply
drops the voltage below 4V?
a. Built-in Power-on-reset b. Brown-out reset c. Both a & bd. None of the above
ans b

CONCLUSION
 Thus the difference between microprocessor and microcontroller has been discussed.
 Given` an understanding about the concepts, basic architecture,pin configuration,
special function register and application of 8086 microprocessor and 8051
microcontroller.
 Need of interfacing devices with microprocessor and microcontroller was discussed
 Given an overview about advanced microcontroller.

REFERENCE
1. Kenneth [Link], “The 8051 microcontroller Architecture, Programming and
applications” ,Third edition,Cengage Learning India pvt ltd,2009.
2. [Link],”The 8051 microcontroller” ,CengageNarosa Publication HousePvt.
Ltd, 1st Edition 2011.
3. Mohamed Ali Mazidi,JaniceGillispieMazidi,” The 8051 microcontroller and
embedded systems using Assembly and C”,second edition, Pearson education
/Prentice hall of India, 2007.
4. Amar [Link],”AnuvaGanguly,Microprocessor and Microcontroller 8085,8086 and
8051”,Narosa Publication HousePvt. Ltd,2012.
5. Douglas [Link], “ Microprocessors and Interfacing : Programming and Hardware”,
Tata McGraw Hill ,3rd Edition July 2017.
 6. [Link]& K.M Bhurchandi, “Advanced Microprocessor and Peripherals –
Architecture, Programming and Interfacing”, Tata McGrawHill , 2006.
7. [Link],[Link] “Advanced Microprocessor and Pheripherals”,Tata
McGraw Hill ,3rd Edition 2012.

ASSIGNMENTS
1. Write the assembly language program in 8086 microprocessor for given information
Take two data from memory space, find 1’s complement for that data and store them
in memory space.

2. Identify the following instruction belong to which addressing modes and explain it.

NOP
HLT
MOV BL,84
MOV CH,CL

3. Explain briefly about these instruction given below, assume data wherever necessary

MOV DX,[8234]
MOV CX,3456
ADD DX,[9234]
OR AL,56
CMC

4. Describe briefly about architecture of 8051 microcontroller.

5. Explain the pin configuration of 8051 microcontroller.
6. Explain how to generate square wave form using timer.
7. Describe briefly about special function register.
8. Write the assembly language program in 8051 microcontroller for given information
Take two data from internal RAM memory, find OR operation between them and
result what we are getting should exchange 4bit among themselves.

9. Explain the following instruction

MOV @Ri,A
ADD A,32
 RRC A
JNZ rel
RET

10. Explain how to generate square wave form using timer.