NPTEL Online Certification Courses
Indian Institute of Technology Kharagpur
Course Name: VLSI PHYSICAL DESIGN
Assignment- Week 1
TYPE OF QUESTION: MCQ/MSQ/SA
Number of questions: 10 Total Marks: 10
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QUESTION 1:
Which of the following statement(s) is/are true?
a. Behavioral design specifies netlist of gates.
b. Logic design specifies a netlist of gates/flip flops.
c. Physical design specifies a netlist of register transfer level components.
d. Data path design specifies a netlist of register transfer level components.
Correct Answer: b, d
Detail Solution: Behavioral design specifies the functionality of the chip, data path design
generates a netlist of register transfer level components, logic design generates a netlist of
gates/flip-flops or standard cells, and physical design generates final layout.
Hence options (b) and (d) are correct.
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QUESTION 2:
Which of the following does not represent the behavioral description of a function?
a. Truth table representing a combinational function.
b. Sum-of-the-product representation of a function.
c. A gate-level netlist representation of a function.
d. A function represented by Boolean equations.
Correct Answer: c
Detail Solution: Behavioral description of a function cannot be represented as a gate level
netlist, rest of the options are true for behavioral description.
Hence option (c) is correct.
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Indian Institute of Technology Kharagpur
QUESTION 3:
Which of the following statement(s) is/are true?
a. Logic design is part of front-end CAD.
b. Partitioning comes after floorplanning.
c. Placement and Routing comes under back-end CAD.
d. Placement comes after partitioning.
Correct Answer: a, c, d
Detail Solution: Logic design and synthesis are parts of front-end CAD. Partitioning,
floorplanning, placement and routing all are parts of back-end CAD. In back-end design,
floorplanning and placement comes after partitioning.
Hence options (a), (c) and (d) are correct.
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QUESTION 4:
Which of the following functions cannot be realized by a single 4-input LUT in a typical
FPGA?
a. F = A’.B.C + B.C’
b. F = A.D’ + B’.C’ + A’E
c. F = A.B + C
d. F = B’C’D’ + ABC + CD
Correct Answer: b
Detail Solution: Any function with four or less number of variables can be realized using a
4-input LUT. Only option (b) is a five-variable function, all other options are either 4-
variable or less.
Hence option (b) is correct.
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QUESTION 5:
Which of the following is/are true for gate array design style?
a. The cell size if variable.
b. The cell placement is fixed.
c. Design time is faster than standard cell and full custom design.
NPTEL Online Certification Courses
Indian Institute of Technology Kharagpur
d. Cell type is programmable.
Correct Answer: b, c
Detail Solution: In gate array design style, cell size, cell type and cell placement are fixed
and cannot be changed. Also design time of gate array is faster than standard cell and full
custom design, but slower than FPGA.
Hence, correct options are (b) and (c).
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QUESTION 6:
Which of the following is/are false for floorplanning?
a. Determines rough positions of each of the circuit blocks.
b. Determines shapes of the blocks that are flexible.
c. Floorplanning is not a mandatory step for full custom design style.
d. Determines the pin-location of the blocks.
Correct Answer: c
Detail Solution: All options are true for floorplanning except (c). Floorplanning is a
mandatory step for full-custom design style.
Hence correct option is (c).
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QUESTION 7:
Which of the following is/are true for placement?
a. Placement determines the position of the blocks in the final layout.
b. Placement considers keeping adequate space between blocks for routing.
c. Interconnection modeling is not important in placement.
d. For FPGA floorplanning and placement are similar.
Correct Answer: a, b, d
Detail Solution: All options are correct except (c). Interconnection modeling is very
important while performing placement.
Hence options (a), (b) and (d) are correct.
______________________________________________________________________________
NPTEL Online Certification Courses
Indian Institute of Technology Kharagpur
QUESTION 8:
Which of the following is/are false for static timing analysis?
a. A given circuit netlist is analyzed to estimate worst-case signal delays.
b. We can estimate the maximum clock frequency with which a circuit can run
correctly.
c. Does not allow us to carry out timing optimizations to improve the circuit
speed.
d. An essential step in modern day high performance system.
Correct Answer: c
Detail Solution: All options are true for static timing analysis except (c). It does allow us to
carry out timing optimizations to improve the circuit speed.
Hence option (c) is correct.
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QUESTION 9:
Which of the following statements is/are true?
a. Clock routing must consider issues like delays, skews and hazards.
b. Clock signal may or may not reach various parts of the chip at the same time.
c. Power requirement is same for all parts of the chip.
d. The Vdd and GND lines must have adequate widths to carry the required
currents.
Correct Answer: a, d
Detail Solution: Options (a) and (d) are true. Clock signals must reach various parts of the
chip at the same time to avoid clock skew. The Vdd and GND lines must have adequate
widths to carry the required currents.
Hence options (a) and (d) are correct.
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QUESTION 10:
For the function F = A.B’ + C.D’, which of the following represents the correct bit pattern to
be loaded into a 4-input LUT to realize the function?
a. 0010 1010 1111 0010
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Indian Institute of Technology Kharagpur
b. 0010 0010 1111 0010
c. 0001 0010 0111 0010
d. 0001 1010 1111 0010
Correct Answer: b
Detailed Solution: The truth table of the function is shown below:
A B C D F
==========
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0
The bit pattern to be loaded into the LUT will be that corresponding to the output column
of the truth table, which corresponds to option (b).
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