1 mark COA
1.a) What is a register transfer language?
Answer (Outside Source): Register Transfer Language (RTL) is a symbolic
notation used to describe the micro-operation transfers between registers in a
computer system.
1.b) Define computer registers.
Answer (Outside Source): Computer registers are high-speed, small-capacity
storage units located directly inside the CPU used to hold temporary data,
instructions, and addresses during processing.
1.c) What is Micro-programmed control Unit?
Answer (Outside Source): A micro-programmed control unit is a control unit
where the control signals are generated by executing a sequence of micro-
instructions stored in a control memory, rather than by hardwired logic gates.
1.d) List any two types of logical and bit manipulation instructions.
Answer (Outside Source): Two common types are:
1. Logical Operations: AND, OR, XOR.
2. Shift/Rotate Operations: Logical Shift, Arithmetic Shift, Rotate Left/Right.
1.e) What is the purpose of data representation in computers?
Answer (Outside Source): The purpose is to translate various forms of
human-readable information (such as numbers, text, images, and sound) into
a binary format (0s and 1s) that the computer hardware can physically store,
process, and transmit.
1.f) Give an example of a real-world application that heavily relies on floating-
point arithmetic.
Answer (Outside Source): Scientific simulations, such as weather forecasting
or molecular modeling, rely heavily on floating-point arithmetic to handle very
large or very small numbers with high precision.
1.g) What is the purpose of data types in computer programming?
1 mark COA 1
Answer (Outside Source): Data types define the nature of the data (e.g.,
integer, character, float) to inform the compiler or processor how much
memory to allocate and which operations can validly be performed on that
data.
1.h) Why is cache memory faster than main memory?
Answer (Outside Source): Cache memory is faster because it uses high-
speed SRAM (Static RAM) technology compared to the slower DRAM used in
main memory, and it is physically located closer to (or on) the CPU chip to
minimize access latency.
1.i) List the key features of an array processor.
Answer (Outside Source): Key features include the ability to perform
computations on large arrays of data simultaneously (SIMD - Single
Instruction, Multiple Data), the use of multiple functional units or processing
elements, and optimization for vector arithmetic.
1.j) Define the term “RISC”.
Answer (Outside Source): RISC stands for Reduced Instruction Set
Computer. It is a CPU design strategy based on the insight that a simplified
instruction set (where instructions take one cycle to execute) can provide
higher performance and efficiency than a complex set of instructions.
1(a) What is an instruction cycle?
It is the sequence of steps (fetch, decode, execute) used by the CPU to execute
one instruction.
1(b) Draw block diagram of digital computer.
Input → CPU (ALU + CU + Registers) → Output
↑
Memory
1(c) What is an effective address?
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The actual memory address of the operand after addressing-mode calculation.
1(d) Write a micro program to illustrate ADD operation.
T1: DR ← M[R1]
T2: AC ← DR + M[R2]
T3: R1 ← AC
1(e) Convert the following decimal numbers into hexadecimal.
i) (328)₁₀ = 148₁₆
ii) (2039)₁₀ = 7F7₁₆
1(f) How can you perform subtraction of two binary numbers
using 2’s complement?
Take the 2’s complement of the subtrahend and add it to the minuend; discard
final carry.
1(g) Distinguish between isolated and memory mapped I/O.
Isolated I/O: Separate I/O address space; uses IN/OUT instructions.
Memory-mapped I/O: Devices share memory space; accessed using normal
load/store.
1(h) What is IBM 370 I/O Channel? Explain.
A dedicated processor that handles I/O operations independently of the CPU.
1(i) What are CISC characteristics?
Large instruction set, many addressing modes, complex instructions,
microprogrammed control.
1(j) Explain RISC pipeline process.
1 mark COA 3
RISC uses a 5-stage pipeline (IF, ID, EX, MEM, WB) to execute multiple instructions
in parallel.
1 mark COA 4