CHAPTER 2: BASIC ARCHITECTURE OF THE 8088 AND 8086

MICROPROCESSORS
2.1 Internal architecture of the 8086/8088 microprocessors
The programming model of the 8086 through the Core2 is considered to be program visible
because its registers are used during application programming and are specified by the
instructions. Other registers, detailed later in this chapter, are considered to be program
invisible because they are not addressable directly during applications programming, but may
be used indirectly during system programming.

Architecture of 8086 microprocessor:

 As shown in the below figure, the 8086 CPU is divided into two independent functional parts
o Bus Interface Unit (BIU)
o Execution Unit (EU)
 Dividing the work between these two units’ speeds up processing.

The Execution Unit (EU):

The execution unit of the 8086 tells the BIU where to fetch instructions or data from, decodes
instructions, and executes instructions.
 The EU contains control circuitry, which directs internal operations.
 A decoder in the EU translates instructions fetched from memory into a series of actions,
which the EU carries out.
 The EU has a 16-bit arithmetic logic unit (ALU) which can add, subtract, AND, OR, XOR,
increment, decrement, complement or shift binary numbers.
 The main functions of EU are:
o Decoding of Instructions
o Execution of instructions
Steps
 EU extracts instructions from top of queue in BIU
 Decode the instructions
 Generates operands if necessary
 Passes operands to BIU & requests it to perform read or write bus cycles to memory or I/O
 Perform the operation specified by the instruction on operands

Bus Interface Unit (BIU):

 The BIU sends out addresses, fetches instructions from memory, reads data from ports and
memory, and writes data to ports and memory.
In simple words, the BIU handles all transfers of data and addresses on the buses for the
execution unit.
8086 HAS PIPELINING ARCHITECTURE:
 While the EU is decoding an instruction or executing an instruction, which does not require
use of the buses, the BIU fetches up to six instruction bytes for the following instructions.
 The BIU stores these pre-fetched bytes in a first-in-first-out register set called a queue.
 When the EU is ready for its next instruction from the queue in the BIU. This is much faster
than sending out an address to the system memory and waiting for memory to send back the
next instruction byte or bytes.
 Except in the case of JMP and CALL instructions, where the queue must be dumped and then
reloaded starting from a new address, this pre-fetch and queue scheme greatly speeds up
processing.
 Fetching the next instruction while the current instruction executes is called pipelining

Pin diagram
Power supply and frequency signals: It uses 5V DC supply at VCC pin 40, and uses ground at
VSS pin 1 and 20 for its operation.
Clock signal: Clock signal is provided through Pin-19. It provides timing to the processor for
operations. Its frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.
Address/data bus: AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order
byte data and AD8AD15 carries higher order byte data. During the first clock cycle, it carries
16-bit address and after that it carries 16-bit data.
Address/status bus: A16-A19/S3-S6. These are the 4 address/status buses. During the first
clock cycle, it carries 4-bit address and later it carries status signals.
S7/BHE: BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the
transfer of data using data bus D8-D15. This signal is low during the first clock cycle, thereafter
it is active.
Read (RD): It is available at pin 32 and is used to read signal for Read operation.
Ready: It is available at pin 22. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready to
transfer data. When it is low, it indicates wait state.
RESET: It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock cycles
to RESET the microprocessor.
INTR: It is available at pin 18. It is an interrupt request signal, which is sampled during the last
clock cycle of each instruction to determine if the processor considered this as an interrupt or
not.
NMI: It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered
input, which causes an interrupt request to the microprocessor.
TEST: This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.
MN/MX: It stands for Minimum/Maximum and is available at pin 33. It indicates what mode
the processor is to operate in; when it is high, it works in the minimum mode and vice-versa.
INTA: It is an interrupt acknowledgement signal and id available at pin 24. When the
microprocessor receives this signal, it acknowledges the interrupt.
ALE: It stands for address enable latch and is available at pin 25. A positive pulse is generated
each time the processor begins any operation. This signal indicates the availability of a valid
address on the address/data lines.
DEN: It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver
8286. The transreceiver is a device used to separate data from the address/data bus.
DT/R: It stands for Data Transmit/Receive signal and is available at pin 27. It decides the
direction of data flow through the transreceiver. When it is high, data is transmitted out and
vice-a-versa.
M/IO: This signal is used to distinguish between memory and I/O operations. When it is high,
it indicates I/O operation and when it is low indicates the memory operation. It is available at
pin 28.
WR: It stands for write signal and is available at pin 29. It is used to write the data into the
memory or the output device depending on the status of M/IO signal.
HLDA: It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.
 HOLD: This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.
QS1 and QS0: These are queue status signals and are available at pin 24 and 25. These signals
provide the status of instruction queue. Their conditions are shown in the following table −
QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

S0, S1, S2: These are the status signals that provide the status of operation, which is used by the
Bus Controller 8288 to generate memory & I/O control signals. These are available at pin 26,
27, and 28. Following is the table showing their status
S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive
LOCK: When this signal is active, it indicates to the other processors not to ask the CPU to
leave the system bus. It is activated using the LOCK prefix on any instruction and is available
at pin 29.
RQ/GT1 and RQ/GT0: These are the Request/Grant signals used by the other processors
requesting the CPU to release the system bus. When the signal is received by CPU, then it
sends acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.
2.2 Memory address space and data organization
Memory Segmentation:
 The memory in an 8086 based system is organized as segmented memory.
 The CPU 8086 is able to access 1MB of physical memory. The complete 1MB of memory
can be divided into 16 segments, each of 64KB size and is addressed by one of the segment
registers.
  The 16-bit contents of the segment register actually point to the starting location of a
particular segment. The address of the segments may be assigned as 0000H to F000h
respectively.
 To address a specific memory location within a segment, we need an offset address. The
offset address values are from 0000H to FFFFH so that the physical addresses range from
00000H to FFFFFH
Physical address = Segment address * 10H + Offset address
Physical address is calculated as below:
Ex: Segment address ------- 1005H
Offset address ---------- 5555H
Physical address -------155A5H
The main advantages of the segmented memory scheme are as follows:
1. Allows the memory capacity to be 1MB although the actual addresses to be handled are of 16-
bit size.
2. Allows the placing of code, data and stack portions of the same program in different parts
(segments) of memory, for data and code protection.
3. Permits a program and/or its data to be put into different areas of memory each time the
program is executed, i.e., provision for relocation is done.

2.3 Data types

In 8086 assembly, data can be allocated (or defined) using the following directives:
DB (Define Byte) Allocates 1-byte
DW (Define Word) Allocates 2-bytes
DD (Define Double word) Allocates 4-bytes
DQ (Define Quad Word) Allocates 8-bytes
The general format of data allocation is
Examples:
Var1 DB 0AH
Var2 DB 1BH, 20H, 34H
DW 01ACH
Directive Purpose Storage Space

DB Define Byte allocates 1 byte

DW Define Word allocates 2 bytes

DD Define Doubleword allocates 4 bytes

DQ Define Quadword allocates 8 bytes

DT Define Ten Bytes allocates 10 bytes

Registers
Processor operations mostly involve processing data. This data can be stored in memory and accessed
from thereon. However, reading data from and storing data into memory slows down the processor, as it
involves complicated processes of sending the data request across the control bus and into the memory
storage unit and getting the data through the same channel.

To speed up the processor operations, the processor includes some internal memory storage locations,
called registers.

The registers store data elements for processing without having to access the memory. A limited number
of registers are built into the processor chip.

Processor Registers

There are ten 32-bit and six 16-bit processor registers in IA-32 architecture. The registers are grouped into
three categories −

• General registers,
• Control registers, and
• Segment registers.
The general registers are further divided into the following groups −

• Data registers,
• Pointer registers, and
• Index registers.

Data Registers

Four 32-bit data registers are used for arithmetic, logical, and other operations. These 32-bit registers can
be used in three ways −

• As complete 32-bit data registers: EAX, EBX, ECX, EDX.

• Lower halves of the 32-bit registers can be used as four 16-bit data registers: AX, BX, CX and
DX.
• Lower and higher halves of the above-mentioned four 16-bit registers can be used as eight 8-bit
data registers: AH, AL, BH, BL, CH, CL, DH, and DL.
Some of these data registers have specific use in arithmetical operations.

AX is the primary accumulator; it is used in input/output and most arithmetic instructions. For example,
in multiplication operation, one operand is stored in EAX or AX or AL register according to the size of
the operand.

BX is known as the base register, as it could be used in indexed addressing.

CX is known as the count register, as the ECX, CX registers store the loop count in iterative operations.

DX is known as the data register. It is also used in input/output operations. It is also used with AX
register along with DX for multiply and divide operations involving large values.

Pointer Registers

The pointer registers are 32-bit EIP, ESP, and EBP registers and corresponding 16-bit right portions IP,
SP, and BP. There are three categories of pointer registers −

• Instruction Pointer (IP) − The 16-bit IP register stores the offset address of the next instruction
to be executed. IP in association with the CS register (as CS:IP) gives the complete address of the
current instruction in the code segment.
• Stack Pointer (SP) − The 16-bit SP register provides the offset value within the program stack.
SP in association with the SS register (SS:SP) refers to be current position of data or address
within the program stack.
• Base Pointer (BP) − The 16-bit BP register mainly helps in referencing the parameter variables
passed to a subroutine. The address in SS register is combined with the offset in BP to get the
location of the parameter. BP can also be combined with DI and SI as base register for special
addressing.
Index Registers

The 32-bit index registers, ESI and EDI, and their 16-bit rightmost portions. SI and DI, are used for
indexed addressing and sometimes used in addition and subtraction. There are two sets of index pointers.

• Source Index (SI) − It is used as source index for string operations.

• Destination Index (DI) − It is used as destination index for string operations.

Control Registers

The 32-bit instruction pointer register and the 32-bit flags register combined are considered as the control
registers.

Many instructions involve comparisons and mathematical calculations and change the status of the flags
and some other conditional instructions test the value of these status flags to take the control flow to other
location.

The common flag bits are:

• Overflow Flag (OF) − It indicates the overflow of a high-order bit (leftmost bit) of data after a
signed arithmetic operation.
• Direction Flag (DF) − It determines left or right direction for moving or comparing string data.
When the DF value is 0, the string operation takes left-to-right direction and when the value is set
to 1, the string operation takes right-to-left direction.
• Interrupt Flag (IF) − It determines whether the external interrupts like keyboard entry, etc., are
to be ignored or processed. It disables the external interrupt when the value is 0 and enables
interrupts when set to 1.
• Trap Flag (TF) − It allows setting the operation of the processor in single-step mode. The
DEBUG program we used sets the trap flag, so we could step through the execution one
instruction at a time.
• Sign Flag (SF) − It shows the sign of the result of an arithmetic operation. This flag is set
according to the sign of a data item following the arithmetic operation. The sign is indicated by
the high-order of leftmost bit. A positive result clears the value of SF to 0 and negative result sets
it to 1.
• Zero Flag (ZF) − It indicates the result of an arithmetic or comparison operation. A nonzero
result clears the zero flag to 0, and a zero result sets it to 1.
 • Auxiliary Carry Flag (AF) − It contains the carry from bit 3 to bit 4 following an arithmetic
operation; used for specialized arithmetic. The AF is set when a 1-byte arithmetic operation
causes a carry from bit 3 into bit 4.
• Parity Flag (PF) − It indicates the total number of 1-bits in the result obtained from an arithmetic
operation. An even number of 1-bits clears the parity flag to 0 and an odd number of 1-bits sets
the parity flag to 1.
• Carry Flag (CF) − It contains the carry of 0 or 1 from a high-order bit (leftmost) after an
arithmetic operation. It also stores the contents of last bit of a shift or rotate operation.

Segment Registers

Segments are specific areas defined in a program for containing data, code and stack. There are three
main segments −

• Code Segment − It contains all the instructions to be executed. A 16-bit Code Segment register
or CS register stores the starting address of the code segment.
• Data Segment − It contains data, constants and work areas. A 16-bit Data Segment register or
DS register stores the starting address of the data segment.
• Stack Segment − It contains data and return addresses of procedures or subroutines. It is
implemented as a 'stack' data structure. The Stack Segment register or SS register stores the
starting address of the stack.
Apart from the DS, CS and SS registers, there are other extra segment registers - ES (extra segment), FS
and GS, which provide additional segments for storing data.

In assembly programming, a program needs to access the memory locations. All memory locations within
a segment are relative to the starting address of the segment. A segment begins in an address evenly
divisible by 16 or hexadecimal 10. So, the rightmost hex digit in all such memory addresses is 0, which is
not generally stored in the segment registers.

The segment registers store the starting addresses of a segment. To get the exact location of data or
instruction within a segment, an offset value (or displacement) is required. To reference any memory
location in a segment, the processor combines the segment address in the segment register with the offset
value of the location.