Synchronous FIFO

The document outlines a technical presentation on the design and implementation of a synchronous FIFO using FPGA, focusing on its functionality as a data storage structure that maintains the order of data flow. It includes sections on background motivation, problem statement, design methodology, literature survey, and the tools and hardware used for the project. The goal is to create an 8-bit, 16-depth synchronous FIFO that ensures correct data order with appropriate signaling.

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Synchronous FIFO

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vaishup0510

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Download as PDF, TXT or read online on Scribd

Government College of Engineering, Karad

(An Autonomous Institute of Government of Maharashtra)

Department of Electronics and Telecommunication

Third Year [Link]. [Summer-2022]

EX2611: Technical Presentation [ REVIEW ]

Title: DESIGN & IMPLEMENTATION OF SYNCHRONOUS FIFO

USINF FPGA

Name of Guide: Student Name [[Link].]

Prof. Utkarsha Gharge Sanika Sambhaji Jadhav [23151044]

Vaishnavi Prakash Patil[23151052]
• CONTENT
1. Introduction
2. Background & Motivation
3. Problem Statement & Design Methodology
4. Literature Survey
5. Tools & Hardware Used
6. References
• INTRODUCTION

• FIFO (First In First Out) is a temporary data

storage structure.
• Data is read in the same order in which it is
written.
• Synchronous FIFO uses a single clock for both
read and write operations.
• It is used to manage data flow between digital
modules.
BACKGROUND MOTIVATION
• Digital systems often operate at different • Prevent data loss and overflow.
speeds. • Ensure smooth and reliable data
• Fast modules generate data continuously. transfer.
• Slow modules cannot process data • FIFO provides ordered data storage.
instantly.

FIFO
ADC PROCESSOR ADC PROCESSOR
CIRCUIT
(Fast) (Slow) (Fast) (Slow)
(Storage Element )
PROBLEM STATEMENT
• Design an 8-bit, 16-depth synchronous FIFO.
• Ensure correct data order with Full and Empty signals.

DESIGN METHODOLOGY
VHDL coding Simulation Synthesis

FPGA Hardware
Bitstream Generation Implementation
Testing
• LITERATURE SURVEY
Paper 1-Design and Verification of Synchronous FIFO
Authors Publications Proposed Work Outcomes
Yatheeswar Penta, Riadul Islam arXiv Preprint (2025) This paper presents the design The design was successfully
and verification of a simulated and verified to ensure
synchronous FIFO using RTL correct data transfer without
coding with read/write pointer overflow or underflow
and flag generation logic. conditions.

Paper 2-Simulation and Implementation of Multi-Channel UART Controller Based on FIFO and FPGA
Authors Publications Proposed Work Outcomes
Boorthula Kiran, Md. Shazia International Journal of VLSI This paper presents the design The implementation
Fatima, P. V. N. Swamy System Design and and FPGA implementation of a demonstrates improved data
Communication Systems, Vol. multi-channel UART controller buffering and reliable
03, Issue 04, July 2015 using synchronous FIFO buffers communication using FIFO
for data storage and architecture on FPGA.
synchronization.
• HARDWARE & TOOLS
1. Hardware Used-
• FPGA Development Board
• On-Board Switches
• On-Board LED’S
• USB Cable

2. Software Used-
Xilinx Vivado Design Suite
• REFERENCES
1. B. Kiran, M. S. Fatima and P. V. N. Swamy, “Simulation and Implementation of Multi-Channel UART
Controller Based on FIFO and FPGA,” International Journal of VLSI System Design and Communication
Systems, Vol. 03, Issue 04, July 2015.
2. Y. Penta and R. Islam, “Design and Verification of a Synchronous FIFO,” arXiv preprint arXiv:2504.10901,
2025.
3. [Link]

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Synchronous FIFO

Uploaded by

Synchronous FIFO

Uploaded by

Government College of Engineering, Karad

(An Autonomous Institute of Government of Maharashtra)

Department of Electronics and Telecommunication

Third Year [Link]. [Summer-2022]

EX2611: Technical Presentation [ REVIEW ]

Title: DESIGN & IMPLEMENTATION OF SYNCHRONOUS FIFO

Name of Guide: Student Name [[Link].]

Prof. Utkarsha Gharge Sanika Sambhaji Jadhav [23151044]

• FIFO (First In First Out) is a temporary data

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