NPTEL Online Certification Courses
Indian Institute of Technology Kharagpur
Digital Electronics
Assignment- Week 12
TYPE OF QUESTION: MCQ/MSQ
Number of questions: 13 Total mark: 13 X 1 = 13
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QUESTION 1 :
How many address input and data input lines are required for a 64 K × 16 memory?
a. 6, 16
b. 16, 16
c. 16, 18
d. 18, 18
Correct Answer: b
Detailed Solution:
Total no. of address locations = 64𝐾 = 64 × 1024 = 26 × 210 = 216
Hence 16 address lines are required to interface 216
Total no. of bits required to store a word = 16 for 64K x 16 memory.
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QUESTION 2:
A certain semi-conductor memory chip is specified as 20K×8. How many words can be stored on
this chip? What is the word size?
a. 10240, 8 bit
b. 20480, 8 bit
c. 10240, 10 bit
d. 20480, 10 bit
Correct Answer: b
Detailed Solution: 20K = 20*1024 = 20280. Each word is having 8 bit.
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Indian Institute of Technology Kharagpur
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QUESTION 3:
Statement 1: Setup time is the minimum time between placements of valid address and write
disable.
Statement 2: Access time is the time to be allowed between placement of stable address and
availability of stable data.
a. Statement 1 is true but 2 is false
b. Statement 2 is true but 1 is false
c. Both the statements are true
d. Both the statements are false
Correct Answer: b
Detailed Solution:
Setup time is the minimum time between placements of valid address and write enable.
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QUESTION 4:
A RAM chip has a capacity of (2K × 8). The number of 2 × 4 decoders with enable line needed to
construct a (128K × 16) RAM from (2K × 8) RAM is
a. 16
b. 19
c. 21
d. 22
Correct Answer: c
Detailed Solution:
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RAM chip size = 2k ×8 (2048 words of 8 bits each)
RAM to construct =128k ×16
Number of chips required = (128k x 16)/ (2k x 8) = (64 x 2) [64 chips vertically with each having 2 chips
Horizontally]
So to select one chip out of 64 vertical chips, we need 6 x 64 decoder.
Available decoder is 2 x 4 decoder to construct 6 x 64decoder.
So 64/4=16, 16/4=4, 4/4=1
Hence 16+ 4 + 1 = 21 decoders are required.
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NPTEL Online Certification Courses
Indian Institute of Technology Kharagpur
QUESTION 5:
Consider the following circuit: If row address is HIGH, column address is HIGH, 𝑅̅/W=LOW
and ̅̅̅̅̅̅̅
𝐷𝑎𝑡𝑎 = LOW then which operation will takes place and what will be the value of Dout ?
a. Read, Low
b. Read, High
c. Write, Low
d. Write, High
Correct Answer: b
Detailed Solution:
(Refer to Lecture-57, Static Random Access Memory (SRAM) , NPTEL online certification
courses )
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NPTEL Online Certification Courses
Indian Institute of Technology Kharagpur
QUESTION 6:
A Decoder-OR ROM circuit is to be designed using 4 address lines. Find the min-term expressions
at the output of OR gates if the ROM is hardwired to store data 0010, 0110, 1010 and 1111 at
address locations 0000 to 0011, 0100 to 0111, 1000 to 1011 and 1100 to 1111.
a. F(D3) = ∑m(8,9,10,11,12,13,14,15) ; F(D2) = ∑m(6,7,12,13,14,15) ; F(D1) =
∑m(8,9,10,11) ; F(D0) = ∑m(0,1,2,3,4,5,8,9,10,11,12,13,14,15)
b. F(D3) = ∑m(0,1,2,3,4,5,8,9,10,11,12,13,14,15) ; F(D2) = ∑m(6,7,12,13,14,15) ;
F(D1) = ∑m(8,9,10,11) ; F(D0) = ∑m(8,9,10,11,12,13,14,15)
c. F(D3) = ∑m(8,9,10,11,12,13,14,15) ; F(D2) = ∑m(4,5,6,7,12,13,14,15) ; F(D1) =
∑m(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15); F(D0) = ∑m(12,13,14,15)
d. F(D3) = ∑m(8,9,10,11); F(D2) = ∑m(4,5, 6,7,12,13,14,15); F(D1) =
∑m(0,1,2,3,4,5,8,9,10,11,12,13,14,15); F(D0) = ∑m(12,13,14,15)
Correct Answer: c
Detailed Solution:
A3 A2 A1 A0 D3 D2 D1 D0
0 0 0 0 0 0 1 0
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 0
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 0
0 1 1 0 0 1 1 0
0 1 1 1 0 1 1 0
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1 0 0 0 1 0 1 0
1 0 0 1 1 0 1 0
1 0 1 0 1 0 1 0
1 0 1 1 1 0 1 0
1 1 0 0 1 1 1 1
1 1 0 1 1 1 1 1
1 1 1 0 1 1 1 1
1 1 1 1 1 1 1 1
The following truth table can be implemented by using 4 OR gates with input:
F(D3) = ∑m(8,9,10,11,12,13,14,15)
F(D2) = ∑m(4,5,6,7,12,13,14,15)
F(D1) = ∑m(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15)
F(D0) = ∑m(12,13,14,15)
Hence, correct answer is c.
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Indian Institute of Technology Kharagpur
QUESTION 7:
Which of the following statements are False?
I. The main memory of a computer system must be non-volatile.
II. To interface a 128K X 8 RAM, we require a minimum of 25 address lines.
III. Write enable time is the time to be allowed between placement of stable address and availability of
stable data.
IV. SRAM using CMOS uses cross-coupled inverters for basic memory cell.
a. I, II, III
b. I, II
c. II, III
d. All statements are false
Correct Answer: a
Detailed Solution:
Statement I is false because main memory is typically built using semiconductor RAM that is
volatile.
Statement II is false as 128K X 8 RAM can be interfaced using 17 address lines. (128 K = 128 ×
1024 = 27 × 210 = 217 = 17 address lines.)
Statement III is false. Write enable time is the minimum time required for write to remain
enabled.
Statement IV is true. SRAM using CMOS uses cross-coupled inverters for basic memory cell
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QUESTION 8:
Consider the following squaring BCD ROM circuit:
BCD Input, A3A2A1A0, (0-9)
D7 D4 D3 D0
The min-term expression for data line D4 and D3 is:
a. F(D4) = ∑m(4, 6) ; F(D3) = ∑m(3, 7)
b. F(D4) = ∑m(3, 7) ; F(D3) = ∑m(4, 6)
c. F(D4) = ∑m(5, 6,) ; F(D3) = ∑m(7, 8)
d. F(D4) = ∑m(7, 8) ; F(D3) = ∑m(5, 6)
Correct Answer: a
Detailed Solution:
The above given circuit can be implemented as,
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A3 A2 A1 A0 Dec. D7 D6 D5 D4 D3 D2 D1 D0 Dec
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 0 0 0 0 0 0 0 1 1
0 0 1 0 2 0 0 0 0 0 1 0 0 4
0 0 1 1 3 0 0 0 0 1 0 0 1 9
0 1 0 0 4 0 0 0 1 0 1 1 0 16
0 1 0 1 5 0 0 1 0 0 1 0 1 25
0 1 1 0 6 0 0 1 1 0 1 1 0 36
0 1 1 1 7 0 1 0 0 1 0 0 1 49
1 0 0 0 8 0 1 1 0 0 1 0 0 64
1 0 0 1 9 1 0 0 0 0 0 0 1 81
Hence, correct answer is a.
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QUESTION 9:
Flash memory is faster than EEPROM as data writing is in block (e.g 512 bytes) instead of 1 byte
at a time.
a. True
b. False
Correct Answer: a
Detailed Solution:
Refer to Lecture-59, Read Only Memory (ROM), NPTEL online certification courses and
reference books.
NPTEL Online Certification Courses
Indian Institute of Technology Kharagpur
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QUESTION 10:
Which of the following statements are TRUE?
1. In 1T DRAM cell, reading can be destructive due to high parasitic line capacitance.
2. 3T DRAM uses a separate capacitor for data storage, whereas, 1-T DRAM uses parasitic
capacitance of MOSFET.
3. Both capacitances of a 4T DRAM cell charges when Refresh signal is made active.
4. Address range of Memory can be increased by using additional decoder and Chip Select input
of a memory block.
a. 1 and 3
b. 2 and 3
c. 1 and 4
d. 2 and 4
Correct Answer: c
Detailed Solution:
2. Parasitic capacitance is used in 3T DRAM and a separate capacitor is used in 1T DRAM.
3. In 4T DRAM, charge across only one capacitor is refreshed.
Refer lecture-58, NPTEL online certification course.
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NPTEL Online Certification Courses
Indian Institute of Technology Kharagpur
QUESTION 11:
In the given circuit diagram of a PLA unit, the expression for F1 and F2is given by:
2 1
a) F1= πM (1, 3, 5, 6), F2= πM (0, 2, 4, 7)
b) F1= πM (0, 1, 2, 3, 5, 7), F2= πM (5,7)
c) F1= πM (1, 3, 5, 6), F2= πM (5,7)
d) F1= πM (0, 2, 4, 7), F2= πM (0, 1, 2, 3, 4, 6)
Correct Answer: c
Detailed Solution:
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Indian Institute of Technology Kharagpur
The input to AND gates are:
Gate 1 =A’ C’; Gate 2 = ABC; Gate 3 = B’C’; Gate 4 = AC
Similarly, input to OR gates are:
Gate 1 = A’C’+ABC+B’C’; Gate 2 = ABC+AC
The output F1 and F2 hence becomes, F1 = A’C’+ABC+B’C’ and F2 = (ABC+AC)’
F2 = (ABC+AC)’
= (AC (B+1))’
= (AC)’
= A’ + C’
Converting obtained F1 and F2 to min-term expressions, we get, F1= Σm (0, 2, 4, 7) = πM (1, 3, 5,
6) and F2= Σm (0, 1, 2, 3, 4, 6)= πM (5,7)
Hence, correct answer is c).
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