ECT304 VLSI CIRCUIT DESIGN

MODULE 1: PART 1
Module : VLSI Design Methodologies.
Introduction:
 Moore’s law

 ASIC: Design

 Fullcustom ASICs
 Standard cell based ASICs
 Gate array based ASICs

 SoCs
 FPGA devices
 ASIC and FPGA Design flows
Moore’s Law
 The law was named after Intel cofounder Gordon E. Moore.
 Moore’s law states that “the number of transistors in a dense

integrated circuit ( IC) doubles every 18 months”.

Moore’s Law
 Transistor sizes become smaller.
 Power consumption and cost decreases.
 Memory capacity and speed increases.
 Manufacturing companies such as Intel and IBM follow this trend when
releasing chips.
 Moore’s Law
5

 As of 2019, Samsung and TSMC are

commercially producing 5nm
transistors.
 By 2021 it is expected to go down
to 3nm.

Introduction to Electronics
ASIC
 Application-Specific Integrated Circuit.
 Design to perform a specific and unique applications.

 Using single chip for integrates several functions there by

reduces the system development cost.

 ASIC is a non-standard integrated circuit that is designed for a

specific use or application.

 ASIC may contain a very large part of the electronics needed

on a single integrated circuit.

ASIC Examples
ASIC ICs are: -
 A chip for a toy bear that talks,

 A chip for a satellite,

 A chip designed to handle the interface between memory and a

microprocessor for a workstation CPU,

 A chip containing a microprocessor as a cell together with other logic.
Types of ASICs
 ICs are made on a wafer.
 Circuits are built up with successive mask layers.
 The number of masks used to define the interconnect and other
layers is different between full-custom ICs and programmable
ASICs.
Types of ASICs
 The classification of ASICs is
Full-Custom ASICs
 All mask layers are customized.
 It only makes sense to design a full-custom IC if there are no

libraries available.
 Full-custom offers the highest performance and lowest part cost

(smallest die size) with the disadvantages of increased design time,

complexity, design expense, and highest risk.
 Microprocessors were exclusively full-custom, but designers are

increasingly turning to semicustom ASIC techniques in this area too.

 Full-Custom ASICs
 Other examples of full-custom ICs or ASICs are requirements for
high-voltage (automobile), analog/digital (communications), or sensors
and actuators.
 Customizing all of the IC features in this way allows designers to

include analog circuits, optimized memory cells, or mechanical structures

on an IC, for example. Full-custom ICs are the most expensive to
manufacture and to design.
 The manufacturing lead time (the time required just to make an IC not

including design time) is typically eight weeks for a full-custom IC.

Full-Custom ASICs
 These specialized full-custom ICs are often intended for a specific
application so, we might call some of them as full- custom ASICs.
 In a full-custom ASIC an engineer designs some or all of the logic

cells, circuits, or layout specifically for one ASIC. This means the
designer avoids using pretested and pre characterized cells for all
or part of that design.
 This might be because existing cell libraries are not fast enough, or

the logic cells are not small enough or consume too much power.
Full-Custom ASICs
Full-custom ASIC design makes sense only
 When no suitable existing libraries exist or

 Existing library cells are not fast enough or

 The available pre-designed/pre-tested cells consume too much

power that a design can allow or

 The available logic cells are not compact enough to fit or

 ASIC technology is new or/and so special that no cell library

exits.
Semicustom ASICs
 ASICs , for which all of the logic cells are predesigned and some
(possibly all) of the mask layers are customized are called semi custom
ASICs.
 Using the predesigned cells from a cell library makes the design, much
easier.
 There are two types of semicustom ASICs
1) Standard-cell–based ASICs
2) Gate-array–based ASICs.
Standard-Cell Based ASICs
 A cell-based ASIC (CBIC—“sea-bick”).
 Use predesigned logic cells (AND gates, OR gates, multiplexers, and
flip-flops, for example) known as standard cells from
 Megacells (Microcontroller or Microprocessors), megafunctions, fullcustom
blocks, system-level macros (SLMs), fixed blocks, cores, or Functional
Standard Blocks (FSBs)
 All mask layers are customized — transistors and interconnect
 Custom blocks can be embedded
 Manufacturing lead time is about eight weeks.
Standard-Cell Based ASICs
 A cell-based ASIC (CBIC)
die with a single standard-
cell area (a flexible block)
together with four fixed
blocks.
Standard-Cell Based ASICs
Standard Cell in Flexible block of CBIC
 Std cell in library is constructed using full-custom design

methodology -
 Same performance and flexibility but reduce time and risk.
 ASIC designer defines only placement of standard cells
 It can be placed anywhere on silicon.
Standard-Cell Based ASICs
Construction of Flexible blocks in CBIC
 Standard cells are designed like bricks in a wall.

 Groups of standard cells fit horizontally to form rows.

 The rows stack vertically to form flexible blocks-reshape during

design
 Flexible blocks connected with other std cell blocks or full

custom block
Standard-Cell Based ASICs
Advantages of CBIC:
 Save time, money, reduce risk.

 Standard cell optimized individually for speed or area.

Disadvantages of CBIC:
 Time to design standard cell library.

 Expenses of designing std cell library.

 Time needed to fabricate all layers of the ASIC for new design.
Gate-Array Based ASICs
 Transistors are predefined on the silicon wafer.
 Predefined pattern of transistors on a gate array is base array.

 Smallest element repeated to form base array is base cell.

 Only the top few layers of metal, which define the interconnect

between transistors, are defined by the designer using custom

masks. It is often called a Masked Gate Array (MGA).
 Less turn around time: few days or couple of weeks.
Gate-Array Based ASICs
 A gate array, masked gate array, MGA, or prediffused array
uses macros (books) to reduce turnaround time and comprises
a base array made from a base cell or primitive cell. There
are three types:
 Channeled gate arrays
 Channelless gate arrays
 Structured gate arrays
Channeled Gate Array
 First to be developed
 Only the interconnect is
customized.
 The interconnect uses predefined
spaces between rows of base cells
 Manufacturing lead time is
between two days and two weeks
 Similar to CBIC – but here space
is fixed.
Channelless Gate Array
 A channelless gate array
(channel-free gate array, sea
of-gates array, or SOG array)
 Only some (the top few) mask
layers are customized — the
interconnect.
 Manufacturing lead time is
between two days and two
weeks.
Structured Gate Array
 An embedded gate array or
structured gate array
(masterslice or masterimage).
 Only the interconnect is
customized.
 Custom blocks (the same for each
design) can be embedded.
 Manufacturing lead time is
between two days and two
weeks.
 System-on chip (SoC)
31

 Technological Advances
 today’s chip can contains billions of transistors .
 approximately every 18 months the number of transistors on a chip
doubles – Moore’s law .
 System on chip (SoC)
32

 A new design innovation  a system on a single chip.

 SoC is a system on a VLSI chip that has all needed analog as well
as digital circuits, processors and software.
 Innovations in the semiconductor area  concept of integration of
multiple function ‘systems’ on a single chip.
 SoCs changed the concept of embedded processor from general
purpose design to device specific design.
 E.g. like Set Top Boxes, Portable media players, mobile phone etc.
 SoC …
33

 Usually includes:
 Programmable processor(s)
 Memory
 Accelerating function units
 Input/output interfaces
 Software
 Re-usable intellectual property (IP) blocks (HW + SW)
 SoC …
34

 SoC technology will put the maximum amount of technology into

the smallest possible space.
 On a first look SoC and ASIC resembles the same, but they are

not.
 SoCs are built by integrating the proven reusable IPs of

different sub-systems, whereas ASICs are IPs developed for a

specific application.
 SoC is Everywhere..
35
 SoC, embedded systems, microcontrollers, microprocessors
36

 Microprocessors/CPUs,
generally speaking, are the computing core and are the base for
everything else
 Microcontrollers
= microprocessors + memory + other peripherals like UART, USB,
CAN; can be a standalone device
 Embedded systems
is microcontrollers programmed to do specific tasks, so normally not
general-purpose
 SoC, embedded systems, microcontrollers, microprocessors
37

 SoC
is microcontrollers + advanced components like GPU, more
general-purpose compared to embedded systems; has all the
ability of a computer (can run OS like Linux), just inferior in
performance
 System on Chip (SoC) ?
38

 SoC not only chip, but more on “system”.

 SoC = Chip + Software + Integration
 The SoC chip includes:
 Embedded processor
 ASIC Logics and analog circuitry
 Embedded memory
 System on Chip (SoC) ?
39

 The SoC Software includes:

 OS, compiler, simulator, firmware, driver, protocol stack
Integrated development environment (debugger, linker, ICE),
Application interface (C/C++, assembly)
 The SoC Integration includes :
 The whole system solution
 Manufacture consultant
 Technical Supporting
SoC
Architecture

40
 SoC usually contains various components such as:
41

 Embedded processor GPP or ASIP core,

 Single purpose processing cores or multiple processor cores,

 A network bus protocol core,

 An encryption and decryption functions cores,

 Cores for FFT and Discrete cosine transforms for signal

processing applications,
 Memories
 SoC usually contains various components such as:
42

 Multiple standard source solutions, called IP (Intellectual

Property) cores,
 Programmable logic device and FPGA (Field Programmable

Gate Array) cores.

 Other logic and analog units.
 IPs in SoC
43

 IP – a standard source solution for synthesizing a higher-level

component by configuring a core of VLSI circuit or FPGA core
available as an Intellectual Property, called IP.
 High Level Components with gate level sophistication circuit

much above level of counters and registers.

 Designer or designing company holds the copyright.

 One might have to pay royalty for every chip shipped. An

embedded system may incorporate several IPs.

 SoC design with re-usable IP modules
44

 IP = intellectual property  Steps in re-use

 HW or SW block  Block -> IP -> integration
 Designed for reuse architecture
 Need for standards (VSIA)

 Platform-based SoC design

 Organized method
 Reduce cost and risk
 Heavy re-use of HW and SW
IP
 Solution is Design Re-use
45

 Design activity is split into two groups:

– IP Authors – producers .
– IP Integrators – consumers .
 IP Authors produce fully verified IP libraries
– Thus making overall verification task more manageable
 IP Integrators select, evaluate, integrate IP from multiple vendors
– IP integrated onto Integration Platform designed with specific
application in mind
 An IP may provide a:
46

 Design for adaptive filtering of a signal.

 Full design for implementing Hypertext Transfer Protocol (HTTP)

or File Transfer Protocol (FTP) to transmit a web page or file on

Internet.
 USB port controller, Bluetooth, GPS interface, Wireless
802.11or 802.16 interfaces.
 The Benefits of SoCs
47

 There are several benefits in integrating a large digital system into a

single integrated circuit .
These include
– Lower cost per gate.
– Lower power consumption.
– Faster circuit operation.
– More reliable implementation.
– Smaller physical size.
– Greater design security.
 The Drawbacks of SoCs
48

 The principle drawbacks of SoC design are associated with the

design pressures imposed on today’s engineers , such as :
– Time-to-market demands.
– Exponential fabrication cost.
– Increased system complexity.
– Increased verification requirements.
 SoC Some Challenges
49

 IP Availability
 Good and qualified IP from qualified vendors
 One stop IP search engine & service
 System Complexity
 Analog IP process dependency
 Advanced process maturity
 System software development - IP coverage
 Verification & Failure Analysis
 Lack of system simulation models
 IP testability - built-in self testing
 Testing equipment limitation
 Major SoC applications
50

 Speech Signal Processing .

 Image and Video Signal Processing .
 Information Technologies
 PC interface (USB, PCI,PCI-Express, IDE,..etc)
 Computer peripheries (printer control, LCD monitor controller, DVD
controller,.etc) .
 Data Communication
 Wireline Communication: 10/100 Based-T, xDSL, Gigabit Ethernet,.. Etc
 Wireless communication: BlueTooth, WLAN, 2G/3G/4G, WiMax, UWB, …,etc
 Major SoC applications
51

 Mobile phone/Smart phone

 Smart Home Appliances
52
Technology Basic Paradigm Basic Method of
Improvements within
Technology Paradigm
Chip-on-Board (CoB) Mounting of IC chips Substituting different
directly on PCBs materials to reducing
interconnect delays
System-in-package (SiP) Stacked chips or packages Improving performance
of reduced form factor and power efficiency
System-on-chip (SoC) Complete system on a chip Reducing form factor,
power consumption, heat
dissipation, analog mixed
signal integration
Field-Programmable Gate Arrays (FPGAs)
 FPGAs are the newest member of the ASIC family and are rapidly
growing in, replacing TTL in microelectronic systems.
 Even though an FPGA is a type of gate array, we do not consider the
term gate-array based ASICs to include FPGAs.
 There is very little difference between an FPGA and a PLD.
 An FPGA is usually just larger and more complex than a PLD.
 In fact, some vendors that manufacture programmable ASICs call their
products as FPGAs and some call them as complex PLDs .
Field-Programmable Gate Arrays (FPGAs)
 None of the mask layers are
customized.
 A method for programming the
basic logic cells and the
interconnect.
 The core is a regular array of
programmable basic logic cells
that can implement
combinational as well as
sequential logic (flip-flops).
Essential characteristics of FPGA
 Core-regular array of Programmable basic logic cells implement
combinational or sequential logic.
 Matrix of programmable interconnects surround the basic logic

cells.
 Programmable I/O cells surround the core.

 A method of programming the basic logic cells and interconnect.

 None of the mask layers are customized.

 Design turnaround is few hours.

FPGA Advantages
 Fast programming and testing time by the end user (instant turn-around)
 Excellent for prototyping
 Easy to migrate from prototype to the final design
 Can be re-used for other designs
 Cheaper (in small volumes)  lower start-up costs
 Re-programmable
 Lower financial risk
 Ease of design changes/modifications
 Cheaper design tools
FPGA Drawbacks:
 Slower than ASIC (2-3 times slower)
 Power hungry (up to 10 times more dynamic power)
 Use more transistors per logic function
 More area (20 to 35 times more area than a standard cell ASIC)
Implementation Approaches (ASIC vs. FPGA)
ASIC
Design
Flow
ASIC Design Flow
1 Design entry: Using a hardware description language (HDL) or schematic
entry.
2 Logic synthesis: Produces a netlist—logic cells and their connections.
3 System partitioning: Divide a large system into ASIC-sized pieces.
4 Prelayout simulation: Check to see if the design functions correctly.
5 Floorplanning: Arrange the blocks of the netlist on the chip.
6 Placement: Decide the locations of cells in a block.
7 Routing: Make the connections between cells and blocks.
8 Extraction: Determine the resistance and capacitance of the
interconnect.
9 Postlayout Check to see the design still works with the added loads of
simulation: the interconnect.
FPGA Design Flow
Design Entry
 The design entry is done in different techniques like schematic based,
hardware description language (HDL) and a combination of both etc.
 If the designer wants to deal with hardware, then the schematic entry
is a good choice.
 Ifthe designer thinks the design in an algorithmic way, then the HDL is the
better choice.
 The schematic based entry gives the designer a greater visibility and
control over the hardware.
Design Synthesis

 This process translates VHDL code into a device netlist format,

i.e., a complete circuit with logical elements.
 The design synthesis process will check the code syntax and

analyze the hierarchy of the design architecture.

 This ensures the design optimized for the design architecture.

 The netlist is saved as Native Generic Circuit (NGC) file.

Design Implementation
The implementation process consists of
 Translate

 Map

 Place and Route

Design Implementation

Translate
 This process combines all the input netlists to the logic design

file which is saved as NGD (Native Generic Database) file.

Here the ports are assigned to the physical elements like pins,
switches in the design.
 This is stored in a file called User Constraints File (UCF).
Design Implementation

Map
 Mapping divides the circuit into sub-blocks such that they can be

fit into the FPGA logic blocks.

 Thus this process fits the logic defined by NGD into the

combinational Logic Blocks, Input-Output Blocks and then

generates an NCD file, which represents the design mapped to
the components of FPGA.
Design Implementation

Place and Route

 The routing process places the sub-blocks from the mapping

process into the logic block according to the constraints and

then connects the logic blocks.
 It takes mapped NCD file as input and produces a completely

routed NCD file as output, which consist of routing information.

Design Programming
 The routed design must be loaded into the FPGA.
 This design must be converted into a format supported by the

FPGA.
 The routed NCD file is given to the BITGEN program, which

generates the BIT file. This BIT file is configured to the FPGA.
Design Verification
 Verification can be done at various stages of the process.
[Link] Simulation (RTL Simulation)
 Behavioral simulation is the first of all the steps that occur in the

hierarchy of the design.

 This is performed before cheap lace dresses the synthesis process

to verify the RTL code.

 In this process, the signals and variables are observed and further,

the procedures and functions are traced and breakpoints are set.
Design Verification
 Verification can be done at various stages of the process.
2. Functional Simulation
 Functional simulation is performed post-translation simulation. It gives

the information about the logical operation of the circuit.

3. Static Timing Simulation
 This is done post mapping. Post map timing report gives the signal path

delays.
 After place and route, timing report takes the timing delay information.

This provides a complete timing summary of the design.