ERBIL TECHNICAL ENGINEERING COLLEGE
Department Of Information And
Communication Technology Engineering
First stage
Basic RAM Overview:
Prepared by : Foad salem
Supervised by: M. Hemn Dasko
2025-2026
Table of Contents
Basic RAM Overview: ........................................................2
What RAM architecture Looks Like ...................................2
How The Data In RAM Is Accessed Figure .........................3
Main RAM .........................................................................4
Async Static RAM (ASRAM) ...............................................4
Burst (or SynchBurst) Static RAM (BSRAM) .......................5
Pipeline Burst Static RAM (PB SRAM) ...............................5
SRAM Comparison ............................................................5
Conclusion.........................................................................8
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Basic RAM Overview:
Random Access Memory, or RAM, is the hardware location in a computer where the operating
system, running applications, and data are stored for quick access by the processor. RAM can
read and write data far more quickly than the majority of other computer storage types, including
CD-ROM, floppy disks, and hard drives. But RAM can only store data for as long as it is
powered. RAM loses data when the computer is turned off. Your operating system and other
files are reloaded into RAM when you switch on your computer, usually from your hard drive.
RAM is like a person's short-term memory, and the hard drive is like their long-term memory.
Why Random Access?
RAM stands for "random access" since it allows direct access to any storage location. The term's
original use was to distinguish between offline memory, which was typically stored on magnetic
tape and required sequential address searching to retrieve a piece of data. With RAM access
being anything but random, perhaps "non-sequential memory" would have been a better term.
(Giakamozis, 1999) RAM can store and retrieve data straight to designated locations because of
the way it is arranged and managed. Direct access memory or storage is a word that IBM favors.
(Giakamozis, 1999) Although other types of storage, such the hard drive and CD-ROM, are also
accessed directly, or "randomly," random access is not the same as
What RAM architecture Looks Like
In general, RAM is much like an arrangement of cells in which each cell can hold a
0 or a 1. Each cell has a unique address that can be found by counting across
columns and then counting down by row. To find the contents of a cell, the RAM
controller sends the column/row address down a very thin electrical line etched
into the chip. There is an address line for each row and each column in the set of
cells. If data is being read, the bits that are read flow back on a separate data line.
In describing a RAM chip or module, a notation such as 256Kx16 means 256
thousand columns of cells standing 16 rows deep Eight million capacitors, eight million
transistors, and the pathways connecting them are found in an 8 megabyte module of dynamic
RAM.
Every cell in dynamic RAM, the most popular type of RAM, has a charge or lack of
stored energy in a structure akin to an electrical capacitor. When deciding whether the value in
the capacitor can be read or written, a transistor functions as a gate. The transistor in static RAM
functions as a positional flip/flop switch, with one position denoting 1 and the other position
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denoting 0, rather than a capacitor-held charge.
RAM is an external chip that is integrated into the motherboard of a personal computer, with a
variable number of extra modules inserted into motherboard sockets. Adding RAM to your PC is
as easy as adding
How Data In RAM Is Accessed Figure
The instruction that the processor or CPU must execute next may include the address of a
memory or RAM location where data must be read and sent to the processor for additional
processing. The RAM receives this address.
in charge. In order to read the values of each capacitor, transistors along the address lines along
the RAM controller's path assemble the request and send it down the relevant address lines. In
DRAM, a capacitor that is charged above a specific voltage level denotes a binary value of 1,
and a capacitor that is charged below that level denotes a binary value of 0.
A capacitor in dynamic RAM needs to be power-refreshed before it can be read to guarantee that
the value
RAM is often divided into two main categories (1) main RAM, which stores every
kind of data and makes it quickly accessible to a microprocessor and (2) video
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RAM, which stores data intended for your display screen, enabling images to get
to your display faster.
Main RAM
RAM can be divided into static RAM (SRAM) and dynamic RAM (DRAM).
Static random access memory uses multiple transistors, typically four to six, for
each memory cell but doesn't have a capacitor in each cell. It is used primarily for
cache. Static RAM is more expensive, requires four times the amount of space for
a given amount of data than dynamic RAM, but, unlike dynamic RAM, does not
need to be power-refreshed and is therefore faster to access. One source gives a
typical access time as 25 nanoseconds in contrast to a typical access time of 60
nanoseconds for dynamic RAM. (AMT International 2001) (More recent advances
in dynamic RAM have improved access time.) Static RAM is used mainly for the
level-1 and level-2 caches that the microprocessor looks in first before looking in
dynamic RAM. (AMT International 2001)
Async Static RAM (ASRAM)
Async SRAM has been with us since the days of the 386, and is still in place in the
L2 cache of many PCs. It's called asynchronous because it's not in sync with the
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system clock, and therefore the CPU must wait for data requested from the L2
cache. However, the wait isn't as long as it is with DRAM. (AMT International
2001)
Burst (or SynchBurst) Static RAM (BSRAM)
Burst SRAM (also known as SynchBurst SRAM) is synchronized with the system
clock or, in some cases, the cache bus clock. This allows it be more easily
synchronized with any device that accesses it and reduces access waiting time. It
is used as the external level-2 cache memory for the Pentium II microprocessor
chipset. (AMT International 2001) Async SRAM commonly used for L2 caches, with
speeds of about 8.5 ns. Unfortunately, Sync SRAM isn't being produced in
sufficient quantities to drive its cost down, so it seems destined for a relatively
short life. That's especially true because it loses the ability to synchronize at bus
speeds higher than 66 MHz. (AMT International 2001)
Pipeline Burst Static RAM (PB SRAM)
Using burst technology, SRAM requests can be pipelined, or collected so that
requests within the burst are executed on a nearly instantaneous basis. PB SRAM
uses pipelining, and while it's slightly behind system synchronization speeds, it's a
possible improvement over Sync SRAM because it's designed to work well with
bus speeds of 75 MHz and higher. (x2xtreme 2001)
SRAM Comparison
The following table shows the capabilities of various SRAM technologies at a
number of external bus frequencies. The numbers in the table indicate the typical
memory access achieved in terms of the number of wait states for initial and
subsequent accesses. The shaded areas indicate the best performance/price
points for the various bus speeds and technology. Note issue to keep in mind is
that the most cost effective SRAM technology moves from asynchronous to flow-
through synchronous to pipelined synchronous as bus frequencies increase.
However, presently there are fewer suppliers with the underlying SRAM
technology required for very fast flow-through synchronous SRAMs. As a result, in
systems where performance is less critical designers are choosing pipelined
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synchronous for the 50 MHz to 66 MHz bus frequencies to increase the number of
possible suppliers and hopefully, product availability. (x2xtreme 2001)
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refresh is required after each read. Apart from reading, just to maintain the charge
that holds its content in place, DRAM must be refreshed about every 15
microseconds. This simple architecture makes DRAM the least expensive kind of
RAM. (AMT International 2001)
Parity DRAM
Normally you assume 8 bits to one byte in memory. However, for many years, a
ninth bit has been added as parity bit in the RAM blocks to verify correct
transmission. That way you have to transmit 9 bits, to store 8 bits in the old 30 pin
RAM chips. And it takes 36 bits to store 32 bits in the larger 72 pin chips, which
increases the cost of the RAM chip by about 12%. If your motherboard required
36 bit modules, you had to use the larger parity modules. Fortunately, most
system boards accepted 32 bit modules, so this was rarely a major concern. (AMT
International 2001)
A series of FPM read access's starts with the activation of a row in the DRAM array
by providing a row address and bringing RAS LOW. Then, multiple column accesses
may be executed by cycling CAS. Each CAS cycle includes applying a column
address, bringing CAS LOW, waiting for valid data-out, latching data in the system
and bringing CAS HIGH to prepare for the next cycle, in that order. This sequence
of events is shown in the Figure. Note that CAS going HIGH disables the data
outputs, and therefore must occur only after the valid data is latched by the
system. Fast page mode dynamic random access memory was the original form of
DRAM. A timing graph of a typical FPM DRAM is shown above. It waits through
the entire process of locating a bit of data by column and row and then reading
the bit before it starts on the next bit. Maximum transfer rate to L2 cache is
approximately 176 megabytes per second. FPM was the traditional RAM for PCs
long before the EDO was introduced. It was usually mounted in SIMM modules of
2, 4, 8, 16, or 32 MB. Typically, it is found in 60 ns or 70 ns versions. Clock timings
for FPM DRAM are typically 6-3-3-3 (meaning 3 clock cycles for access setup, and
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3 clock cycles for the first and each of three successive accesses based on the
initial setup). (Tang 1996)
Conclusion
Random Access Memory (RAM) is a fundamental component of modern computer
systems, providing fast and temporary storage that enables the processor to
access data and instructions efficiently. Although volatile in nature—losing its
contents when power is removed—RAM plays a critical role in overall system
performance.
The distinction between Static RAM (SRAM) and Dynamic RAM (DRAM)
highlights the trade-off between speed and cost: SRAM is faster and used mainly
for cache, while DRAM is cheaper and used as the main system memory. With
continuous technological advancements, RAM remains central to improving
computing speed, responsiveness, and efficiency in modern devices.
References
• Wikipedia – Random Access Memory
Comprehensive overview of RAM, its history, architecture, and modern
implementations.
Random-access memory - Wikipedia
• GeeksforGeeks – Different Types of RAM
Explains RAM types (SRAM, DRAM, SDRAM, DDR, etc.) with clear
comparisons.
Different Types of RAM (Random Access Memory) - GeeksforGeeks
• Sanfoundry – RAM Fundamentals
Tutorial-style explanation of RAM definition, features, architecture, and
differences with ROM.
Random Access Memory (RAM) - Sanfoundry
• GeeksforGeeks – Difference between SRAM and DRAM
Detailed comparison of static vs dynamic RAM, including speed, cost, and
usage.
Difference between SRAM and DRAM - GeeksforGeeks
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