CSCI2510 Computer Organization

Lecture 09:
Basic Processing Unit

Ming-Chang YANG
mcyang@[Link]

Reading: Chap. 2.13, 5

Basic Functional Units of a Computer

Registers
Input

Arithmetic and
Memory
Logic Unit

Output
Control

I/O Processor / CPU

• Input: accepts coded information from human operators.
• Memory: stores the received information for later use.
• Processor: executes the instructions of a program stored in the memory.
• Output: reacts to the outside world.
• Control: coordinates all these actions.
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 2
Outline
• Processor Basics
• RISC-Style Processor Design
– Five-Stage Organization
– Instruction Execution

• CISC-Style Processor Design

– Multi-Bus Interconnect
– Instruction Execution

• Control Signal Generation

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 3

Basic Processing Unit: Processor
• Executing machine-language instructions.
• Coordinating other units in a computer system.
• Used to be called the central processing unit (CPU).
– The term “central” is no longer appropriate today.
– Today’s computers often include several processing units.
• E.g., multi-core processor, graphic processing unit (GPU), etc.

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 4

Main Components of a Processor
Control Instruction Address Generator
Circuitry
Program Counter (PC)
Interpret/decode the fetched instruction & Keep the address of the next instruction
issue control signals to coordinate all the other units to be fetched and executed (special register)
Update the contents of PC
Register after every instruction is fetched
File
(i.e., R0~Rn-1) Instruction Register (IR)
Served as the processor’s general-purpose registers Hold the instruction until
its execution is completed (special register)

Other Special Registers

Arithmetic and Other SpecialRegisters
Other Special Registers
Logic Unit (ALU) E.g., memory address register, memory
data register, condition code register, stack
Perform arithmetic or logic operations pointer register, link register, etc.

Processor–Memory Interface
Allow communication between processor and memory through two special registers:
memory address register (MAR) and memory data register (MDR)
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 5
Register File
• General-purpose registers are usually implemented
as a register file, a small and fast memory block.
• It allows data to be read from written into any register
with two data outputs (A & B) and one data input (C).

C C C

Register Register Register

File File File

A B A B

Single Memory Block Two Memory Blocks

(with duplicate datapaths and access circuitry) (with two files having identical contents)
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 6
Arithmetic and Logic Unit (ALU)
• The ALU is used to
process data. C

– It supports arithmetic
Register
operations (e.g., ADD and File
SUB) and logic operations
(e.g., AND, OR, and XOR). A B

– It has two data inputs:

• InA is from Output A of
MuxB
Register File;
• InB is from either Output B of
Register File or the
InA InB
immediate value in IR
(selected by multiplexer MuxB). ALU

– Its output (Out) connects to Out

Input C of Register File.

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 7
Structure for Data Processing (1/2)
• The general structure of data processing:
– Instructions operate on data in registers.
– Data are processed by combinational logic circuits (e.g.,
full adder), and the results are placed into a register.
– A clock is used to control the timing of data transfers.
• The clock period (i.e., the time between two successive pulses)
must be long enough to allow the combinational circuit to complete.

A A B Cin SUM Cout

Register

Register
B SUM
Combinational 0 0 0 0 0
…

…
Logic 0 0 1 1 0
Cin
Circuit Cout ...
1 1 1 1 1

Clock
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 8
Structure for Data Processing (2/2)
• Alternatively, data processing can be broken down
into simpler steps:
– Each step is performed by a subcircuit (that can be
completed in less time;
– These subcircuits are cascaded into a multistage structure.
• If 𝑛 stages are used, the operation will be completed in 𝑛 cycles.
– It is particularly suitable for pipelined operation (see Lec10).
Register
Register

Register

Register
Sub- Sub- Sub-

…
…

…
circuit circuit circuit

Stage  Stage  Stage 

Clock
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Recall: RISC vs. CISC Styles
• There are two fundamentally different approaches in
the design of instruction sets for modern computers:
1) Reduced Instruction Set Computer (RISC) reduces the
complexity/types of instructions for higher performance.
• Each instruction fits in a single word in memory.
• A load/store architecture is adopted.
– Memory operands are accessed only using Load/Store instructions.
– The operands involved in arithmetic/logic operations must be either in
registers or given explicitly within the instruction.
2) Complex Instruction Set Computer (CISC) allows more
complicated but powerful instructions to be designed.
• Each instruction may span more than one word in memory.
• The operands involved in arithmetic/logic operations can be in both
registers and memory or given explicitly within the instruction.
• Two-operand format is usually used.
The processor
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10
Outline
• Processor Basics
• RISC-Style Processor Design
– Five-Stage Organization
– Instruction Execution

• CISC-Style Processor Design

– Multi-Bus Interconnect
– Instruction Execution

• Control Signal Generation

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 11

Five-Stage Organization (RISC CPU)
• The execution of RISC instructions can be generally
organized into a five-stage sequence of actions:
 Fetch an instruction and increment the PC.
 Decode the instruction & read source registers.
 Perform an ALU operation.
 Read or write memory data if memory operand is involved.
 Write the result into the destination register.
Note: Not all actions have to be carried out by every instruction.
Stage  Stage  Stage  Stage  Stage 

Instruction Source Memory Destination

ALU
Fetch Registers Access Register

Fetch Phase Execution Phase

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 12
Multi-Stage Structure: Datapath
• The processor’s hardware C IR
Addr.
PC
Gen.
can also be organized into Register
File
multiple stages. A
(R0~Rn-1)
B
– Control Circuitry
coordinates all the stages. RA RB

• Each stage can work MuxB

independently. Control
Circuitry
InA InB
– It is necessary to have inter- ALU
stage registers to  hold
the produced results and  RZ RM

work as inputs to the next.

Mem
• This multi-stage structure MuxY MDR MAR

is often called datapath. RY

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 13
Outline
• Processor Basics
• RISC-Style Processor Design
– Five-Stage Organization
– Instruction Execution

• CISC-Style Processor Design

– Multi-Bus Interconnect
– Instruction Execution

• Control Signal Generation

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 14

Fetch Phase: Stage 
IR_enable PC_enable

• The fetch phase includes

RY MDR
Addr.
C IR PC
Gen.
two major actions: Register
File reg. IR

#immediate
1) IR  [[PC]] A
(R0~Rn-1)
B
addr.
Control
• Load the memory contents Circuitry
...
pointed to by PC into IR. RA RB
control signals

• The MuxMA is set to select RB

the address from PC. MuxB
• IR_enable must be set. RA
InA InB
2) PC  [PC] + 4 ALU
• PC_enable must be set. RB
Branch offset RZ RM
PC_enable
4 from IR
INC_sel
RZ MDR RZ PC
PC MuxINC
MuxY MA_sel MuxMA
Instruction

Mem
R/W
Adder RY MDR MAR
Address MFC
Generator
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 15
Execution Phase: Stage 
• The execution phase is
RY MDR
Addr.
C IR PC
Gen.
generally of four stages: Register
File reg. IR

#immediate
 Decode the instruction & A
(R0~Rn-1)
B
addr.
Control
read source registers. Circuitry
...
control signals
• [IR] must be firstly decoded RA RB
by Control Circuity. RB

– It is for generating signals MuxB

to control all the hardware. RA
• Two source registers can be InA InB
ALU
read from Register File at
RB
the same time.
RZ RM
– How? The source register
addresses are supplied by
RZ MDR RZ PC
IR directly (w/o decoding).
MuxY MuxMA
– Two source registers are
always read and placed

Mem
into RA and RB (no matter RY MDR MAR
whether
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 Instruction Encoding
• Consider a RISC-style processor that
– Has 32 general-purpose registers;
– Represents every instruction by a 32-bit word.

• Representative encoding formats include:

31 27 26 22 21 17 16 0
 Register-operand Format
Rsrc1 Rsrc2 Rdst OP code
• E.g., Add, Rdst, Rsrc1, Rsrc2
 Immediate-operand Format
• E.g., Add Rdst, Rsrc, #Value
• E.g., Load/Store instruction using 31 27 26 22 21 6 5 0
register indirect or index modes Immediate OP
Rsrc Rdst
• E.g., Branch instruction using offset operand code

 Address-operand Format 31 6 5 0
• E.g., Branch instruction OP
Address
• E.g., Call instruction code

The instruction
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17
Class Exercise 9.1
• Consider the register-operand format for the
instruction encoding.

• What are the maximal numbers of registers and types

of instructions this format can support, respectively?

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 18

Execution Phase: Stage 
• The execution phase is
RY MDR
Addr.
C IR PC
Gen.
generally of four stages: Register
File reg. IR

#immediate
 Perform ALU operation. A
(R0~Rn-1)
B
addr.
Control
• The input InA of ALU is Circuitry
...
supplied by RA. RA RB
control signals

• The input InB of ALU is RB

supplied by the multiplexer B_sel MuxB
MuxB which forwards: RA
– Either the contents of RB; InA InB
ALU
– Or the immediate value
ALU_op RB
specified in IR.
RZ RM
• ALU performs the operation.
• The computed result is RZ MDR RZ PC
placed in RZ. MuxY MuxMA
• Note: [RB] will also be

Mem
forwarded to RM (though it’s RY MDR MAR
only
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byUnit 2024-25 T1 20
Execution Phase: Stage 
• The execution phase is
RY MDR
Addr.
C IR PC
Gen.
generally of four stages: Register
File reg. IR

#immediate
 Read/write memory data. A
(R0~Rn-1)
B
addr.
Control
• The memory read/write takes Circuitry
...
place via Processor-Mem RA RB
control signals

Interface. RB
– The effective address is MuxB
derived by ALU and kept in
RA
RZ in Stage .
InA InB
– The “loaded” data are put ALU
into RY (with the multiplexer RB
MuxY properly set). RZ RM
– The “to-be-stored” data are
available in RM. RZ MDR RZ PC
• Note: For non-Load and non- Y_sel MuxY MA_sel MuxMA
Store instructions, the data

Mem
R/W
in RZ are forwarded to RY. RY MFC
MDR MAR
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 21
Execution Phase: Stage 
• The execution phase is
RY MDR
Addr.
RF_write C IR PC
Gen.
generally of four stages: Register
File reg. IR

#immediate
 Write the result into the A
(R0~Rn-1)
B
addr.
Control
destination register. Circuitry
...
control signals
• The data kept in RY, which RA RB
can be: RB

– Either the result computed MuxB

by ALU in Stage  and RA
forwarded to RY in Stage ; InA InB
– Or the data loaded from the ALU
memory in Stage . RB

are written into Register File RZ RM

if needed.
RZ MDR RZ PC
– The dest. reg. address is
from IR but is determined MuxY MuxMA
by Control Circuitry.

Mem
RY MDR MAR
– RF_write must be set.
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 22
Observations
• The datapath is designed
RY MDR
Addr.
C IR PC
Gen.
to be independent, multi- Register
File reg. IR

#immediate
function, and general. A
(R0~Rn-1)
B
addr.
Control
Circuitry
• But not all actions/stages ...
control signals
RA RB
have to be carried out by RB
every instructions. MuxB

• Let’s examine it with the RA

InA InB
ALU
following instructions:
RB
1) Add R3, R4, R5 RZ RM
2) Load R5, X(R7)
RZ MDR RZ PC
3) Store R6, X(R8) MuxY MuxMA
4) Branch

Mem
RY MDR MAR
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 23
Recall: Register Transfer Notation
• Register Transfer Notation (RTN) describes the data
transfer from one location in computer to another.
– Possible locations: memory locations, processor registers.
• Locations can be identified symbolically with names (e.g., LOC).

Ex.
R2 ← [LOC]
– Transferring the contents of memory LOC into register R2.

 Contents of any location: denoted by placing

square brackets [ ] around its location name (e.g. [LOC]).
 Right-hand side of RTN: always denotes a value
 Left-hand side of RTN: the name of a location where the
value is to be placed (by overwriting the old contents)
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 24
Ex 1: Add R3, R4, R5
 MAR  [PC], Read memory, RY MDR
Addr.
C IR PC
Wait_MFC, IR  [MDR], RF_write
Register
Gen.
PC  [PC] + 4 (shown here) File reg. IR

#immediate
(R0~Rn-1) addr.
 Decode instruction, A B Control
Circuitry
RA  [R4], RB  [R5] ...
control signals
• The source register addresses are RA RB
available in IR31-27 and IR26-22. RB
• As a result, [R4] and [R5] can be B_sel MuxB
read into RA and RB in Stage . RA

 RZ  [RA] + [RB] InA

ALU
InB

• MuxB is set to select input from RB. ALU_op RB

• ALU is set to perform an Add.
RZ RM
 RY  [RZ]
RZ MDR RZ PC
• MuxY is set to select input from RZ.
Y_sel MuxY MuxMA
 R3  [RY]

Mem
• The dest. reg. address is in IR21-17. RY MDR MAR
• RF_write
CSCI2510 Lec09: BasicisProcessing
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Unit 2024-25 25
Class Exercise 9.2
• Assume R3, R4, and R5 originally hold the values 0,
40, and 60, respectively.
• Considering Add R3, R4, R5, show the registers’
contents “after” the completion of Stages  to :
– Note: Fill in “?” for those blanks that cannot be determined.

RA RB RZ RY R3





CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 26

Ex 2: Load R5, X(R7)
 MAR  [PC], Read memory, RY MDR
Addr.
C IR PC
Wait_MFC, IR  [MDR], RF_write
Register
Gen.
PC  [PC] + 4 (shown here) File reg. IR

#immediate
(R0~Rn-1) addr.
 Decode instruction, A B Control
Circuitry
RA  [R7] ...
control signals
• The src. reg. address is in IR31-27. RA RB
RB
 RZ  [RA] + X B_sel MuxB
• The immediate value X is from IR. RA
• MuxB is set to select input from IR. InA InB
• ALU is set to perform an Add. ALU

 MAR  [RZ], Read memory, ALU_op RB

Wait_MFC, RY  [MDR] RZ RM

• MuxMA is set to select input from RZ.

RZ MDR RZ PC
• MuxY is set to select input from MDR.
Y_sel MuxY MA_sel MuxMA
 R5  [RY]

Mem
R
• The dest. reg. address is in IR26-22. RY MFC
MDR MAR
• RF_write
CSCI2510 Lec09: BasicisProcessing
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Unit 2024-25 28
Class Exercise 9.3
• Assume R5 and R7 originally hold the values 0 and 4,
respectively, and the contents of main memory are
shown as follows:
0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 …
9 8 7 6 5 4 3 2 1 0 …
• Considering Load R5, 4(R7), show the registers’
contents “after” the completion of Stages  to :
– Note: Fill in “?” for those blanks that cannot be determined.
RA RB RZ RY MAR MDR R5 R7




CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 29
Ex 3: Store R6, X(R8)
 MAR  [PC], Read memory, RY MDR
Addr.
C IR PC
Wait_MFC, IR  [MDR], Register
Gen.
PC  [PC] + 4 (shown here) File reg. IR

#immediate
(R0~Rn-1) addr.
 Decode instruction, A B Control
Circuitry
RA  [R8], RB  [R6] ...
control signals
• The src. reg. address is in IR31-27. RA RB
• The dest. reg. address is in IR26-22. RB
B_sel MuxB
 RZ  [RA] + X, RM  [RB]
RA
• The immediate value X is from IR.
InA InB
• [R6] is forwarded to  via RM. ALU

 MAR  [RZ], MDR  [RM], ALU_op RB

Write memory, Wait_MFC RZ RM

• MuxMA is set to select input from RZ.

RZ MDR RZ PC
• The written data are forwarded
from RM to MDR. MuxY MA_sel MuxMA

 No action

Mem
W
RY MFC
MDR MAR
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 31
Ex 4: Branch
PC_enable
 MAR  [PC], Read memory, RY MDR
Addr.
C IR PC
Wait_MFC, IR  [MDR], Register
Gen.
PC  [PC] + 4 (shown here) File reg. IR

#immediate
(R0~Rn-1) addr.
 Decode instruction A B Control
Circuitry
 PC  [PC] + branch offset ...
control signals
RA RB
• The branch offset is from IR.
• MuxINC (in Instruction Address RB

Generator) is set to select offset. MuxB

 No action RA
InA InB
 No action ALU
RB
Branch offset RZ RM
PC_enable
4 from IR
INC_sel
RZ MDR RZ PC
PC MuxINC
MuxY MuxMA
Instruction

Mem
Adder RY MDR MAR
Address
Generator
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 32
Class Exercise 9.4
• Branch instructions typically use the address field to
specify an offset from the current instruction to the
branch target. LABEL ADDR. OPCODE OPERAND

• Given the program, 100 Move R2, addr LIST

104 Clear R3
what is the required 108 Load R4, N
offset for Branch 112 Load R5, (R2)
LOOP at the memory LOOP: 116 Subtract R4, R4, #1
address 140? 120 Branch_if_[R4]=0 DONE

– Note: This program 124 Add R3, R3, #4

128 Load R6, (R2,R3)
finds out the smallest
132 Branch_if_[R6]≥[R5] LOOP
number in a list.
136 Move R5, R6
140 Branch LOOP
DONE: 144 Store R5, RESULT
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 33
Remark 1: Register Enabling
IR_enable PC_enable

• Inter-stage registers
RY MDR
Addr.
RF_write C IR PC
Gen.
(i.e., RA, RB, RZ, RM, & Register
File reg. IR

#immediate
RY) are always enabled. A
(R0~Rn-1)
B
addr.
Control
Circuitry
– The results from one stage ...
control signals
are always transferred to RA RB
the next for simplicity. RB

MuxB
• Other registers (e.g., PC, RA

IR, and Register File) InA

ALU
InB

must not be changed in RB

every stage. RZ RM

– They are enabled only at RZ MDR RZ PC

certain times (by Control MuxY MuxMA

Circuitry) via PC_enable,

Mem
RY MDR MAR
IR_enable and RF_write.
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 35
Remark 2: Memory Function Completed
• For stages involving Mem,
RY MDR
Addr.
C IR PC
Gen.
– If data are in cache, the Register
File reg. IR

#immediate
stage can be completed in (R0~Rn-1) addr.
Control
A B
one clock cycle. Circuitry
...
– If data are not in cache, the RA RB
control signals

stage may take several RB

clock cycles. MuxB

– To handle such uncertainty:

RA
InA InB
ALU
• Processor-Memory
Interface generates the MFC RB

signal upon the completion of RZ RM

a memory operation.
RZ MDR RZ PC
• Control Circuitry checks the
MuxY MuxMA
MFC signal during any stage
involving memory to delay

Mem
R/W
RY MFC
MDR MAR
subsequent stage(s).
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 36
Outline
• Processor Basics
• RISC-Style Processor Design
– Five-Stage Organization
– Instruction Execution

• CISC-Style Processor Design

– Multi-Bus Interconnect
– Instruction Execution

• Control Signal Generation

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 37

Interconnect (CISC CPU)
• CISC-style instructions require a different and more
flexible organization of the processor hardware:
– Interconnect provides interconnections among other units
but does not prescribe any pattern of data flow.
– Inter-stage registers are not needed, but it is still necessary
to have some Temporary Registers.

Register Control
File Circuitry
Temporary
Registers IR
Interconnect
CPU-Mem PC
Interface
Instruction
ALU
Address
To cache and main memory Generator
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 38
Buses: Key to Transferring Data
• It is typical to use buses to implement Interconnect.
– A bus consists of a set of lines that enable data transferring
from any one device to any other (connected to the bus).

• There may be multiple devices connected to the bus:

– Only one can drive the bus at any given time.
– More than one can receive data from the bus at the same t.
– For this reason, switches ( ) are often needed to allow
data to be transferred into or transferred out from a device.
Bus

A B C D
A-in A-out B-in B-out C-in C-out D-in D-out

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 39

Three-Bus Implementation
Bus Bus Bus
• It is common to interconnect A B
Instruction
Addr. Gen.
C

the processor hardware via

PC
three buses:
– Why 3? Typical instruction format! Register
File
– Bus A and Bus B allow the data
transfer of two source operands InA
to ALU simultaneously. ALU
– Bus C allows transferring the InB

result (computed by ALU) to the

Control
destination operand.
– Note: Addresses for the three IR

ports of Register File are Temporary

generated by Control Circuity Registers
(not shown in the figure).
CPU-Mem
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 40
Outline
• Processor Basics
• RISC-Style Processor Design
– Five-Stage Organization
– Instruction Execution

• CISC-Style Processor Design

– Multi-Bus Interconnect
– Instruction Execution

• Control Signal Generation

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 41

Instruction Fetching and Decoding
Bus Bus Bus
• All the instructions share the A B
Instruction
Addr. Gen.
C

same actions of fetching and 

decoding: PC

 MAR  [PC], Read memory, Register

Wait_MFC, IR  [MDR], File
PC  [PC] + 4
• Bus B is used to send [PC] to CPU-Memory InA
Interface to fetch the instruction. ALU
• The data read from the memory are sent to InB
IR over Bus C. 
• Note: Wait_MFC is needed since the data Control
may be read from the main memory. 
IR
 Decode instruction
• [IR] is decoded by Control Circuity to Temporary
generate control signals (not shown). Registers
 
CPU-Mem
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 42
Ex 1: Add R5, R6
Bus Bus Bus
 MAR  [PC], Read memory, A B
Instruction
C
Addr. Gen.
Wait_MFC, IR  [MDR],
PC  [PC] + 4 (shown here)
PC
 Decode instruction (shown here)
 R5  [R5] + [R6] Register
File
• [R5] is read from Register File and
transferred to InA of ALU via Bus A.
InA
• [R6] is read from Register File and
transferred to InB of ALU via Bus B. ALU

• ALU is set to perform an Add. InB
• The sum is stored back into R5 via Bus C.
Control
• Note 1: Reading source registers cannot
proceed in parallel with the decoding, since
IR
CISC-style instructions do not always use
the same fields to specify reg. addresses.
• Note 2: Control Circuitry must carefully Temporary
Registers
coordinate how to read and write Register
File within the same step.
CPU-Mem
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 43
Ex 2: And X(R7), R9
Bus Bus Bus
• Assume the index offset is a A B
Instruction
Addr. Gen.
C

32-bit value given as the

PC
second word of the instruction.
31 0
Register
OP code Source Dest. Other File
Index Offset (X)
InA
 MAR  [PC], Read memory, ALU
Wait_MFC, IR  [MDR], 
InB
PC  [PC] + 4 (shown here)
 Decode instruction (shown here) Control

 MAR  [PC], Read memory, IR

Wait_MFC, Tmp1  [MDR],
PC  [PC] + 4 Temporary
Registers
• The second word (i.e., X) is fetched from
memory into the temporary register Tmp1.
CPU-Mem
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 44
Ex 2: And X(R7), R9 (Cont’d)
Bus Bus Bus
 Tmp2  [Tmp1] + [R7] A B
Instruction
C
Addr. Gen.
• [Tmp1] and [R7] are sent to ALU over
Buses A and B, and the effective address
PC
is placed into the temporary register Tmp2.
 MAR  [Tmp2], Read memory, Register
Wait_MFC, Tmp1  [MDR] File

• The contents of memory address X(R7)

are read and placed into Tmp1. InA
ALU
 Tmp1  [Tmp1] AND [R9] 



InB
• The AND computation is performed, and the
result is placed into Tmp1. Control
 MAR  [Tmp2], MDR  [Tmp1],
IR
Write memory, Wait_MFC
• The result is stored into the memory at the Temporary
address X(R7), which is “still” available in Registers
Tmp2 since the completion of .
CPU-Mem
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 45
Class Exercise 9.5
• Consider the three-bus implementation of a CISC-
style processor design.
• How many times of memory accesses are involved in
Add R5, R6 and And X(R7), R9, respectively?

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 46

Outline
• Processor Basics
• RISC-Style Processor Design
– Five-Stage Organization
– Instruction Execution

• CISC-Style Processor Design

– Multi-Bus Interconnect
– Instruction Execution

• Control Signal Generation

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 48

Recall: Control Signals
IR_enable PC_enable

• The processor’s hardware

RY MDR
Addr.
RF_write C IR PC
Gen.
is governed by control Register
File reg. IR

#immediate
signals that determine: A
(R0~Rn-1)
B
addr.
Control
– What is the input data appearing Circuitry
...
at a Multiplexer’s output? RA RB
control signals

– What will be the operation RB

performed by ALU? B_sel MuxB
– Will the data be loaded into the RA
selected register? InA InB
ALU
– Etc.
ALU_op RB
Branch offset RZ RM
PC_enable
4 from IR
INC_sel
RZ MDR RZ PC
PC MuxINC Y_sel MuxY MA_sel MuxMA
Instruction

Mem
R/W
Adder RY MDR MAR
Address MFC
Generator
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 49
Control Signal Generation
• There’re two typical ways to generate control signals:
1) Hardwired Control: 2) Microprogrammed Control:
• The combinational circuit is used • Control signals are specified by
to “hard code” the generation of “micro-programs” in Control Store.
control signals with logic gates. – The micro-Program Counter (μPC)
points to the next control word.
• It is a “hardware approach” and can
operate at high speed. • It is a “software approach” and can
support a complex instruction set.

Step Counter Clock control μPC

word
Combinational Circuit Control Store (Memory)
IR T1 IR T T T T T T T T T T
T2 1 2 3 4 5 1 2 3 4 5
T3 …

001...
T4 μProgram μProgram
(Add) (Sub)
T5

control signals ... control signals ...

 MAR  [PC], Read memory, Wait_MFC,  MAR  [PC], Read memory, Wait_MFC,
IR  [MDR], PC  [PC] + 4 IR  [MDR], PC  [PC] + 4

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 50

Hardwired Control

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 51

Microprogrammed Control

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 52

Program Counter vs. μ-Program Counter

Control Circuitry

Instruction Register Program Counter μ-Program Counter

(IR) (PC) (μPC)

T1 Control Word

T2 Control Word
Control
Memory I0 I1 I2 … …
Store
E.g.,
Add

Assembly μProgram
Program (Add)
CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 53
Summary
• Processor Basics
• RISC-Style Processor Design
– Five-Stage Organization
– Instruction Execution

• CISC-Style Processor Design

– Multi-Bus Interconnect
– Instruction Execution

• Control Signal Generation

CSCI2510 Lec09: Basic Processing Unit 2024-25 T1 54