8085 Microprocessor

Introduction
●​ Microprocessor is a semi Cond vector component design by using VLSI
technology & it contains ALU, Cu & registers of a CPU in a single
package.​

●​ For a microprocessor, Memory is connected externally

●​ The registers inside the processor can not be treated as memory as they
are used to hold the data temporary.
●​ Bit → Binary digit (0 or 1)
●​ Nibble → 4 - bits
●​ Byte → 8 bits
●​ Word length → depend on type of processor

History of Microprocessors
𝑠𝑡
●​ 1 microprocessor, 1971 → Intel 4004 → 4 bit
𝑛𝑑
●​ 2 microprocessor, 1972 → Intel 8008 → 8 bit
 𝑟𝑑
●​ 3 microprocessor, 1974 → Intel 8080 → 8 bit
𝑡ℎ
●​ 4 microprocessor, 1977 → Intel 8085 → 8 bit
𝑡ℎ
●​ 5 microprocessor, 1978 → Intel 8086 → 16 bit

Note

Microprocessor Word length Memory capacity

Intel 4004 (PMOS) 4 - bit 640 B

Intel 8008 8 -bit 16 kB

Intel 8080 (NMOS) 8 -bit 64 KB

Intel 8085 (NMOS) 8 − 𝑏𝑖𝑡 64𝐾𝐵

Intel 8086 (HMOS) 16-bit 1 MB

Intel 8088 8/16-bit 1 MB

Intel 80186 16-bit 1 MB

Intel 80286 16-bit 16 MB real 44 B virtual

Intel 80386 32 − 𝑏𝑖𝑡 44 B real, 4 GB virtual

Intel 80486 32 − 𝑏𝑖𝑡 4 GB real 64 TB virtual

Pentium - Il 64 - bit 64 GB real

Z-80 8 -bit 64𝐾𝐵

Z-800 8-bit 500 KB

●​ Most of the general purpose Microprocessors used in the modern world

computers are the family of 8086 .
Difference between Microprocessors & Microcontroller

Microprocessor Microcontroller

It contains ALU, CU & resistors It contains ALU, CU & resistors

 No internal memory It has interfacing circuit

No interfacing circuits i.e, timer /

Has interfacing circuit
counters

Used for general purpose Used for specific Purpose

Application EX: Intel Ex: Intel 8051, 8031 PIC - 8 bit/Is bit
8085, 8086, 𝑀6800, 𝑖3, 𝑖7 AT89C5

Micro-controller

Microprocessor Architecture
●​ Program & data are stored in a memory & it is responsible to operate
microprocessor
●​ Depending on how programmers & data are stored in the memory. They
are of two types of Architecture.

Von - Neumann or Princeton Architecture

Harvard Architecture
Program & data are separately present is different
Program & data both are present in same memory Program & Data Ex: Intel
8085, Intel 8086

Memory​
Program​
Memory​
Data​
Ex: Intel 8051 (MC)

Basic Operation

●​ Opcode fetch → Reading or accessing instruction i.e, opcode from

memory into the processor.
●​ Memory read → Reading or accessing data from memory
●​ Memory write → Sending or transferring data to memory
●​ I/O read → Reading or accessing data from input device or port Here, part
indicates connection of am I/O device.
●​ I/O write → Transferring data to output part or device.
Note:- The above 5 operations are called machine cycle or time processing

System Bus
●​ Bus is a group of conductor or wires used for communication between
processor, Memory & input output devices.

Three types of Bus →

(i) Address Bus

●​ It is used to transfer the address of either memory or input & output
devices from the processor.
●​ It defines the maximum memory that can be connected for as processor
given by the relation.
𝑛
Where, 2 = 𝑁​
𝑛 = number of address line​
𝑁 = number of address memory location.
 ●​ It is of 16 bit in length for 8085 microprocessor
●​ It is unidirectional.

(ii) Data Bus

●​ If is used to transfer data between processor, memory and I/O devices.
●​ It is of 8 bit in a length for 8085 .
●​ It is bidirectional.
●​ There is not separate date bus in 8085 . The Lower ' 8 ' address line can
be used either as address or data bus with the help of signal known as.
ALE (Address Latch Enable).

ALE

If all high : All i6 lines is Address bus

If one is zero or low:

𝐴15 − 𝐴8 is Address bus

𝐴𝐷7 − 𝐴𝐷0 is Date bus

𝐴15 − 𝐴8 𝐴𝐷7 − 𝐴𝐷0

ALE → 1: Higher order address bus Lower order Address bus

ALE → 0: Address bus Date bus

(iii) Control Bus

●​ It is a group of different control signals required for various operations of
the processor.
●​ It is partially unidirectional & partially bi - directional.
●​ ALE, 𝑅𝐷, 𝑊𝑅
Note:- If partially unidirectional & partially bi - directional is not given in the
options than prefer unidirectional.

Memory
 ●​ Memory is a group of register, a register is a group of flip-flap, a flip-flap is
a memory cell which can store a bit.
●​ Most of the memories are designed to store or hold 8 bits per each
registers or memory location or Address location.
●​ Memory is represented in terms of bits.
●​ Maximum memory that can be connected to 8085 is 64 KB​

●​ Relationship between address line & memory-

𝑛
2 = 𝑁
Where,​
𝑛 = number of address line 𝑁 = number of address or memory location.

Note - Address of the memory locations are not stored in memory. It stored in
processor.

●​ Memory has separate address line & separate data lines.

●​ Processor does not have separate address & reports data lines.
●​ The lower eight lines are multiplexed.
𝐿𝐴𝑇𝐶𝐻 →
●​ Latch is an interfacing component as the data is present on the bus for
very few microsounds.
 ●​ It is used to hold the value for some time such that output units like
display, Memory etc. can recognize the data. Ex :- 7415373

Representation of a Memory Chip

𝑚×𝑛
​
Where,

𝑀 = 𝑁𝑜 𝑜𝑓 𝑎𝑑𝑑𝑟𝑒𝑠𝑠 𝑜𝑟 𝑚𝑒𝑚𝑜𝑟𝑦 𝑙𝑜𝑐𝑎𝑡𝑖𝑜𝑛 𝑁 = 𝑛𝑜 𝑜𝑓 𝑏𝑖𝑡𝑠 𝑜𝑟 𝑙𝑜𝑐𝑎𝑡𝑖𝑜𝑛.

Internal Architecture

Register Unit
●​ There are two types of registers
1.​ General purpose registers - There are six 8 - bit general purpose register.
●​ They can also be used as 16 bit register i.e., register pair.
●​ They are three register pair namely - BC, DE, & HL
●​ Any of the register pair can be used to point to the memory but 'HL' pain
Ps known as default memory or data pointer.
●​ EX. MOV C, M
●​ Here, ' M ' indicates memory contained or resistor whose address is
present in HL pair only.

Accumulator (A)
1.​ Accumulator is a 8-bit multipurpose register by which almost all Arithmetic
& logic operational ore preferred.
The result of an operation is stored in the accumulator.​
2. Special purpose registers- There are two 18-bits special purpose register
called program counter. (pc) & stock pointer (sp).

(i) Program Counter (PC) -

●​ It is a 16 - bit special purpose register used to sequence the execution of
programmer.
●​ The function of the program counter is to point to the memory address
from which the next byte is to be fetched.
●​ When the microprocessor is reset, the PC sets to Zero.
●​ Instruction register- It is a 8 - bit register which contain op - code of
present instruction. It does not contain data.
 ●​ After the op-code is fetched into Instruction register, it is forwarded into
decoder
●​ Op-code is decoded with the help of micro-program.​
(ii) Stack Pointer (SP)-
●​ It is a 16-bit special purpose register which contains the address of data
present at top of the sock or it points to top of stock memory.
●​ Stock is a part of read, write memory which is used to store temporary
data & also the content of program counter when subroutines are used.
●​ Stock grows from bottom to top following LIFO (Last In First out) structure
& the SP contains keep decreasing as the stack grows.
●​ When data is stored or into stack memory stack pointer is decremented.
●​ When data is access from stack memory stack pointer is incremented.
●​ A single register data cannot be stored is stock memory.

Flag Register
●​ Flag register is a 8 - bit register.
●​ There are five Hag in 8085 which indicate the status after an Arithmetic &
logic operation.
●​ Hags are affected by the content of accumulator for most of the ALU
operation in some instructions they only also be modified for general
purpose registers.
●​ Flags are affected or modified only for operations.
●​ Example: Increment & Decrement.

Rules
●​ In signed operations;​
𝑆 → 0; (+ )𝑣𝑒 result​
𝑆 → 1; (− )𝑣𝑒 result

●​ If​
𝑍 → 1; if result in ' A ' = 𝑂𝑂𝐻​
𝑍 → 0; otherwise
●​ If 𝐴𝐶 → 1; If there is a carry from 𝐷4 bit ← 𝐷3 bit or Higher nibble ← lower
nibble 𝐴𝐶 → 𝑜; otherwise
●​ If 𝑃 → 1; if no of binary ' 1 ' in 𝐴 is even 𝑝 − 0; if no of binary ' 1 ' in 𝐴 is
odd.
 ●​ If 𝑐𝑦 → 1; if these is a carry i.e, out of 𝐷7 bit​
𝑐𝑦 → 0; otherwise

Program status word (PSW)

●​ PSW is a combination of accumulator and Hag register together where
accumulator is high ' 𝐹 ' byte.

Temporary Register-
●​ The temporary registers W&Z are used to store data/address temporarily.
●​ They are two 8-bit temporary registers which are not accessible by the
user.
●​ This register is also called Invisible register because they are not available
for user during programmer.

Time & Control Unit

●​ It is responsible for generating various control timing & status signal
required for operating for the processor.
●​ Two pins ( 𝑥1, &𝑋2 ) a crystal oscillator (provide stable oscillation)
connected between these pins to provide reference fervency for the
processor.
●​ Crystal is used as it produces stable oscillations compared to RC & LC
oscillators, which are temperature dependent
𝑓𝑜𝑟𝑦𝑠𝑡𝑎𝑙
𝐹𝑐𝑙𝑘 = 2

●​ ​
𝑓𝑐𝑙𝑘 = 3𝑀𝐻3 (operating frequency)​
Range = 3 to 6𝑀𝐻3

Address Latch Enable (ALE)

●​ ALE is used to make 𝐴𝐷7 − 𝐴𝐷0 either as a address or data bus.

●​ ALE 1 ; A11 16 lines → Address bus, 0; 𝐴15 − 𝐴8 Address bus,

𝐴𝐷7 − 𝐴𝐷0 → Data bus.

●​ 𝑅𝐷 = Read control signal​

0 → Active​
1 → Inactive​
𝑊𝑅 = Write control signal​
 0 → Active​
1 → Inactive​
IO/M = status signal which indicates memory of I/O operation​
𝐼𝑂/𝑀‾ = 0; memory operation, 1 ; IO operation

Control
10/𝑀 𝑅𝐷 𝐷𝑅 Operation
signal

Memory
0 0 1 M/M Read
Read

Memory
0 1 0 M/M write
write

1 0 1 I/OR I/O Read

1 1 0 I/ O W I/O write

𝑆 𝑆0 status line - There give the status of bus cycle for operation
1

𝐼𝑂/𝑀 S1 S2 States

𝑍 0 0 Halt

0 0 1 Memory write

0 1 0 Memory Read

0 1 1 Fetch

1 0 1 I/O write

1 1 0 I/O Read

1 1 1 INIA

𝑍 𝑋 𝑋 Hold

𝑍 𝑋 𝑋 Reset

Where, Z is High impedance state

HOLD
●​ This indicates if any other device is requesting the use of address & data
bus. Then microprocessor transfers the control to the requesting device as
soon as the current cycle is over.
●​ After the process of requesting deceive is over, the control is transferred
black to the microprocessor.

HLDA
●​ HLODA is the acknowledgement signal for HOLD.
●​ It indicates whether the HOLD signal is received or not.
●​ After The execution of HOLD request, HLDA goes low.​

●​ Purpose of DMA → when more data is to be transferred between memory

& 1/0 at a faster rate, direct memory Access (DMA) operation is used with
the help of DMA controls.
 ●​ Modes of DMA →
1.​ Burst mode - Hold signal remain High unless until total data transfer.
During there period, the processor is present in WAIT/IDLE state. Therefore,
interference is more.

2. Cycle stealing technique / short burst mode-

The total data to be transferred is divided into blocks. Blocks are transferred in a
sequence of intervals of time.

The processor is interrupted only when true is a data transfer.

Interference is less.​
EX: - Audio & file transfer application in a computer.​
3. Inter leaved DMA → In both burst & cycle stealing techniques, the processor is
present in wait state.

Reset - in - Low active input signal to reset the processor & PC is initializing to
oooH​
Reset - Out - Output signal which indicates that processor is reset. It can be used
to reset IO devices.​
Clock - Out -Output pin on which the same operating frequency of the processor
is available It can be connected to clock input for a synchronous operation.

Ready - High Active input signal to the processor from a slow speed I/O If ready
is high, then only the processor will either transmit data to or receive data from
I/O device.

Interrupts of 8085
Interrupts is a method by which the I/O device informs the processor that it
requires the service of the processor.

Classification of Interrupts
●​ Hardware interrupts - 8085 has 5 hardware interrupts or external interrupts​
Non-Vectored Interrupt

Software interrupts
●​ Their interrupts are available in the form of instruction.
●​ 8085 has 8 software interrupts.​

Mask able Interrupts

Interrupts which can be ignored or avoided even if they are triggered are
mask-able.

Now - Mask able interrupts

Interrupts which cannot be ignored or avoided when triggered.​
Note: - TRAP is the only non - mask-able interrupt in 8085 It must be connected
to highly prioritized events in practical applications.

Vectored interrupts
Interrupts which have specific address location in the memory are vectored.

Non - Vectored Interrupts

Interrupts which do not have specific address location in the memory are non -
vectored.​
EX: - INTR is the only Non - vectored interrupt in 8085.

Note

Type of
Priority Interrupts Vector Address
triggering

Level & edge

1 TRAP 0024 H
triggering

Only edge
2 RST 7.5 003 CH
triggering

Only level
3 RST 6.5 0034 H
triggering

Only level
4 RST 5.5 002 CH
triggering

Only level
5 INTR -
triggering

Interrupt Service Routines (ISR)

●​ It is a program that is executed in response to an interrupt
●​ Every vectored Interrupt is assigned 8 bytes in a memory to store the
corresponding ISR.
 ●​ If the length of ISR is more than 8 bytes or when both Hardware &
software interrupts are required an unconditional jump instruction can be
used such that the program may be continued fretter.

TRAP -
●​ TRAP is both edge & level triggered.
●​ It may respond quickly.
●​ It differentiate original signal from practical application & error signal due
to noise.
INTER - 𝐼𝑁𝑇𝑅

●​ 𝐼𝑁𝑇𝑅 Generates the pulse only to recognize the INTR interrupt.

●​ 𝐼𝑁𝑇𝑅 is required only for INTR not for vectored interrupt.
●​ In order to use INTR, the programmer most select one of the software
interrupt address to store ISR of I/O device.

Instructions Related to Interrupt -

●​ El (Enable interrupt) - Used to enable Mask able interrupt
●​ DI (Disable interrupt) - Used to disable mask able interrupt
●​ SIM (Set Interrupt mask) - Use to mask the interrupts or make then
available.
RIM (Read Interrupt Mask) - Used to know the states of pending Interrupts.​
NOTE: the above instruction are valid only for mask able interrupts. TRAP cannot
be Enable or disable.

PROGRAMMING MODEL
●​ Program is a set of instruction.
●​ Instruction is command given to computer to perform specific task.
●​ Machine level language is a binary medium of communication with a
computer through a design set of instructions.
●​ Assembly level language in which instructions are written in separate
words known as ‘Mnemonics’
●​ Both Assembly & Machine level languages are together known as Two -
level language which are machine dependent.
●​ Overall cycle of writing the program till execution.​
 ●​ Op - code fetch, Decode & Execute are the basic steps of execution of an
Instruction.
●​ Monitor program is similar to operating system software. It is used in
microprocessor based system.

Instruction Format
Op - code Operands​
Where,

●​ Op - code indicates the type of operation to be performed for an

instruction.
●​ Operand is data on which operation is to be performed.

Length of an Instruction
●​ Number of bytes occupied by the instruction in the memory
 ●​ Three are three types of instruction classified according to length.​
(i) 1 - Byte instruction :
Ex:

●​ Mov-Op-code
●​ A, C - Operands​
(ii) 2 - Byte instruction :
Ex.

●​ MVI B, 77H​
(iii) 3 - Byte instruction :
Ex:

●​ LXI H - Opcode (1 Byte)

●​ 9080 H - Operands (2 - Byte)

Memory Rule
●​ In all memory related operations, the data present in lower byte of register
is transferred to the lower address location.
●​ Higher byte or higher register content is transferred to higher address
location or vice - versa.

Standard Codes
𝐵 → 000
𝐶 → 001
𝐷 → 010
𝐸 → 011
𝐻 → 100
●​ L → 101
𝐴 → 111
Memory (M) → 10

𝐵𝐶 → 00
●​ DE → 01
𝐻𝐿 → 10
𝑆𝑃 → 11
Addressing Modes
These are various formats specify the operands or they indicate how data is
accessed for instructions. There are five type of Addressing mode.​
i. Immediate Addressing mode - Data is present in the instruction itself.​
ii. Direct Adorning mode - Address of the data is present in the instruction.​
iii. Indirect Addressing mode - Address of the data is present as the content of
another register pair.​
iv. Register addressing mode - Data is transferred between registers.​
v. Implicit / Implied addressing mode - No operand or data is preset in an
instruction but some kind of operation is performed by the instruction.

Timing diagram →
●​ Timing diagram is pictorial representation of execution of an instruction
with the help of various timing control and status signal.
●​ T-state is one sub - division of an operation performed in 1 clock period.
●​ Machine cycle - It is defined as the time required to access either memory
& I/O.
●​ 1 Machine cycle may have 3-6T-State.
●​ Instruction cycle - It is defined as the time required to complete the
execution of an instruction. one instruction cycle may have one to five
Machine cycles.
Note :- The maximum 𝑇 - state possible for execution of an instruction in 8085 is
18

●​ Steps of execution is (i) Fetch (ii) Decode (iii) Execute

Diagram

Instruction Set Classification

Type of operation Length of instruction

(i) Data transfer (copy) instruction (i) 1 Byte instruction

(ii) Arithmetic instruction (ii) 2 Byte instruction

(iii) Logical instruction (iii) 3 Byte instruction

(iv) Branching instruction

(v) Machine Control instruction

Data transfer or copy instruction
●​ In this group, the data is transferred from one location i. e., Source to
another location i.e destination.
●​ It may be between -​
a. Register to register​
b. Register to Memory​
c. Register to I/O​
d. Register to data

Terminology used in data transfer instructions -

𝑀 → Move​
I → Immediate​
𝑅𝑃 → Register pair​
𝑋 → Operation on 𝑅𝑃​
[ ] → Content of​
[[ ]] → Reference or content​
𝐿 → Load​
𝑠 = Store​
IN 8 bit port address, [A] data I/P device (I/O Read)​
Out 8 bit port address, [A] O/P device​
[ ]
Push 𝑅𝑝 : 𝑅𝑝 Stack Memory​
POP 𝑅𝑝: [𝑅𝑝] data from stack

Syntax Operation

MVI r, data B 𝑟 <= data 8

𝐿 × 𝐼𝑟𝑝, NUM 16 (𝑟𝑝) < NUM 16

MVP M, data 8 ((𝐻𝐿)) <= data 8

MOV rd 𝑟𝑠 (𝑟𝑑) <= (𝑟𝑠)

SPHL (𝑆𝑃) <= (𝐻𝐿

PCHL (𝑃𝐶) <= (𝐻𝐿)

XCHG (DE) <=> (𝐻𝐿)

OUT Add 8 (Add 8) <= (𝐴)

 IN Add 8 (A) < = (Add 8)

MOV M,r ((𝐻𝐿)) <= (𝑟)

MOV r,M (𝑟) <= ((𝐻𝐿))

STAX 𝑟𝑝 ((𝑟𝑝)) <= (𝐴)

LDAX 𝑟𝑝 (A) <= ((𝑟𝑝))
LDA Add 16 (A) (Add 16)

STA Add 16 (Add 16) < = (A)

( 𝐴𝑑𝑑 16) <= (𝐿) ( 𝐴𝑑𝑑 16 + 1) <= (𝐻

SHLD Add 16
2 memory write operation.

(𝐿) = ( 𝐴𝑑𝑑 16) (𝐻) = ( 𝐴𝑑𝑑 16 + 1)

LHLD Add 16
2 Memory Read operation

PUSH 𝑟𝑝
( )
((𝑠𝑝) − 1) = 𝑟𝐻 ((𝑠𝑝) − 2) = 𝑟𝐿 ( )
(SP) decremented by 2

(𝑟𝐿) = ((𝑠𝑝)) (𝑟𝐻) = ((𝑠𝑝) + 1)

POP 𝑟𝑝 (𝑠𝑝)
incremented by 2

(𝑇𝑜𝑠) <=> (𝐻𝐿) 𝑇𝑜𝑠 = 𝑇𝑜𝑝 𝑜𝑓 𝑡ℎ𝑒 𝑠

𝑠𝑝
XTHL
is unchanged after execution PoPh
followed by PUSH H

Remember:-
●​ In almost all data transfer operation the contain of source is unchanged
after the execution
 ●​ Flags are not affected for execution of data transfer group of instruction,
since ALU is not involved.

Arithmetic instruction:
●​ There is no multiplexer or division operation is supported by 8085
●​ 8085 microprocessor has accumulator based ALU​
(a) Addition; ADD C​
(b) Subtraction; SVB M​
(c) Increment; INX H​
(d) Decrement; DCR M

Syntax Operation

Add r (𝐴) = (𝐴) + (𝑟)

DAA Decimal adjust after addition

DAD 𝑟𝑝 ( )
(𝐻𝐿) + 𝑟𝑝 = (𝐻𝐿)

ADC r (𝐴) = (𝐴) + (𝑟) + (𝐶𝑌)

ADD M (𝐴) <= (𝐴) + ((𝐻𝐿))

ADC M (𝐴) <= (𝐴) + ((𝐶𝐻𝐿)) + (𝐶𝑌)

ADI data 8 (𝐴) <= (𝐴) + data 8

ACI data 8 (𝐴) <= (𝐴) + data 8 + (𝑐𝑦)

SUB r (𝐴) <= (𝐴) − (𝑟)

SUB r (𝐴) <= (𝐴) − (𝑟) − (𝑐𝑦)

SUB M (𝐴) <= (𝐴) − ((𝐻𝐿))

SUB M (𝐴) <= (𝐴) − ((𝐻𝐿)) − (cy)

SUI data 8 (𝐴) <= (𝐴) - data 8

SBI data 8 (𝐴) <= (𝐴) − data − (𝐶𝑌)

INR r (𝑟) <= (𝑟) + 1

 INX 𝑟𝑝 (𝑟𝑝) <= (𝑟𝑝) + 1
INR M (𝑀) <= ((𝐻𝐿)) + 1

DCR r (𝑟) <= (𝑟) − 1

DCR 𝑟𝑝 (𝑟𝑝) <= (𝑟𝑝) − 1

DCR M (𝑀) <= ((𝐻𝐿)) − 1

Note:
●​ DAD instruction is a special instruction for performing 16 bit addition
●​ Microprocessor uses 2's compliment technique for subtraction operation
●​ After subtraction operation carry flag is to be complemented
●​ If 𝐶𝑌 = 1 then result in accumulator is positive
●​ If 𝐶𝑌 = 0 then result in accumulator is negative
●​ INR & DCR instruction effects all flags except CY flag
●​ For DAD Accumulator is unchanged after the operation IF there is carry
out of 16 − 6π carry flag is affected remaining flags are unchanged.

Logical Instruction:

Syntax Operation

AND accumulator with 𝑟

ANA r
(𝐴) <= (𝐴) ∧ (𝑟)

ANA M (𝐴) <= (𝐴) ∧ ((𝐻𝐿) )

ANI data 8 (𝐴) <= (𝐴) ∧ data 8

ORA r (A) <= (𝐴) ∨ (𝑟)

ORA M (𝐴) <= (𝐴) ∨ ((𝐻𝐿) )

ORI data 8 (𝐴) <= (𝐴) ∨ data

XRA r (𝐴) <= (𝐴) ∨ (𝑟)

 XRA M (𝐴) <= (𝐴) ∨ ((𝐻𝐿) )

XRA data 8 (A) <= (A) ∨ data 8

CMP r (A) - (r)

CMP M (A) - ((HL))

CPI data 8 (A) - data 8

CMA Complement contents of accumulator

CMC 𝐶𝑌 <= 𝐶𝑌

STC 𝐶𝑌 <= 1

RLC Rotate accumulator left

RAL Rotate accumulator left through carry

RRC Rotate accumulator right

Rotate accumulator right through

RAR
carry.

Note:
●​ For CMP M operation result are not stored in ' 𝑀 ' it differs from SUB
instruction. Ned to check status from flags.
●​ CMA instruction is used for 1's compliment performing.
●​ Rotate operations include only change of carry flag. No other flags are
affected using rotate operation.
●​ For any AND operation; 𝐴𝐶 = 1&𝐶𝑌 = 0
●​ For any 𝑂𝑅 operation; 𝐴𝐶 = 0&𝐶𝑌 = 0

𝑍 𝐶𝑌 (𝐴) − (𝐵) Result

1 0 Zero (𝐴) = (𝐵)

0 0 Positive (𝐴) > (𝐵)

 0 1 Negative (𝐴) < (𝐵)

●​ Sign flag depends on the subtraction of (𝐴) − (𝐵)

Rotate:-
●​ Only possible with ' A ' content
●​ Only 'CY' is affected
RLC: - Rotate the content of Accumulator one bit left without carry.​

RAL: - Rotate the content of Accumulator one bit left with carry​

RRC: - Rotate the content of Accumulator one right without carry​

RAR: - Rotate the content of accumulator one right with carry​

Application:
●​ They are used to find (+) ve and (-) ve, even & odd number, multiplication
& division & also for serial communication

Branching Instruction:
●​ In this group, the control of program is transferred from one location to
another conditionally or unconditionally

Conditional Instruction:
●​ They depend on status of flags effected for previous ALU operation
(except Auxiliary) carry flag (AC)

True condition:
●​ Control of the program is transferred to 16 bit address & execution
continues.
False condition:
●​ Control of the program is transferred to very next instructions

Unconditional instructions:
●​ Control of the program is transferred to 16 bit address unconditional. E.g.
Jump, call, Return.

Jump instruction:
●​ They are used to transfer the control of program from one location to
another conditionally or unconditionally.

Conditional Jump Instruction:

●​ True condition: Three machine cycle i.e IOT states are required
●​ False condition: Two machine cycle i.e 7 T-state are required.
Note: - (For only false) = one machine cycle is wasted even the condition is false.

●​ There are 9 Jump instruction (8-conditional & 1 -unconditional) and each

instruction require 3 - machine cycle Hence, total machine cycle required
to execute all 9 − jump instruction = 9 × 3 = 27 machine cycles.
●​ If the content of register ' c ' is ' 𝑛 ' the load executes for 𝑛-times where the
condition is true for ( 𝑛 − 1 ) times & false only once.
●​ If ' 𝑐 ' has ' 𝐹𝐹 ' the loop runs for 255 times
●​ IF ' 𝑐 ' has 'oo' the loop runs for 256 times
●​ The length of the program is 7 bytes.
Total execution time ( T )​
𝑇 = 𝑇𝑂𝐿 + 𝑇𝑊𝐿

●​ ​
where,
𝑇𝑜𝐿 = 𝑡𝑖𝑚𝑒 𝑓𝑜𝑟 𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛 𝑜𝑢𝑡 𝑜𝑓 𝑙𝑜𝑜𝑝

𝑇𝑤𝐿 = time for instruction within the loop​

1
𝑇𝑜𝐿 = 𝐹𝑐𝑙𝑘
× (𝑇 − state ) × ( count value )
 Microprocessor
Module 1: Introduction to Microprocessor and Microcomputer Architecture
1. Microprocessor Basics
●​ Definition: A microprocessor is a programmable electronic chip that functions as
the central processing unit (CPU) of a computer. It performs arithmetic and logic
operations, decision-making, and data processing.
●​ Microcomputer: A microprocessor-based system with limited resources.
Examples include embedded systems in devices like washing machines and
mobile phones.

Microprocessor-based system
2. Key Concepts
●​ Bit and Word:
○​ Bit: Smallest unit of data in computing, represented by 0 or 1.
○​ Word: A fixed-sized piece of data handled as a unit by the microprocessor
(e.g., 16-bit, 32-bit).
●​ Bus System:
○​ Data Bus: Carries data between the processor, memory, and peripherals.
○​ Address Bus: Transmits the address of the data.
○​ Control Bus: Manages control signals and the coordination of different
parts of the computer.
3. Microprocessor Architecture
●​ ALU (Arithmetic and Logic Unit):
○​ Performs arithmetic (addition, subtraction) and logic operations (AND,
OR).
○​ Stores result in the accumulator.
●​ Registers:
○​ General-Purpose Registers: Six 8-bit registers (B, C, D, E, H, L) that can
form 16-bit register pairs (BC, DE, HL).
○​ Accumulator (A): An 8-bit register used for arithmetic and logic
operations.
 ○​ Flag Register: Consists of five flags (Zero, Sign, Parity, Carry, Auxiliary
Carry) that indicate the outcome of operations.
●​ Control Unit: Directs the operation of the processor by generating control
signals.
4. Microprocessor Classification
●​ Data Bus Width:
○​ 4-bit, 8-bit, 16-bit, 32-bit processors: Refers to the size of the data bus,
determining how much data can be processed at a time.
●​ Application-Based:
○​ General-Purpose Microprocessors: Used in general computing (e.g.,
Intel Pentium).
○​ Microcontrollers: Integrated with memory and I/O ports for specific
control applications (e.g., 8051).
○​ Special-Purpose Processors: Designed for specific tasks like signal
processing (DSPs, ASICs).
●​ Architecture-Based:
○​ RISC (Reduced Instruction Set Computer): Simplified instructions for
fast execution.
○​ CISC (Complex Instruction Set Computer): More complex instructions
that can perform multiple operations.

Module 2: 8085 Microprocessor Architecture

 Internal Architecture of 8085
1. Overview
●​ 8085 Microprocessor:
○​ 8-bit processor with a 16-bit address bus.
○​ Can address up to 64KB of memory.
○​ Operates at a maximum clock frequency of 3 MHz.
2. Internal Architecture​

●​ Registers:
○​ Accumulator (A): Core register for arithmetic operations.
○​ Flag Registers:
 Flag register
■​ Zero (Z) Flag: Set to 1 if the result of an operation is zero.
■​ Carry (CY) Flag: Set to 1 if an arithmetic operation results in a
carry out of the most significant bit.
■​ Sign (S) Flag: Copies the most significant bit of the result to
indicate its sign (1 for negative, 0 for positive).
■​ Parity (P) Flag: Set to 1 if the result has an even number of 1s.
■​ Auxiliary Carry (AC) Flag: Set to 1 if there is a carry from bit D3 to
bit D4.
○​ General Purpose Registers: B, C, D, E, H, L, used for temporary data
storage.
○​ Stack Pointer (SP): Points to the top of the stack, a special region in
memory used for temporary storage during function calls.
○​ Program Counter (PC): Holds the address of the next instruction to be
executed.
●​ Instruction Set:
○​ Data Transfer: MOV, MVI (move instructions).
○​ Arithmetic: ADD, SUB, INR, DCR.
○​ Logical: ANA, XRA, CMP.
○​ Branching: JMP, CALL, RET, conditional branches.
○​ Machine Control: HLT, NOP (No Operation), DI (Disable Interrupts), EI
(Enable Interrupts).
●​ Timing and Control Unit:
○​ Generates control signals for data bus, address bus, and control bus
coordination.
○​ Controls machine cycles: Fetch, decode, and execute.
3. Instruction Cycle

●​ Fetch-Decode-Execute:
○​ Fetch: Retrieve the instruction from memory.
○​ Decode: Interpret the instruction.
○​ Execute: Perform the operation.
4. 8085 Pin Configuration and Signals

8085 microprocessor pin layout and signal groups

●​ Address and Data Buses:
○​ A8-A15: High-order address bus.
○​ AD0-AD7: Multiplexed address and data bus.
●​ Control & Status Signals:
○​ ALE (Address Latch Enable): Distinguishes between address and data
on the multiplexed bus.
○​ RD̅ (Read): Indicates data is being read from memory or I/O.
○​ WR̅ (Write): Indicates data is being written to memory or I/O.
○​ IO/M, S1 and S0: Status signals.

SI S0 States

0 0 Halt

0 1 Write
 1 0 Read

1 1 Fetch

Status signals and associated operations

●​ Power and Clock:
○​ Vcc: +5V power supply.
○​ Vss: Ground reference
○​ X1, X2: Connections for an external clock crystal to set the operating
frequency.
○​ CLK: Clock output
●​ Externally Initiated and Interrupt Signals
○​ RESET IN̅: When this pin's signal is low, the Program Counter (PC) is set
to 0, buses are tri-stated, and the processor is reset.
○​ RESET OUT: This signal indicates that the processor is being reset and
can be used to reset other devices.
○​ READY: When this signal is low, the processor waits for an integral
number of clock cycles until it goes high.
○​ HOLD: This signal indicates that a peripheral device, like a Direct Memory
Access (DMA) controller, is requesting the use of the address and data
buses.
○​ HLDA (Hold Acknowledge): This signal acknowledges the HOLD
request.
○​ INTR (Interrupt Request): A general-purpose interrupt signal.
○​ INTA̅ (Interrupt Acknowledge): This signal is used to acknowledge an
interrupt request.
○​ RST 7.5, RST 6.5, RST 5.5 (Restart Interrupts): These are vectored
interrupts with higher priority than the INTR interrupt.
○​ TRAP: This is a non-maskable interrupt with the highest priority.
●​ Serial I/O Signals
○​ SID (Serial Input Data): This is the serial input signal. A bit on this line is
loaded into the D7 bit of register A using the RIM (Read Interrupt Mask)
instruction.
○​ SOD (Serial Output Data): This is the serial output signal. The output
SOD can be set or reset using the SIM (Set Interrupt Mask) instruction.

Module 3: Instruction Set and Execution in 8085

1. Instruction Set Classification
●​ Data Transfer Instructions:
 ○​ MOV: Copy data between registers.
○​ MVI: Move immediate data into a register.
●​ Arithmetic Instructions:
○​ ADD, SUB: Basic arithmetic operations.
○​ INR, DCR: Increment and decrement.
●​ Logical Instructions:
○​ ANA: Logical AND.
○​ XRA: Logical XOR.
○​ CMP: Compare registers.
●​ Branching Instructions:
○​ JMP: Unconditional jump.
○​ CALL: Call a subroutine.
○​ RET: Return from a subroutine.
●​ Machine Control Instructions:
○​ NOP: No operation, used for timing adjustments.
○​ HLT: Halt the processor.
2. Addressing Modes
●​ Immediate Addressing: Operand is specified in the instruction itself.
○​ Example: MVI A, 05H (Move 05H to Accumulator A).
●​ Register Addressing: Operand is in one of the registers.
○​ Example: MOV A, B (Copy the content of register B to A).
●​ Direct Addressing: The address of the operand is given explicitly.
○​ Example: LDA 2000H (Load the content of memory location 2000H into
A).
●​ Indirect Addressing: The address of the operand is specified in a register pair.
○​ Example: MOV A, M (Move the content of the memory location pointed to
by HL to A).
●​ Implicit Addressing: The operand is implied in the instruction.
○​ Example: CMA (Complement the content of the accumulator).

Module 4: Instruction Execution and Timing Diagram

1. Instruction Cycle
●​ Instruction Cycle: The time taken to fetch, decode, and execute an instruction.
○​ Machine Cycle: The time required to complete one operation (e.g.,
memory read, memory write).
○​ T-State: One subdivision of the machine cycle, corresponding to one clock
period.
2. Opcode Fetch Cycle
●​ Process:
 ○​ The address of the instruction is placed on the address bus.
○​ The control unit fetches the opcode from memory and places it in the
instruction register.
○​ The instruction is then decoded and executed.
3. Timing Diagrams
●​ Memory Read Cycle: Timing diagram showing how data is read from memory.
●​ Memory Write Cycle: Diagram showing the timing for writing data to memory.
●​ I/O Read/Write Cycle: Diagrams for input/output operations.
4. Example Timing Diagram
●​ IN 80H: Timing diagram for the IN instruction, which inputs data from an I/O port
to the accumulator.

Module 5: Interrupts in 8085

1. Interrupt Structure
●​ Interrupts: Mechanism to handle external or internal events that require
immediate attention.
●​ Types of Interrupts:
○​ Software Interrupts: Triggered by an instruction in the program.
○​ Hardware Interrupts: Triggered by external hardware signals.
○​ Vectored Interrupts: Automatically jumps to a predefined memory
location.
○​ Non-Vectored Interrupts: Requires the interrupting device to supply the
address of the ISR.
○​ Maskable Interrupts: Can be disabled or masked.
○​ Non-Maskable Interrupts: Cannot be disabled.
2. Interrupt Handling
●​ Interrupt Process:
○​ Save the current program state (PC and registers).
○​ Jump to the ISR.
○​ Execute the ISR.
○​ Restore the program state and continue execution.
●​ Interrupt Sources in 8085:
○​ TRAP: Non-maskable, highest priority.
○​ RST7.5, RST6.5, RST5.5: Maskable, vectored interrupts.
○​ INTR: General-purpose interrupt.
Hardware interrupts of 8085

Interrupt Interrupt Maskable or Edge or Level Priority

vector non-maskable triggered
 TRAP 0024H Non-maskable Level 1

RST 7.5 003CH Maskable Rising edge 2

RST 6.5 0034H Maskable Level 3

RST 5.5 002CH Maskable Level 4

INTR Decided by Maskable Level 5

hardware

3. Masking Interrupts
●​ Masking: Selectively disabling specific interrupts.
●​ EI: Enable interrupts.
●​ DI: Disable interrupts.
●​ SIM/RIM Instructions: Set Interrupt Mask and Read Interrupt Mask.

Module 6: 8086 Microprocessor

●​ Type: 16-bit microprocessor.
●​ Address Bus: 20-bit, allowing access to up to 2^20 or 1 MB of memory.
●​ I/O Ports: Supports up to 64K I/O ports.
●​ Registers: Contains 14 registers, each 16-bit wide.
●​ Bus: Multiplexed address and data bus; uses AD0-AD15 and A16-A19.
●​ Power Supply: Requires a +5V power supply.
●​ Package: Available as a 40-pin dual in-line package (DIP).
●​ Clock: Operates with a single-phase clock with a 33% duty cycle.
1. Operating Modes
●​ Minimum Mode: Single microprocessor configuration. Selected by applying logic
1 to the MN/MX# pin.
●​ Maximum Mode: Multi-processor configuration. Selected by applying logic 0 to
the MN/MX# pin.

2. Bus Interface Unit (BIU)

●​ Instruction Queue: Prefetches up to 6 bytes of instructions from memory to
speed up execution, implementing a pipeline architecture.
●​ Segment Registers:
○​ CS (Code Segment): Holds the starting address of the code segment.
○​ DS (Data Segment): Points to the data segment in memory.
○​ SS (Stack Segment): Points to the stack segment.
○​ ES (Extra Segment): Typically used for string operations.
 ●​ Instruction Pointer (IP): Holds the address of the next instruction to be
executed.
●​ Address Calculation: The 20-bit physical address is formed by combining a
16-bit segment address with a 16-bit offset address.
3. Execution Unit (EU)
●​ Control Circuitry: Manages instruction decoding and execution.
●​ ALU (Arithmetic Logic Unit): Performs arithmetic and logical operations.
●​ Instruction Decoder: Converts instructions into executable operations.
●​ Pointer and Index Registers:
○​ SP (Stack Pointer): Points to the current position in the stack.
○​ BP (Base Pointer): Typically used for accessing data on the stack.
○​ SI (Source Index) and DI (Destination Index): Used for indexed
addressing and string operations.
●​ Flag Register: Contains status flags that reflect the outcome of ALU operations
(e.g., Zero Flag, Sign Flag).
4. Bus Interface Unit (BIU) Operations
●​ Prefetching: Instruction bytes are fetched in advance and stored in the
instruction queue, allowing the BIU to look ahead in the program and fetch
instructions during idle periods.
●​ Pipeline Operation: Overlapping of instruction fetch and execution enhances
processing efficiency.
●​ Address Generation: The BIU generates the physical memory addresses by
combining the segment and offset addresses, enabling access to a 1MB address
space.
5. Memory Segmentation
●​ Segments: The 8086 uses four segments (Code, Data, Stack, Extra) to manage
memory. Each segment is 64KB in size.
6. 8086 Register Organization
●​ General-Purpose Registers: AX, BX, CX, and DX, each can be divided into two
8-bit registers (e.g., AX into AH and AL).
●​ Segment Registers: CS, DS, SS, ES—each pointing to different segments in
memory.
●​ Pointer Registers: SP, BP.
●​ Index Registers: SI, DI, used for operations on arrays and strings.
●​ Instruction Pointer (IP): Tracks the next instruction to execute.
●​ Flags Register: 9 status flags indicating conditions like carry, zero, sign, and
overflow.
7. 8086 Pin Configuration
●​ Address/Data Multiplexing: Pins AD0-AD15 are used for both address and
data, with the address being sent first, followed by the data.
8. Minimum and Maximum Mode Operations
●​ Minimum Mode:
○​ Suitable for small systems with a single processor.
○​ Provides all necessary control signals internally.
●​ Maximum Mode:
○​ Suitable for systems with multiple processors.
○​ Requires an external bus controller (8288) to generate control signals.
9. Instruction Set and Execution
●​ Instruction Pipeline: Allows prefetching of instructions to speed up execution.
●​ Clock Cycles: Execution of instructions involves multiple clock cycles, with
different stages for fetching, decoding, and executing.
Bus Arbitration and Control in Maximum Mode
●​ Bus Controller (8288): Generates command signals like memory read/write and
I/O read/write.
●​ Bus Arbitration: In a multiprocessor system, the 8086 uses bus arbitration to
control access to shared resources.

8051 Microcontroller Overview

The 8051 microcontroller is one of the most widely used microcontrollers in embedded systems.
Its architecture, memory management, and features make it a powerful tool for controlling
various electronic devices.

Key Features:

●​ 8-bit CPU: The microcontroller can handle 8-bit data at a time.

●​ 16-bit Program Counter (PC): This allows the 8051 to address up to 64KB of memory.
●​ 8-bit Stack Pointer (SP): Points to the top of the stack in RAM.
●​ 128 bytes of Internal RAM: Used for storing temporary data during program execution.
●​ 128 bytes of Special Function Registers (SFRs): These registers control specific
functions within the microcontroller.
 ●​ 32 I/O Pins: Organized into four 8-bit ports (P0 to P3), which can be used for various
input/output operations.
●​ Two 16-bit Timer/Counters (T0 and T1): These are essential for timing operations.
●​ Five Interrupts: Including two external and three internal interrupts.
●​ Full-Duplex Serial Communication: Facilitates serial communication via a built-in serial
port.

8051 Microcontroller Pin Diagram:

Pins 1 - 8 (PORT 1):

●​ Pins 1 to 8 are the PORT 1 Pins of 8051.

●​ PORT 1 Pins consists of 8 - bit bidirectional Input / Output Port with internal pull-up resistors.
●​ In some of the newer 8051 Microcontrollers, few PORT 1 Pins have dual functions. P1.0 and
P1.1 act as Timer 2 and Timer 2 Trigger Input respectively.​

Pin 9 (RST):

●​ Pin 9 is the Reset Input Pin.

●​ It is an active HIGH Pin i.e. if the RST Pin is HIGH for a minimum of two machine cycles, the
microcontroller will be reset. During this time, the oscillator must be running.​

Pins 10 - 17 (PORT 3):

 ●​ Pins 10 to 17 form the PORT 3 pins of the 8051 Microcontroller.
●​ PORT 3 also acts as a bidirectional Input / Output PORT with internal pull-ups.
●​ Additionally, all the PORT 3 Pins have special functions multifunctional for the 8051
microcontrollers.

Architecture:

The 8051 architecture is designed to be efficient and straightforward, making it ideal for a range
of applications. It includes:

●​ Accumulator (A): Used for arithmetic operations.

●​ B Register: Primarily used for multiplication and division.
●​ Program Status Word (PSW): Stores the status of the program.
●​ Data Pointer (DPTR): Consists of two 8-bit registers (DPH and DPL) and is used for
addressing external memory.
●​ Port Registers (P0 to P3): Control the I/O ports.

FLAG:

●​ Carry Flag(CY): During addition and subtraction any carry or borrow is generated then
 carry flag is set otherwise carry flag resets. It is used in arithmetic, logical, jump, rotate

and Boolean operations.

●​ Auxiliary carry flag(AC): If during addition and subtraction any carry or borrow is

generated from lower 4 bit to higher 4 bit then AC sets else it resets. It is used in BCD

arithmetic operations.

●​ Overflow flag(OV): If in signed arithmetic operations result exceeds more than 7 bit

than OV flag sets else [Link] is used in signed arithmetic operations only.

●​ Parity flag(P): If in result, even no. Of ones "1" are present than it is called even parity

and parity flag sets. In result odd no. Of ones "1"are present than it is called odd parity

and parity flag resets.

Memory Organization:

The 8051 has two types of memory:

●​ Program Memory (ROM): Used to store the program code. Early models used external
memory for this purpose, but later versions included internal ROM.
●​ Data Memory (RAM): Used for storing data and intermediate results. The internal RAM
is divided into three main areas:
○​ Working Registers: 32 bytes from 00h to 1Fh.
○​ Bit-Addressable Area: 16 bytes from 20h to 2Fh.
○​ General-Purpose RAM: 80 bytes from 30h to 7Fh.

Instruction set of 8051

1. Data Transfer Instructions

These instructions are used to move data from one place to another within the microcontroller.
The common data transfer instructions include:

●​ MOV dest, src: Move data from source to destination.

○​ Example: MOV A, #0x25 (Move immediate value 25h to the accumulator A).
●​ MOVC A, @A+DPTR: Move code byte relative to DPTR and Accumulator.
●​ MOVX A, @DPTR: Move external data pointed by DPTR to the Accumulator.
●​ PUSH direct: Push the direct byte onto the stack.
 ●​ POP direct: Pop the byte from the stack to the direct address.

2. Arithmetic Instructions

These instructions perform arithmetic operations such as addition, subtraction, multiplication,

and division.

●​ ADD A, src: Add the source operand to the accumulator.

○​ Example: ADD A, R0 (Add the contents of register R0 to the accumulator).
●​ ADDC A, src: Add with carry the source operand to the accumulator.
●​ SUBB A, src: Subtract the source operand and the carry flag from the accumulator.
●​ MUL AB: Multiply A and B and store the result in A and B.
●​ DIV AB: Divide A by B and store the quotient in A and remainder in B.
●​ INC dest: Increment the destination operand by 1.
●​ DEC dest: Decrement the destination operand by 1.

3. Logical Instructions

These instructions are used for bitwise logical operations, including AND, OR, XOR, and rotate
operations.

●​ ANL dest, src: Perform bitwise AND operation between source and destination.
○​ Example: ANL A, R1 (AND the contents of R1 with the accumulator).
●​ ORL dest, src: Perform bitwise OR operation between source and destination.
●​ XRL dest, src: Perform bitwise XOR operation between source and destination.
●​ CLR A: Clear the accumulator.
●​ CPL A: Complement the bits of the accumulator.
●​ RL A: Rotate the bits of the accumulator left.
●​ RLC A: Rotate the bits of the accumulator left through the carry.
●​ RR A: Rotate the bits of the accumulator right.
●​ RRC A: Rotate the bits of the accumulator right through the carry.

4. Control Instructions

Control instructions are used for controlling the flow of the program, including jumps, calls, and
returns.

●​ ACALL addr11: Absolute call to a subroutine within the same 2K block.

●​ LCALL addr16: Long call to a subroutine located anywhere in the 64K code memory.
●​ LJMP addr16: Long jump to any location in the 64K code memory.
●​ SJMP rel: Short jump relative to the current PC.
●​ JZ rel: Jump if the accumulator is zero.
●​ JNZ rel: Jump if the accumulator is not zero.
●​ CJNE dest, src, rel: Compare and jump if not equal.
●​ DJNZ reg, rel: Decrement the register and jump if not zero.
5. Bit Manipulation Instructions

These instructions are used to operate on individual bits in the registers or memory.

●​ SETB bit: Set the specified bit to 1.

○​ Example: SETB P1.0 (Set bit 0 of port 1 to 1).
●​ CLR bit: Clear the specified bit to 0.
●​ CPL bit: Complement the specified bit.
●​ ANL C, bit: AND the carry bit with the specified bit.
●​ ORL C, bit: OR the carry bit with the specified bit.
●​ MOV C, bit: Move the specified bit to the carry.
●​ MOV bit, C: Move the carry to the specified bit.

6. Boolean (Bit-Level) Operations

These instructions provide direct control over the individual bits, allowing detailed and efficient
manipulation of data.

●​ JB bit, rel: Jump if the specified bit is set.

○​ Example: JB P1.0, LABEL (Jump to LABEL if bit 0 of port 1 is set).
●​ JNB bit, rel: Jump if the specified bit is not set.
●​ JBC bit, rel: Jump if the specified bit is set, and then clear the bit.

7. Miscellaneous Instructions

These include other operations that do not fit into the above categories.

●​ NOP: No operation. Used for creating delays or for timing adjustments.

●​ SWAP A: Swap the nibbles within the accumulator.
●​ DA A: Decimal adjust the accumulator after addition.