COMPUTER ORGANIZATION (23ISPC205)

Module- 4 – Processing Unit

Q) Explain Single bus organization of data path inside a processor.

Figure shows an organization in which the arithmetic and logic unit (ALU) and all the registers are
interconnected via a single common bus. This bus is internal to the processor.

The address and data lines of the external memory bus are connected to the internal processor bus via
the memory data register, MDR, and the memory address register, MAR, respectively.

The use and number of the processor registers R0 through R(n-1) vary considerably from one processor
to another. Registers may be provided for general purpose use by the programmer. Some may be
dedicated as special-purpose registers, such as index registers or stack pointers. Three registers, Y, S,
and TEMP are never referenced explicitly by any instruction. They are used by the processor for
temporary storage during execution of some instructions.

As instruction execution progresses, data are transferred from one register to another, often passing
through the ALU to perform some arithmetic or logic operation. The instruction decoder and control
logic unit is responsible for implementing the actions specified by the instruction loaded in the 1R
register. The decoder generates the control signals needed to select the registers involved and direct
the transfer of data. The registers, the ALU, and the interconnecting bus are collectively referred to as
the data path.

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Q) Explain the process of fetching a word from memory and storing a word to memory.

Fetching a word from memory:

To fetch a word from memory, the CPU has to specify the address of the memory location where this
information is stored and request a read operation.

The CPU transfers the address of the required word of information to the MAR, which is connected to
address lines of the memory bus. The CPU uses the control lines of the memory bus to indicate a Read
operation is needed.

Then the CPU waits for Read operation completion, which is indicated by Memory-Function
Completed (MFC) signal set.

When the MFC is set, the information on the data lines is loaded into MDR.

The example below demonstrates how to fetch a word from memory location, whose address is
specified in R1, and place the word fetched in R2.

1. MAR ← [R1]
2. Request memory READ and put the data to the address register
3. Wait for the Memory Fetch Cycle (MFC) signal and put the result from [MDR] to R2.
4. R2 ←[MDR]

Storing a word to memory:

To store a word from memory, the CPU has to specify the address of the memory location where this
information is to be stored and initiate a write operation.

The CPU transfers the address where the word to be stored to the MAR, which is connected to address
lines of the memory bus. Then CPU transfers the word to be stored into MDR. The CPU uses the
control lines of the memory bus to indicate a Write operation is needed.

Then the CPU waits for Write operation completion, which is indicated by Memory-Function
Completed (MFC) signal set.

When the MFC is set, the information in MDR is stored into the specified memory address.

The example below shows how the machine stores a word in R2 into a memory location, whose address
is specified in R1.

1. MAR ← [R1]
2. MDR ← [R2]
3. Request memory write
4. Wait for MFC signal

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Q) Explain the process of Register to Register transfers and ALU operations.

Register to Register transfers:

Instruction execution involves a sequence of steps in which data are transferred from one register to
another. For each register, two control signals are used to place the contents of that register on the bus
or to load the data on the bus into the register. This is represented symbolically in below figure.

The input and output of register Ri are connected to the bus via switches controlled by the signals Riin
and Riout respectively. When Riin is set to 1, the data on the bus are loaded into Ri. Similarly, when
Riout is set to 1, the contents of register Ri are placed on the bus. While Riout is equal to 0, the bus
can be used for transferring data from other registers.

Suppose we wish to transfer the contents of register R1 to register R4. This is accomplished as follows:

• Enable the output of register R1 by setting R1out to 1. This places the contents of R1 on the
processor bus.
• Enable the input of register R4 by setting R4in to 1. This loads data from the processor bus into
register R4.

ALU operations:

The ALU is a combinational circuit that performs arithmetic and logic operations on the two operands
applied to its A and B inputs. To add two numbers, the two operands have to be made available at the
inputs of the ALU simultaneously as shown below.

The result produced by the ALU is stored temporarily in register Z. Therefore, a sequence of
operations to add the contents of registers R1 and R2 and store the result in register R3 is:

1. R1out, Yin
2. R2out, Select Y, Add, Zin
3. Zout, R3in

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Q) Explain the control sequence for execution of instruction ADD (R3),R1.

Consider the instruction, Add (R3), R1 which adds the contents of a memory location pointed to by R3
to register R1. Executing this instruction requires the following actions:

1. Fetch the instruction

2. Fetch the first operand (the contents of the memory location pointed to by R3)
3. Perform the addition
4. Load the result into R1

Following is the sequence of control steps required to perform these operations for the single-bus
organization:

• Steps 1 through 3 constitute the instruction fetch phase, which is the same for all instructions.
• The instruction decoding circuit interprets the contents of the IR at the beginning of step 4.
This enables the control circuitry to activate the control signals for steps 4 through 7, which
constitute the execution phase.
• The contents of register R3 are transferred to the MAR in step 4 and a memory Read operation
is initiated.
• Then, the contents of R1 are transferred to register Y in step 5, to prepare for the addition
operation.
• When the Read operation is completed, the memory operand is available in register MDR and
the addition operation is performed in step 6.
• The sum is stored in register Z and then transferred to R1 in step 7. The End signal causes a
new instruction fetch cycle to begin by returning to step 1.

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Q) Explain the control sequence for execution of Unconditional Branch Instruction.

A branch instruction replaces the contents of the PC with the branch target address. This address is
usually obtained by adding an offset X given in the branch instruction to the updated value of the PC.

The offset X used in branch instruction is usually the difference between the branch target address
and the address immediately following the branch instruction. For example, if the branch instruction
is at location 2000 and if the branch target address is 2050, the value of X must be 50.

Control sequence that implements an unconditional branch instruction is given below.

• Processing starts, as usual with the fetch phase. This phase ends when the instruction is
loaded into the IR in step 3. The offset value is extracted from the IR by the instruction
decoding circuit.
• Since the value of the updated PC is already available in register Y, the offset X is gated onto
the bus in step 4 and an addition operation is performed.
• The result, which is the branch target address, is loaded into the PC in step 5.

Q) Draw and explain the block diagram of a complete processor.

A complete processor can be designed using the structure shown below.

This structure has an instruction unit that fetches instructions from an instruction cache or from the
main memory. A data cache is inserted between these units and the main memory. Using separate
caches for instructions and data is common practice in many processors today.

It has separate processing units to deal with integer data and floating-point data. The processor is
connected to the system bus and hence, to the rest of the computer, by means of a bus interface.

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Q) Explain Three bus organization of the processor.

The below figure depicts a three-bus structure used to connect the registers and the ALU of a processor.

All general purpose registers are combined into a single block called the register file. In VLSI technology,
the most efficient way to implement a number of registers is in the form of an array of memory cells similar
to those used in the implementation of random-access memories (RAMs).

The register file is said to have three ports. There are two outputs, allowing the contents of two different
registers to be accessed simultaneously and have their contents placed on buses A and B. The third port
allows the data on bus C to be loaded into a third register during the same clock cycle.

Buses A and B are used to transfer the source operands to the A and B inputs of the ALU where an
arithmetic or logic operation may be performed. The result is transferred to the destination over bus C. The
three-bus arrangement cancels the need for registers Y and Z.

A second feature is the introduction of the Incrementer unit, which is used to increment the PC by 1. Using
the Incrementer eliminates the need to add 1 to the PC using main ALU.

The 3-bus structure requires significantly fewer control steps to execute instructions compared to single bus.
For example consider the instruction Add R4, R5, R6. The control sequence for its execution is given below.

By providing more paths for data transfer, a significant reduction in the number of clock cycles needed to
execute an instruction is achieved, thus achieving better performance.

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Q) Differentiate between Hardwired control and Microprogrammed control.

Attribute Hardwired control Microprogrammed control

Control signals generated by hardware Control signals generated by software

Definition
circuits. stored in Control memory.
Speed Faster Slower
Implementation Implemented in hardware Implemented in software
Flexibility Not flexible to include new instructions More flexible to include new instructions
Design process Very difficult Easy
No of instructions Under 100 instructions More than 100 instructions
Chip area Uses less area Uses more area

Q) Explain the concepts of Hardwired control.

In the hardwired organization, the control unit is designed as a combinational circuit. That is, the
control unit is implemented by gates, flip-flops, decoder and other digital circuits. Hardwired control
units can be optimized for fast operations. The following figure shows hardwired control unit.

To execute instructions, the processor must have some means of generating the control signals needed
in the proper sequence. The decoder/encoder block is a combinational circuit that generates the
required control outputs, depending on the state of all its inputs. The control signals are generated
based on the instruction present in the instruction register IR.

Consider the sequence of control signals needed to execute an instruction. Each step in this sequence
is completed in one clock period. A counter may be used to keep track of the control steps. Each state,
or count, of this counter corresponds to one control step.

The hardwired control hardware shown can be viewed as a state machine that changes from one state
to another in every clock cycle, depending on the contents of the instruction register, the condition
codes, and the external inputs. The outputs of the state machine are the control signals.

The sequence of operations carried out by this machine is determined by the wiring of the logic
elements, hence the name "hardwired." A controller that uses this approach can operate at high speed.
However, it has little flexibility, and the complexity of the instruction set it can implement is limited.

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Q) Illustrate how control signals are generated for Zin and End.

The hardware circuit for Zin is designed based on the appearance of the control signal in each of the
instruction supported by the processor. For example, Zin appears in 1st clock cycle T1 for every
instruction, appears in T4 for Branch instruction, appears in T6 for ADD instruction and so on.

The hardware circuit for End is designed based on the appearance of the control signal in each of the
instruction supported by the processor. For example, End appears in T7 for ADD instruction, appears
in T5 for Branch instruction and so on.

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Q) Explain the concepts of Micro programmed control.

In the Micro program organization, the control unit is designed as a micro program unit. That is, the
control unit is implemented by using a control store comprising of micro programs representing
different instructions. The following figure shows Micro programmed control unit.

The micro-routines for all instructions in the instruction set of a computer are stored in a special
memory called the control store. The control unit can generate the control signals for any instruction
by sequentially reading the CWs of the corresponding micro-routine from the control store.

To read the control words sequentially from the control store, a micro program counter (μPC) is used.
Every time a new instruction is loaded into the IR, the output of the block labeled ―starting address
generator‖ is loaded into the μPC. The μPC is then automatically incremented by the clock, causing
successive microinstructions to be read from the control store. Hence, the control signals are delivered
to various parts of the processor in the correct sequence.

During the addition of many summands, we can group the summands in threes and perform carry-
save addition on each of these groups in parallel to generate a set of S and C vectors which are used
further to calculate the final result and the speed of processing gets increased.

An example microinstructions generated for the instruction ADD (R3), R1 is shown below.

A controller that uses Micro program approach can operates at slower speed. However, it has more
flexibility and any complex instruction can be implemented using this approach.

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