Processes & Assignments
Table of Contents
Types of Assignments : Continuous and Procedural.................................................................................2
Procedural assignments & delays (always blocks)....................................................................................3
Block Statement – Sequential And Parallel Block...................................................................................10
Sensitivity List and always@(*)..............................................................................................................12
Event Timing Control...............................................................................................................................15
Manikanta Page No:1
Types of Assignments : Continuous and Procedural
Continuous Assignment:-
A continuous assignment is used to drive a value on to a net.A continuous assignment replaces gates
in the description of the circuits and describes the circuit at a higher level of abstraction.
A continuous assignment statement starts with the keyword assign.
Continuous assignment have the following characteristics
The left hand side of an assignment must always be a net type.
The Right hand side can be reg or net type.
Continuous assignment are always active.
Delay values can be specified for assignments in terms of time units.
Example:-
out is a net type
A and B are reg type
assign out = A&B;
Implicit Continuous Assignment :-
Contiuous assignment can be placed on a net when it is declared.
There can be only one implicit declaration assignment per net because a net is declared only once.
//Continuous assignment
wire out;
assign out = A& B;
//Implicit Continuous Assignment
wire out = A & B;
Manikanta Page No:2
Procedural assignments & delays (always blocks)
Delays :
Delay values control the time between the changes in a right hand side operand and when the new
value is assigned to the left hand side. Three ways of specifying delays in continuous assignments
statements
1. Regular assignment delay
2. Implicit continuous assignment delay
3. Net declaration delay
Regular assignment delay:-
The delay value is specified after the keyword assign.
Any change in values of A and B will result in a delay of 10 times units before recomputation of
of the expression A and B and the result will be assigned to out.
// Delay in a Continuous assign
assign #10 out = A & B;
Implicit Continuous assignment delay :-
Specify both a delay and an assignment on the net.
//Implicit Continuous assignment delay
wire #10 out = A & B;
Net Declaration Delay :-
A delay can be specified on a net when it is declared without putting a Continuous assignment on the
net.
//Net Delay
wire #10 out;
assign out = A & B;
Manikanta Page No:3
Example Code :
module half_add(input a,b, output s,Cout);
assign s = a ^ b;
assign Cout = a & b;
endmodule
Real Time Application :
Combinational Logic:
Used to model logic gates, adders, multiplexers — e.g., assign y = a & b;
Arithmetic Operations:
For real-time sum, carry, or parity generation — e.g., assign sum = a + b;
FSM Output Logic:
To generate control/status signals — e.g., assign ready = (state == IDLE);
Procedural Assignment :-
Verilog Supports two Procedural Statements always and initial.
All behavioral statements are written inside these blocks.
These blocks run in parallel .
Their activity starts at 0 simulation time.
Initial Statement :
Once executable only
Execution starts at 0 simulation time
Execution stops when the last statement is executed.
Parallel execution in case of multiple initial blocks.
Multiple statement inside an initial block needs to be grouped with begin and end statements.
Always Statement :
Repeats continuous throughout the duration of simulation time.
Like initial block it is also concurrent in nature and starts at 0 simulation time.
Parallel execution in case of multiple always blocks.
A deadlock condition will be created if an always construct has no control for simulation time.
Manikanta Page No:4
Delays in Procedural Assignments :-
Delay based timing control in an expression specifies the time duration between when the statements
is encountered and when it is executed.
[Link] Delay
[Link] Assignment Delay
Regular Delay :-
If delay is specified then at that time the entire statement is executed and assigned to the LHS.
This is the delay before the RHS is evaluated and assigned to the LHS
Entire operation will be delayed.
Example :-
initial
begin
A=5; B=0;
#10 C = A + B;
end
Intra Assignment Delay :
The RHS of the equation is evaluated at current time but the value is assigned to LHS after the
delay time.
Can be applied to both blocking and non blocking assignment.
Example :
initial
begin
A=5; B=0;
C = #10 A + B;
end
Manikanta Page No:5
Real Time Application of Procedural Assignment:
Sequential Logic:
Used in flip-flops and registers — e.g., always @(posedge clk) q <= d;
Counters and Accumulators:
For counting or accumulating values on clock edges — e.g., count <= count + 1;
Finite State Machines (FSMs):
To update the current state and outputs based on clock — e.g., state <= next_state;
Control Logic:
For enabling, resetting, or controlling data flow — e.g., if (reset) q <= 0;
Testbenches:
To generate stimuli or monitor signals — e.g., initial begin a = 0; #10 a = 1; end
Interview Questions :
What is the difference between continuous and procedural assignments in Verilog?
Can we use assign inside an always block?
What types of data objects can be driven by continuous assignment?
What types of data objects can be assigned in procedural blocks?
What happens if you use both continuous and procedural assignments to drive the same net?
Can you assign to a reg using a continuous assignment?
Give a real-time example where continuous assignment is used.
Give a real-time example where procedural assignment is used.
What is the main difference in timing between continuous and procedural assignments?
Can assign statements be used to model sequential circuits?
What is the purpose of the @(*) sensitivity list in procedural blocks?
Can multiple continuous assignments drive the same wire?
In synthesis, what hardware do continuous and procedural assignments generate?
Can we mix blocking and non-blocking assignments in the same always block?
Manikanta Page No:6
Block Statement – Sequential And Parallel Block
Sequential Block:
Begin – end is used to group multiple statements.
Statements are executed in the order they are mentioned.
Delay is treated relative to the simulation time and previous statement.
Example :-
reg x,y;
reg [1:0] z,w;
initial
begin
x = 1’b0; // completes at simulation time 0
#5 y = 1’b1;// completes at simulation time 5
#10 z = {x,y};// completes at simulation time 15
#20 w ={y,x};// completes at simulation time 35
end
Block Statement – Parallel Block
Fork Join is used to group multiple statements.
Statements are executed in concurrently.
Delay is treated relative to the simulation time of entering the block.
Example :-
reg x,y;
reg [1:0] z,w;
initial
fork
x = 1’b0; // completes at simulation time 0
#5 y = 1’b1;// completes at simulation time 5
#10 z = {x,y};// completes at simulation time 10
#20 w ={y,x};// completes at simulation time 20
join
Real Time Application :-
Sequential (begin...end):- Executes statements one after another.
Use: Flip-flops, counters, FSMs, reset logic.
Parallel (fork...join):- Executes statements simultaneously.
Use: Testbench stimulus generation, concurrent monitoring, timing simulations.
Manikanta Page No:7
Interview Questions :-
What is a block statement in Verilog?
What is the difference between sequential (begin...end) and parallel (fork...join) block
statements?
Can you use begin...end inside an always block? If yes, why?
Where is fork...join typically used in Verilog?
What is the difference between fork...join, fork...join_any, and fork...join_none?
Can you have nested sequential blocks? If yes, give an example.
Can parallel blocks be used inside sequential blocks?
How does a fork...join block behave in simulation compared to hardware?
Give a real-time application of a sequential block in hardware design.
Give a real-time application of a parallel block in testbench design.
Sensitivity List and always@(*)
Sensitivity List :-
The always block runs again whenever any signal in its sensitivity list changes value.
There are two types of Sensitivity List
1. Combinational (Level Sensitive)
Used to describe combinational logic where outputs depend continuously on inputs.
Example :-
Here, whenever a, b, or sel change, the always block is re-executed.
always @(a or b or sel)
begin
if (sel)
Manikanta Page No:8
y = a;
else
y = b;
end
Triggered when any of a, b, or sel changes.
If you forget one signal, the simulator won’t update y correctly.
This can cause functional errors in simulation .
Sequential (Edge-Sensitive)
Used to describe flip-flops or sequential circuits that trigger on clock edges( posedge or negedge of
Clock).
Example:
always @(posedge clk )
begin
if (rst_n)
q <= 0;
else
q <= d;
end
Here,Executes only on Rising edge of clk.
Problem with Manual Sensitivity Lists
When designing combinational logic, manually listing every signal can lead to errors.
Example :
always @(a or b)
begin
if (sel)
y = a;
else
Manikanta Page No:9
y = b;
end
Here, sel is missing from the sensitivity list.
� Simulation problem:
When sel changes, y doesn’t update.
In synthesis, the tool still builds correct logic.
Therefore, simulation ≠ synthesis, which is dangerous.
The Solution — always @(*) :
To solve this, Verilog introduced the wildcard sensitivity list(implicit event), written as:
always@(*).
Automatically includes all signals that are read inside the block (right-hand side of
assignments).Ensures the block reacts to all relevant inputs.
Example :
always @(*)
begin
if (sel)
y = a;
else
y = b;
end
Real Time Application:-
Used to trigger always blocks when signals change.
Helps model combinational logic (always @(*)).
Used to model sequential circuits like flip-flops (@(posedge clk)).
Manikanta Page No:10
Interview Questions:-
What is a sensitivity list in Verilog?
Why is the sensitivity list used in always blocks?
What is the difference between always @(*) and always @(a or b)?
What happens if a signal is missing from the sensitivity list?
How is a sensitivity list used in combinational logic modeling?
How is a sensitivity list used in sequential logic modeling?
What is the purpose of including posedge clk or negedge reset in the sensitivity list?
What is the difference between blocking (=) and non-blocking (<=) assignments in alwaysblocks?
How does the sensitivity list affect simulation performance?
What is the difference between an always block and an initial block in terms of sensitivity?
Event Timing Control
Event timing control determines when a statement or block of code executes based on events or time
delays.
Timing control not for synthesis.
Types of Timing Control:
1. Delay-based control (#)
Executes after a specified time delay.
Example :-
#10 a =b; //executes after 10 time unit
2. Event-based control (@)
Executes when a specified event occurs (like a signal change).
Example:-
@(posedge clk) q = d; // executes on rising edge of clk
[Link]-sensitive / Wait statement (wait)
Waits until a condition becomes true.
Manikanta Page No:11
Example :
wait(enable == 1);
Real Time Application:-
Used in testbenches to apply delays and generate input waveforms.
Controls when assignments or actions occur (e.g., #10, @(posedge clk)).
Supports event-driven execution — code runs only when needed, improving simulation efficiency.
Interview Questions:-
What is event timing control in Verilog?
Explain the difference between delay control (#) and event control (@).
What is the purpose of using @(posedge clk) in Verilog?
How does wait differ from @ event control?
What are real-time applications of event timing control?
How are propagation delays modeled using event timing control?
What is a non-blocking delay (#delay) used for in a testbench?
Can we combine multiple event controls in one statement? Give an example.
What is the difference between level-sensitive and edge-sensitive event control?
How does event timing control help in testbench design and waveform generation?
Manikanta Page No:12