COMMUNICATION

PROTOCOLS

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CONTENTS

ON-CHIP COMMUNICATION PROTOCOLS

[Link] TOPICS PAGE NO

1 1 APB PROTOCOL
1 Introduction 6
1.1 Signal Description 6
1.2 Read and write transfers 8
1.3 Error responses 10
1.4 APB States 11
1.5 Interview Questions 13

2 2 AHB PROTOCOL
2 Introduction 14
2.1 AHB Block diagram 16
2.2 Types of transfers 17
2.3 Signal Description 17
2.4 Basic Transfers 18
2.5 Burst Operation 21
2.6 Protection Control 24
2.7 Memory types 25
2.8 Bus Interconnection 26
2.9 Interconnect with AHB interface 27
2.10 Slave response signaling 28
2.11 Error Response 28
2.12 Exclusive Transfers 31
2.13 Interview Questions 33

3 3 AXI PROTOCOL
3 Introduction 35
3.1 Architecture 35
3.2 Channel Definition 36

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 3.3 Signal Description 37
3.4 Channel Handshake 40
3.5 Dependencies between channel handshake signals 42
3.6 System-level Caches and Protection Units 46
3.7 Atomic Access 48
3.8 Response signaling 50
3.9 Ordering Model 51
3.10 Data Buses 53
3.11 Unaligned Transfers 53
3.12 Interview Questions 57

4 4 DMA PROTOCOL
4 Introduction 59
4.1 What is DMA 59
4.2 What is actually DMA 59
4.3 DMA signals 59
4.4 DMA Channels 60
4.5 Modes of DMA operation 60
4.6 DMA operational modes and settings 60
4.7 Types 60
4.8 Working of DMA controller 60
4.9 Bus-Master DMA devices 61
4.10 System DMA Devices 61
4.11 Interview Questions 63

OFF-CHIP COMMUNICATION PROTOCOLS

[Link] TOPICS PAGE NO

5 5 SPI
5 Introduction 64
5.1 SPI pin description 64
5.2 Operation 65
5.3 Configuration 65
5.4 Typical SPI bus 66
5.5 Daisy Chained SPI bus 66
5.6 Data Transmission 66

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 5.7 Clock polarity and Phase 67
5.8 Registers 68
5.9 Configuration of Master and Slave 73
5.10 Interview Questions 75

6 UART
6 Introduction 76
6.1 Why UART 76
6.2 Block diagram 76
6.3 Serial connector 77
6.4 Transmitter section 77
6.5 Receiver Section 77
6.6 UART TxD 78
6.7 UART RxD 79
6.8 How UART works 80
6.9 Transmission and reception 81
6.10 Configuration 81
6.11 Interview Questions 84
7 I2C
7 Introduction 85
7.1 Design 85
7.2 Interface 86
7.3 How I2C works 87
7.4 Types of transactions in I2C 87
7.5 Timing Diagram 88
7.6 Clock stretching 88
7.7 I2C Node device’s 89
7.8 Interview Questions 90

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 AMBA
(ADVANCED MICRO-CONTROLLER BUS ARCHITECTURE)

The Advanced Micro-controller Bus Architecture, or AMBA, is an open-standard, on-chip interconnect

specification for the connection and management of functional blocks in system-on-a-chip (SoC) designs.
AMBA is a set of interconnect protocols.

There are three communication protocol of AMBA family:

1. APB (Advanced Peripheral Bus)
2. AHB (Advanced High-Performance Bus)
3. AXI (Advanced eXtensible Interface).

The diagram depicts a block diagram of a AMBA Architecture. The High-performance ARM processor is the
Core of the system.

The other components like High-bandwidth on-chip RAM, DMA bus master and High-bandwidth memory
interface are connected to the Core by system bus, which is AHB in this case.

The other low bandwidth peripherals like UART, Timer, Keypad, and PIO are connected to the bus through the
bridge by using peripheral bus, here it is APB bus.

In this scenario, the bridge acts as the AHB slave corresponding to the core master. And it also acts as the APB
Master corresponding to remaining low-bandwidth external peripherals.

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 APB
(Advanced Peripheral Bus)

1. Introduction

 Advanced Peripheral Bus (APB) is the part of the Advanced Micro-controller Bus Architecture
(AMBA) family protocols.
 It is a low-cost interface and it is optimized for minimal power consumption and reduced interface
complexity.
 It is Non-Pipelined protocol, used to connect low-bandwidth peripherals.
 Mostly used to connect the external peripheral to the SoC.
 In APB, every transfer takes at least two clock cycles (SETUP cycle and ACCESS cycle) to complete.
 It can also interface with AHB and AXI protocol’s using the bridges in between.

PERIPHERAL
 It is external or internal device that connects to CPU to provide input, output.

1.1 Signal Description

SIGNAL SOURCE WIDTH DESCRIPTION

PCLK clock 1 All APB signals are
timed against the rising
edge of PClk.
PRESETn System bus reset 1 Active-low
asynchronous Reset.
PSELx Master 1 Slave select signal, there
(Requester) will be one PSEL signal
for each slave connected
to master. If master
connected to ‘n’ number
of slaves, PSELn is the
maximum number of
signals present in the
system. (Example :
PSEL1, PSEL2..,
PSELn)
PENABLE Master 1 PEnable indicates the
(Requester) second and subsequent
cycles of an APB
transfer. When
PENABLE is asserted,
the ACCESS phase in
the transfer starts.
PADDR Master ADDR_WIDTH Address bus from
(Requester) Master to Slave, can be

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 up to 32 bit wide.
PWRITE Master 1 The signal indicates an
(Requester) APB write access when
HIGH and an APB read
access when LOW.
PWDATA Master DATA_WIDTH Write data bus from
(Requester) master to slave, can be
up to 32 bit wide. The
PWDATA write data
bus is driven by the
APB bridge when
PWRITE is high .
PRDATA Slave DATA_WIDTH Read data bus from
(Completer) slave to master, can be
up to 32 bit wide. The
PRDATA read data bus
is driven by the APB
peripheral bus slave
when PWRITE is LOW.
PREADY Slave 1 The APB peripheral
(Completer) slave uses this signal to
extend an APB transfer.
PSLVERR Slave 1 This signal indicates
(Completer) transfer success or
failure. PSLVERR is
HIGH when PSELx,
PENABLE, PREADY
are high else becomes
LOW.
PSTRB Master DATA_WIDTH/8 PSTRB (write strobe)
(Requester) shows which bytes of
PWDATA are valid
during a write.
Each bit of PSTRB
controls one byte (8
bits) of the data bus —
PSTRB[n]→PWDATA[
(8n+7):(8n)]. It is used
only for writes and must
stay inactive during
reads.

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 PPROT Master 3 PPROT defines the
(Requester) protection level of an
APB transfer — it
shows whether the
access is normal or
privileged, secure or
non-secure, and whether
it’s a data or instruction
access.

1.3 READ and WRITE transfers

Let’s see how a typical write and read transfers are done in APB protocols

Write Transfers: This section describes the following types of write transfer
 With no wait states
 With wait states

With no wait states

 The setup phase of the write transfer occurs at T1.

 The PSELx signal is asserted which means that PADDR, PWRITE and PWDATA must be valid.
 The ACCESS phase of the write transfer is shown at T2, where PENABLE is asserted.
 PREADY is asserted by the completer at the rising edge of PCLK to indicate that the write data will be
accepted at T3.
 PADDR, PWDATA, and any other control signals, must be stable until the transfer completes.
At the end of the transfer, PENABLE is deasserted PSELx is also deasserted, unless there is another
transfer to the same peripheral.

With wait states

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  During an ACCESS phase, when PENABLE is high, the APB peripheral extends the transfer by driving
PREADY low.
The following signals remain unchanged while PREADY remains low:
 Address signal, PADDR
 Direction signal, PWRITE
 Select SIGNAL, PSELx
 Enable signal, PENABLE
 Write data signal, PWDATA
 PREADY can take any value when PENABLE is low.
This ensure that peripherals that have a fixed two cycle access can tie PREADY high.

Write Strobe
 PSTRB tells which bytes in the write data (PWDATA) are valid during a write.
 Each bit of PSTRB controls one byte (8 bit) – PSTRB[n] – PWDATA [(8n+7): (8n)].
 If PSTRB[n] = 1, that byte is written: if 0, it’s ignored.
 For read transfers, all PSTRB bits must be LOW.

Read Transfer: Two types of read transfer are described in this section
 With no wait states
 With wait states

With no wait states

 At T1, a READ transfer with address PADDR, PWRITE and PSEL starts.
 They will be registered at rising edge of PCLK.
 This is SETUP Phase of the transfer.
 After T2, PENABLE and PREADY are registered at the rising edge of PCLK.
 When asserted, PENABLE indicates the starting of ACCESS phase.
 When asserted, PREADY indicates that slave can complete the transfer at next rising edge of PCLK by
providing the data on PRDATA.
 Slave must provide the data before the end of read transfer .[Link] T3.

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With wait states

 During the ACCESS Phase, when PENABLE is high, the slave extends the transfer by driving
PREADY low.
 The PADDR, PWRITE, PSEL, PENABLE, PPROT signals should remain unchanged while PREADY
is low.
1.4 Error Response
Two types of Error response: 1. Error write response and 2. Error read response.
 PSLVERR is an APB signal that indicates an error during a transfer (read or write).
 It is valid only when PSEL, PENABLE, and PREADY are all high (the last cycle of the transfer).
 It is recommended to keep it low otherwise, if an error occurs
A write may or may not have updated the peripheral.
A read may return invalid data
 Some peripherals don’t support errors, in that case, PSLVERR is just tied low (no errors ever signaled).
Example of a failing write transfer that completes with an error.

A read transfer can also complete with an error response, indicating that there is no valid read data available.

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 1.5 APB STATES
The APB Protocol operates in three operating states:
1. Idle
2. Setup
3. Access

1. IDLE: The default or “resting” state of the APB bus. No transfer is happening.
PSEL = 0 (no peripheral selected).

2. SETUP: Starts when a new transfer is needed.

 The master sets up the address and control signals (PADDR, PWRITE, etc).
 PSEL = 1 (selects the target peripheral).
 This state lasts only one clock cycle.
 Next cycle – always goes to ACCESS.

3. ACCESS: PENBALE = 1 (transfer is active).

 The actual read or write happens here.
 The signals (PADDR, PWRITE, PWDATA, etc.) must stay the same during this state.
 The slave (completer) uses PREADY to control when the transfer finishes:
 If PREADY = 0 – stay in ACCESS (slave not ready yet).
 If PREADY = 1 – transfer completes.
 If no new transfer – go back to IDLE.
 If another transfer is ready – go to SETUP again.

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 STATE WHAT HAPPENS KEY SIGNAL
IDLE No transfer PSEL =0
SETUP Address / control setup PSEL = 1, PENABLE = 0
ACCESS Data transfer PSEL = 1, PENABLE = 1, wait
for PREADY

ADVANTAGES DISADVANTAGES APPLICATIONS

Simple design Slow speed Micro-controllers (e.g., ARM
Cortex-M)
Low power consumption No pipelining or burst transfer Mobile/SoC chips
Low area cost Limited scalability Automotive ECUs
Easy timing control and suitable Simple error handling Embedded / IoT devices , FPGA
for low-speed peripherals Designs

Features
1. Part of AMBA family
2. Simple, non-pipelined protocol
3. Low power and low cost
4. Synchronous operation
5. Used for low-bandwidth peripherals
6. Bridge-based connection
7. Supports both read and write transfers
8. Error reporting supported
9. Byte-level write control
10. Protection signaling
11. Deterministic timing

Real-time use examples

 Microcontrollers – Connects CPU core to peripherals such as timers, UART, GPIO, ADC, SPI, I2C,
ETC.
 Smartphones / tablets (SoCs) – Used inside chips to connect slow control blocks like watchdogs,
power controllers, and system registers.
 Automotive ECUs – Used in chips controlling sensors, safety modules, and dashboard functions.
 Ebedded controllers / IoT – For linking sensors, status registers, or low-speed communication
interfaces to the main processor.
 FPGA-based systems – Often used to build control registers for custom logic blocks.

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1.6 Interview Questions

1. What is APB? Why do we need APB?

2. What are the main signals in APB?

3. What are the operating states in APB?

4. What is the role of PREADY?

5. What does PSLVERR indicate?

6. What is PSTRB used for?

7. What is the difference between SETUP and ACCESS states?

8. Can APB support burst transfers?

9. Can multiple slaves connect to the same APB bus?

10. Is APB synchronous or asynchronous?

11. What happens if PREADY Is never asserted?

12. What are typical APB applications?

13. Why APB interface is design?

14. Why alignment address is important?

15. Why APB data is 32 bit?

16. Why APB is 1 KB boundary?

17. What happens if an error occur during write and read?

18. Can we perform back to back transfer on APB?

19. How does the APB protocol handle slow peripherals?

20. Can a slave ignore PSLVERR?

21. How many cycles to take complete the Transfer? And why?

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 AHB

(ADVANCED HIGH PERFORMANCE BUS)

2 Introduction

Advanced High-Performance Bus (APB) is the part of the Advanced Micro-controller Bus Architecture
(AMBA) family protocols.
It’s widely used in SoC(System-on-Chip) designs to connect multiple IP blocks like CPUs, memory interface’s
and peripheral’s.
It defines master, interconnect and slave.
AHB supports the efficient connection of processors, on-chip memories and off-chip external memory.
Interfaces with low-power peripheral macro cell functions.
It implements the features for high performance, high clock frequency.
1. Burst transfers
2. Single clock edge operation [due to pipeline]
3. Non – Tristate implementation
4. Configurable data bus width [1024]
5. Configurable address bus width.

1. Burst transfer:
 AHB supports burst transferable which allow multiple data transfers to happen back-to-back With-out
restoring the address phase each time. It improves throughput and efficiency.
 Example – If CPU wants to read 4 words of data from memory. It can use a INCR4 burst instead of
sending 4 separate read request.

2. Single clock-edge operation:

 All operations (address, control and data transfer) happen on the rising edge of the clock.
 This simplify the timing and helps to achieve high frequency design.

3. Non-tristate implementation:
 AHB does not used tristate bus. We used mux for data routing, making the bus safe and synthesizable.

4. Configurable data bus widths :

 It supports variable data widths – a) 32 bit b) 64 bit c) 128 bit
 This makes it scale-able based on system performance need.

5. Configurable address bus width :

 It is configurable depending on how much memory space the system needs to access.

AHB component’s
1. AHB Master : (Transfer initiator)
2. AHB Slave
3. AHB Arbiter : (Multi-master)
4. AHB Decoder : (Centralized decoder)

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 2.1 AHB BLOCK DIAGRAM

 1 master and 3 slaves which has 1 interconnect logic which include decoder and mux.
 Decoder check the address sent by master and generate HSELx signal for selectng the slave
 Mux routes the data output from selected slave to master.
 If 1 master and 1 slave then no need decoder and mux.
 If multiple master and multiple slave then we used interconnect (arbitation logic).
 1 master and multiple slave we used 1 decoder and 1 mux is used.

 The main components types of an AHB system are described in :

1. Manager / Master
2. Subordinate / Slave
3. Interconnect

1. Manager / Master
A Master provides address and control information to initiate read and write operations.

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2. Subordinate / Slave
A Slave responds to transfers initiated by masters in the system. The slave uses the HSELx select signal
from the decoder to control when it responds to a bus transfer.

The slave signals back to the master:

The completion or extension of the bus transfer.
The success or failure of the bus transfer.

3. Interconnect
 The interconnect connects masters and slaves in a system.
 In a single-master system, only a decoder and multiplexor are needed.
 In a multi-master system, the interconnect handles arbitration and signal routing (address, control
& data) between multiple masters and slaves.

4. Decoder
 The decoder identifies which slave is selected for each transfer based on the address.
 It generates select signal signals (HSELx) for the appropriate slave.
 Also provides control signals to the multiplexor.

5. Multiplexor
 The multiplexor connects data and response signals from multiple slaves back to the master.
 It selects the correct slave’s output (read, data, response) based on the decoder’s control.
 A single centralized multiplexor is used when there are two or more slaves.

Operation
The master starts a transfer by driving address and control signals.
These signals define:
 Address and direction (read/write).
 Data width.
 Type of transfer (single or burst).

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2.2 Types of transfers
 Single – One data transfer.
 Incrementing burst – Address increases after each transfer.
 Wrapping burst – address wraps around at boundary limits.

Data movement
 Write : data moves master – slave
 Read : data moves slave – master

Transfer Phases
 Address Phase – 1 cycle (address + control).
 Data Phase – 1 or more cycles (actual data transfer.

Control Signals
 HREADY – When low, it inserts wait states to give more time for data.
 HRESP – Indicates success or failure of a transfer.

2.3 AHB Signal Description

[Link] SIGNAL SOURCE WIDTH DESCRIPTION

1. HCLK Clock source 1 System clock
2. HRESETn Reset controller 1 Active low signal
3. HADDR Master & 32 HADDR is the address of AHB. It can be 32,
decoder 64, …….
4. HWDATA master 32 During HWRITE=1, then write operation is
happened.
5. HRDATA Slave & mux 32 During HWRITE=0, then read operation is
happen to slave to master.
6. HWRITE master 1 HWRITE=1, then write operation if
HWRITE=0, then read operation.
7. HBURST master 3 Single, undefined length, uncr4, wrap4---etc.
8. HSIZE master 3 Byte, half-word, word, double-word, 4-word
line, 8-word line,---,---
9. HTRANS master 2 Idle, busy, non-seq and seq.
10. HRESP slave 2 Okay, error, split, retry.
11. HREADY slave 1 HREADY=1, then transfer is finished
12. HSELx Decoder & 1 It select the slave as per address.
slave
13. HSTRB master 8 It send the valid lane of data.
14. HPROT master 4 Protection level of a transfer. Privileged or
user fetch or data access, bufferable, cache.

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 0=no protection, 4=basic protection, 7=full
protection.
15. HMASTL master 1 Indicates that the current transfer is part of a
OCK locked sequence. It has the same timing as
address & control signal.
16. HNONSEC Master & 1 Indicate whether the transfer is non-secure or
decoder secure.

17. HEXOKA mux 1 Exclusive OKAY indicate the success or

Y failure of an exclusive transfer.

Response Type (HRESP)

HRESP TYPE DESCRIPTION

00 OKAY Transfer completed
successfully without error.
01 ERROR Transfer failed due to an error.
Slave signals this when it
cannot process the request.
10 SPLIT Transfer cannot proceed now;
master should retry later. Slave
releases the bus.
11 RETRY Slave is temporarily
unavailable. Master should
retry the same transfer again.

Overview of AHB operation

In AHB normal operation, a master usually completes an entire burst before the arbiter switches to another
master. However, the arbiter can interrupt a burst to reduce latency, requiring the master to re-arbitrate to
finish the burst. During writes, the master holds data stable through extended cycles, while for reads, the
slave only provides valid data when the transfer is about to complete.

2.4 Basic Transfer

An AHB transfer consists of two distinct sections:

1. The address phase : Lasts for a single HCLK cycle unless it is extended by the previous bus transfer.
2. The data phase : Might require several HCLK cycles. Use the HREADY signal to control the number of
clock cycles required to complete the transfer.

 HWRITE is high, it indicates a write transfer and the master broadcasts data on the write data bus,
HWDATA.
 HWRITE is low, a read transfer is performed, and the slave must generate the data on the read data bus,
HRDATA.
 The transfer consists of one address cycle and one data cycle.

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Transfer types (HTRANS)

VALUE SIGNAL DESCRIPTION

00 IDLE No data transfer
01 BUSY The BUSY transfer type enables Masters to
insert idle cycles in the middle of a burst.
10 NON-SEQ First transfer of burst
11 SEQ Sequential transfer.

 Only NONSEQ and SEQ are considered valid data transfers.

 Valid data transfers only occur when HTRANS = NONSEQ or SEQ.
 IDLE and BUSY are ignored by slaves for data operations.

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T0-T1: The 4-beat read starts with a NONSEQ transfer.
T1-T2: The Master is unable to perform the second beat and inserts a BUSY transfer to delay the start of the
second beat. The Slave provides the read data for the first beat.
T2-T3: The Master is now ready to start the second beat, so a SEQ transfer is signaled. The Master ignores any
data that the Slave provides on the read data bus.
T3-T4: The Master performs the third beat. The Slave provides the read data for the second beat.
T4-T5: The Master performs the last beat. The Slave is unable to complete the transfer and uses HREADYOUT
to insert a single wait state.
T5-T6: The Slave provides the read data for the third beat.
T6-T7: The Slave provides the read data for the last beat.

Locked Transfer

Locked transfers in AHB use the HMASTLOCK signal to make a transfer sequence indivisible, meaning no
other transfers can occur in between. This is often used for operations like semaphores to keep data consistent.
 The bus locks when HMASTLOCK, HSEL, and HREADY are all HIGH.
 It unlocks when HMASTLOCK goes LOW and HREADY is HIGH.

 Most slaves don’t need HMASTLOCK since they handle transfers in order. Slaves shared by multiple
masters (like a multi-port memory controller) must support it.
 A master can assert HMASTLOCK during IDLE transfers (before, during, or after a locked sequence),
but this is not recommended because it can disrupt arbitration.
 All transfers in a locked sequence must go to the same slave address region.
Transfer size
HSIZE[2:0] indicates the size of a data transfer.
HSIZE [2] HSIZE [1] HSIZE [0] SIZE (bits) Description
0 0 0 8 BYTE
0 0 1 16 HALFWORD
0 1 0 32 WORD
0 1 1 64 DOUBLE WORD
1 0 0 128 4-WORD LINE

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 1 0 1 256 8-WORD LINE
1 1 0 512 16-WORD LINE
1 1 1 1024 32-WORD LINE
The HSIZE signal defines the number of bits in each data transfer.
It helps slaves/memory interfaces prepare for the correct amount of data width in a transaction.
The HSIZE signals have the same timing as the address bus. However, they must remain constant throughout a
burst transfer.
HSIZE in conjunction with HBURST determines the address boundary for wrapping bursts.

Write Strobes (HWSTRB) Rules in AHB:

 For transfers smaller than the data bus, HSIZE and HADDR decide which byte lanes are active.
 Active lanes’ strobes can be HIGH or LOW — all LOW means a sparse write.
 Inactive lanes’ strobes can also be HIGH or LOW but are ignored.
 If all strobes are LOW, no data is written.
 Strobe-to-data mapping doesn’t depend on endianness.
 For read transfers, strobes should be LOW (off).
 Strobes can change between beats in a write burst.

2.5 Burst Operation (HBURST)

HBURST [2:0] TYPE DESCRIPTION
000 single Single transfer bus
001 Incr Incrementing burst of
undefined length
010 Wrap4 4-beat wrapping burst
011 Incr4 4-beat Incrementing burst
100 Wrap8 8-beat wrapping burst
101 Incr8 8-beat Incrementing burst
110 Wrap16 16-beat wrapping burst
111 Incr16 16-beat Incrementing burst.

 The HBURST signal defines how many beats (data transfers) are in the burst and the behavior (wrap-
ping or incrementing).
 Incrementing bursts simply increase the address.
 Wrapping bursts wrap around to a lower boundary when reaching the end of the burst.
 AHB supports single, 4-, 8-, 16-beat, and undefined-length bursts.

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Two burst types:
Incrementing burst: Address increases sequentially each transfer.
Wrapping burst: Address wraps around after reaching a boundary = (number of beats × transfer size).
Example: A 4-beat word (4-byte) wrapping burst wraps every 16 bytes — e.g., start at 0x34 → 0x34, 0x38,
0x3C, 0x30.
The HBURST[2:0] signals define the burst type.

Waited Transfers
Slaves use HREADYOUT to signal the master to wait if they need more time for data.
While waiting, the master can’t freely change the transfer type or address – there are specific limits on what can
change during these wait states.

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1. Transfer type changes during wait states
 When the slave is requesting wait states, the master must not change the transfer type.
 Idle transfer.
 Busy transfer, fixed-length burst.
 Busy transfer, undefined length burst.
Idle transfer
During a wait, the Manager can change HTRANS from IDLE to NONSEQ, but once it does, it must keep
HTRANS unchanged until HREADY = HIGH.

T0–T1: Manager starts a SINGLE transfer to address A.

T1–T2: Adds an IDLE transfer to address Y; Subordinate makes HREADYOUT = LOW (wait state).
T2–T3: Another IDLE transfer to address Z.
T3–T4: Manager changes to NONSEQ and begins an INCR4 burst to address B.
T4–T6: With HREADY LOW, HTRANS must stay the same.
T5–T6: SINGLE transfer to A finishes (HREADY HIGH); first beat to B starts.
T6–T7: First beat to B ends; next beat starts to B+4.

Busy transfer, fixed-length burst

During a wait in a fixed burst, the Manager can change HTRANS from BUSY to SEQ, but must keep it un-
changed until HREADY = HIGH.

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T0–T1: Manager starts next INCR4 beat to 0x24.
T1–T3: Adds a BUSY transfer to 0x28; Subordinate holds HREADYOUT = LOW (wait).
T3–T4: Manager changes to SEQ and starts next beat to 0x28.
T4–T6: With HREADY LOW, HTRANS stays the same.
T5–T6: Beat to 0x24 finishes (HREADY HIGH).
T6–T7: Beat to 0x28 finishes; next beat starts to 0x2C.

Busy transfer, undefined length burst

During a wait in an INCR burst, the Manager can change from BUSY to any transfer type while HREADY is
LOW.
SEQ→ burst continues.
IDLE or NONSEQ → burst ends.

T0–T1: Manager starts next INCR beat to 0x64.

T1–T3: Adds a BUSY transfer to 0x68; Subordinate sets HREADYOUT = LOW(wait).
T3–T4: Manager changes to NONSEQ, starting a new burst at 0x10.
T4–T6: With HREADY LOW, HTRANS stays constant.
T5–T6: INCR burst ends (HREADY HIGH); first beat to 0x10 starts.
T6–T7: First beat to 0x10 ends; next beat starts to 0x14.

2.6 Protection Control

The protection control signals, HPROT [3:0] gives extra info about a bus transfer for protection purposes.
It shows whether the transfer is: Opcode fetch or data access.
Privileged or user mode access with an MMU, it also shows if the access is cacheable or bufferable.
HPROT[3] HPROT[2] HPROT[1] HPROT[0] Description
Modifiable Bufferable Privileged Data/Opcode
- - - 0 Opcode fetch

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 - - - 1 Data access
- - 0 - User access
- - 1 - Privileged access
- 0 - - Non-bufferable
- 1 - - Bufferable
0 - - - Non-cacheable
1 - - - Cacheable
The HPROT control signals have the same timing as the address bus. However, they must remain constant
throughout a burst transfer.

2.7 Memory types

 AHB5 Extended_Memory_Types shows if an interface supports extended memory types.
 If not defined, extended memory types are not supported.
 This version adds more HPROT signals and detailed rules for each memory type.
BIT NAME 0(DEASSERTED) 1(ASSERTED)
HPROT[0] Data/Inst Instruction fetch Data access
HPROT[1] Priviliged Unprivileged access Privileged access
HPROT[2] Bufferable Write response from Write can respond from
final destination intermediate, must
reach final
destination
HPROT[3] Modifiable Transfer characteristics Transfer characteristics
must not change can be modified
HPROT[4] Lookup No cache lookup; Must be looked up in
pro[agate to final cache
destination
HPROT[5] Allocate Recommended not to Recommended to
allocate in cache allocate in cache
HPROT[6] Sharebale Non-sharebale; response Shareable; response only
not guaranteed after visible to others
visible to others (ignored for device
memory).

HPROT [0] – Data/Instruction:

 0: Instruction fetch
 1: Data access (recommended unless it’s definitely an instruction)
1HPROT [1] – Privileged/Unprivileged:
 0: Unprivileged access

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  1: Privileged access
 Hint: HPROT [0] is just a hint and may not always be exact.

2.8 BUS INTERCONNECTION

 Interconnect
 Address decoding
 Read data and response multiplexor

Interconnect
 Interconnect connects Managers (Masters) and Subordinates (Slaves) in a system.
 Single Manager system: uses only a Decoder and a Multiplexor to connect to Subordinates.
 Multi-Manager system: needs an Interconnect that handles
o Arbitration (decides which Manager can use the bus)
o Routing (sends address, control, and data to the right Subordinate).
o Multi-layer AHB systems allow multiple Managers to work in parallel (details in ARM DVI 0045).
Address decoding
 Address Decoder generates HSELx signals to select each Subordinate (Slave).
 Use simple decoding for faster operation.
 A Subordinate samples HSELx, address, and control signals only when HREADY = HIGH.
 If HREADY = LOW, HSELx might change before the transfer ends.
 Each Subordinate gets a minimum 1KB address space, aligned to 1KB boundaries.
 Bursts never cross a 1KB boundary, ensuring correct decoding.

Default Subordinate
 Used when some address spaces are unused in the memory map.
 If a transfer goes to a nonexistent address, the default Subordinate gives an ERROR for NONSEQ/SEQ
transfers.
 For IDLE/BUSY transfers, it gives an OKAY response with zero wait state.

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Multiple Subordinate Select (HSELx)
 A single Subordinate can have multiple HSELx signals, each for a different address range.
 Each logical interface needs at least 1KB address space.
 This allows one Subordinate to handle multiple address regions (like data path and control registers)
without extra decode logic.
Read data and response multiplexor
 The AHB protocol is used with a read data multiplexor interconnection scheme.
 The Manager drives out the address and control signals to all the Subordinates, with the decoder selecting
the appropriate Subordinate during the data phase of the transfer.
 Any response data from the selected Subordinate, passes through the read data multiplexor to the Man-
ager.

2.9 Interconnect with AHB interfaces

Generic interconnect products support multiple interface options like AHB, AXI, and APB.

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  An interconnect with AHB interfaces connects Managers and Subordinates.
 The Manager side uses HTRANS to show valid transfers and a single HREADY to handle wait states
or arbitration delays.
The Subordinate side has HSEL and two HREADY signals:
 HREADYOUT (from Subordinate) tells Managers to wait.
 HREADY (from interconnect) can pause the Subordinate if needed.
 Alternatively, HSEL can always be HIGH, and the interconnect sets HTRANS = IDLE for unused Sub-
ordinates.

2.10 Slave Response Signaling

Slave transfer responses
 Once a Manager starts a transfer, the Subordinate controls its progress–the Manager can’t cancel it.
 The Subordinate sends a response using HRESP (and HREADYOUT) to show the transfer’s status.
 For systems with AHB5 Exclusive Transfers, there’s an extra signal called HEXOKAY for exclusive ac-
cess.
HRESP Response Description
0 OKAY The transfer is either done or
needs more cycles.
HREADYOUT shows if it’s
still pending or complete.
1 ERROR An error happened during the
transfer. The Manager is
notified, and the error
response takes two cycles –
HREADYOUT is asserted in
the second one.

Transfer done
A successful completed transfer is signaled when HREADY is HIGH and HRESP is OKAY.
Transfer pending
A Subordinate uses HREADYOUT to add wait states during a transfer.
When done, it sets HREADYOUT=HIGH and HRESP=OKAY to show the transfer finished successfully.

2.11 Error Response

 A Subordinate uses the ERROR response to show something went wrong, like trying to write to read-
only memory.
 OKAY takes 1 cycle, but ERROR needs 2 cycles.
 In the first cycle, it sets HRESP = HIGH (ERROR) and HREADYOUT = LOW to delay the transfer.

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  In the second cycle, HREADYOUT = HIGH to finish, and HRESP stays HIGH (still ERROR).
 The 2-cycle delay gives the Manager time to stop the next transfer.
 If more time is needed, the Subordinate can add extra wait states first with HREADYOUT = LOW and
HRESP = OKAY.

T1–T2: Subordinate adds a wait state and gives OKAY.

T2–T3: Starts ERROR response (HREADY = LOW).
T3–T4: Finishes ERROR response (HREADY = HIGH), and the Manager sets the next transfer to IDLE,
canceling it.
T4–T5: Subordinate gives OKAY again.
If an ERROR happens, the Manager can stop the rest of the burst or keep going.
For read errors, the Subordinate should drive HRDATA = 0, since the Manager might still read the data.
Data buses
 An AHB system needs separate read (HRDATA) and write (HWDATA) data buses.
 The recommended bus width is 32 bits, but it can be changed.
 Endianness defines how data bytes are ordered.
HWDATA: The Manager sends write data. If the transfer is delayed (HREADY = LOW), it keeps the data
valid until HREADY = HIGH. For smaller transfers (like 16-bit on a 32-bit bus), only the needed byte lanes are
used.
HRDATA: The Subordinate sends read data. It only provides valid data in the last cycle (HREADY = HIGH).
For smaller transfers, only active byte lanes carry valid data. No valid data is needed for ERROR responses.

Endianness
 AHB supports little-endian and big-endian systems:
 BE8 (byte-invariant big-endian): 8-bit accesses use the same bus bits as little-endian.
 BE32 (word-invariant big-endian): 32-bit accesses use the same bus bits for MS and LS bytes as little-
endian.
 AHB5 uses the Endian property to specify which big-endian form is used.

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  The equations use the following variables:
Address The address of the transfer.
Data_Bus_Bytes The number of 8-bit data bus byte lanes.
INT(x) Rounded down integer value of x.

Little-endian:
LS byte goes to the transfer address.
Higher bytes go to increasing addresses.
Byte access uses Byte_Lane = Address % Data_Bus_Bytes.
Data is transferred on DATA[(8 × Byte_Lane) + 7 : (8 × Byte_Lane)]

Byte-invariant big-endian (BE8):

Same as little-endian for byte access.
For larger transfers, MS byte goes to the transfer address, then decreasingly significant bytes to higher ad-
dresses.
Byte_Lane = Address –(INT(Address / Data_bus_Bytes)) × Data_Bus_Bytes
Data is transferred on DATA[(8 × Byte_lane) + 7 : (8 × Byte_lane)].

Word-invariant big-endian (BE32):

Bytes in a 32-bit word are reversed on the bus.
MS byte of the word is placed on the lowest address byte lane.
Address_Offset = Address –(INT(Address / Data_Bus_Bytes)) × Data_bus_Bytes
Word_Offset = (INT(Address_Offset / 4)) × 4
Byte_Offset = Address_Offset – Word_Offset
Data is transferred on DATA[(8 × (Word_Offset + 3 – Byte_Offset)) + 7 : 8 × (Word_Offset + 3 – Byte_Off-
set)]
For a 32-bit bus, the Word_Offset will always be zero and therefore the equation simplifies to:
DATA[(8 × (3 – Byte_Offset)) + 7 : 8 × (3 – Byte_Offset)]
In short: little-endian sends LS first, BE8 sends MS first, BE32 reverses bytes within each word.
Word-invariant big-endian (BE32):
For half-word/word transfers: MS byte → transfer address, then decreasingly significant bytes to higher
addresses.
For larger-than-word transfers: split into words; LS word → transfer address, then higher words to increasing
addresses.
Data bus notes: 32-bit bus can be wider.
Burst transfers smaller than the bus use different active byte lanes each beat.
Little-endian and byte-invariant big-endian use the same byte lanes, but MS and LS bytes are swapped.

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 Transfer size Address offset DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0]
Word 0 Active[MS] Active Active Active[LS]
Halfword 0 - - Active[MS] Active[LS]
Halfword 2 Active[MS] Active[LS] - -
Byte 0 - - - Active
Byte 1 - - Active -
Byte 2 - Active - -
Byte 3 Active - - -

Clock and Reset requirements

Clock (HCLK):
 All components use one clock, HCLK.
 Inputs are sampled on the rising edge; outputs change after the rising edge.
 Some signals must stay stable during extended transfers, but glitches between edges are implementation-
dependent.
AHB5 Stable_Between_Clock property:
True → signals stay stable and glitch-free.
False/undefined → signals may glitch between edges.

Reset (HRESETn):
 Active LOW, can be asserted asynchronously, but released synchronously with HCLK.
 Must be asserted long enough to fully reset components.
During reset:
Managers keep address/control signals valid and HTRANS = IDLE.
Subordinates set HREADYOUT = HIGH.

2.12 Exclusive Transfers

Exclusive Access Monitor:
 Tracks Exclusive access sequences to see if an Exclusive Write succeeds or fails.
 Must monitor at least one address per Exclusive-capable Manager.
 Can be placed centrally or at each memory controller.
 Not all addresses need Exclusive access; typically used for main memory, not peripherals.

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Exclusive access signals:
HEXCL: Marks a transfer as part of an Exclusive sequence.
HMASTER: Identifies the Manager/thread; ensures uniqueness for the monitor.
HEXOKAY: Shows if the Exclusive transfer succeeded.
Notes: HMASTER width varies (recommendation: 4 bits for interconnect, 8 bits for Subordinate/monitor).
HMASTER must be valid for all transfers, not just Exclusive ones.

Response signaling
HEXOKAY signal:
High: Exclusive Transfer succeeded (Exclusive Write updated memory).
Low: Exclusive Transfer failed:
o Address doesn’t support Exclusive Transfers, or
o Memory changed since the matching Exclusive Read.
Rules:
Assert only when HREADY = HIGH.
Only used for Exclusive Transfers.
Must not be asserted in the same cycle as HRESP.

Note: If only one Manager accesses the location, the Subordinate can always signal success.
Calculation for wrap
lower boundary
(start_address / 2^HSIZE x HBURST) x 2^HSIZE x HBURST
upper boundary
lower boundary + 2^HSIZE x HBURST

Real-life uses of AHB (Advanced High-performance Bus):

1. ARM-based SoCs – Used in smartphones, tablets, and embedded devices for connecting CPUs, memory, and
peripherals.
2. Microcontrollers (MCUs) – For high-speed communication between cores and peripherals (e.g., STM32
series).
3. Memory systems – Fast access between processors and DRAM/Flash in embedded systems.
4. Graphics and multimedia – Transfers large data blocks (video frames, images) efficiently using burst mode.

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 5. Networking equipment – Routers and switches use AHB for processor-memory-peripheral communication.
6. Industrial control systems – Connecting sensors, controllers, and actuators with reliable high-speed transfers.
7. Automotive electronics – Infotainment systems and advanced driver-assistance systems (ADAS) use AHB
for CPU-peripheral data exchange.
8. FPGA-based designs – AHB is used in custom SoCs implemented on FPGAs for rapid prototyping.

FEATURES APPLICATIONS
Single-clock synchronous bus. Embedded systems and SoC.
Supports multiple bus masters and slaves. ARM-based mircocontrollers and processors.
Separate read/write data buses for high throughput. Memory-mapped peripherals in high-performance
systems.
Pipelined operation to overlap address and data Multi-master systems requiring burst transfers.
phases.

ADVANTAGES DISADVANTAGES
High performance due to pipelining and burst More complex than APB.
transfers.
Flexible multi-master support with arbitration. Requires careful timing and signal stability design.
Easier integration with AMBA AXI/APB systems. Hardware cost and area overhead higher due to
pipelining and multiple signals.
Exclusive access support allows safe multi-master Implementation defined behaviors (like glitches
memory updates. between clock edges) may complicate verification.

2.13 Interview Questions

1. What is AHB?
2. What are the main features of AHB?
3. Explain the AMBA bus hierarchy (APB, AHB, AXI)?
4. What is the difference between HWDATA and HRDATA?
5. What is the role of HCLK and HRESETn in AHB?
6. What are the HTRANS signal types?
7. What is the purpose of HREADY signal?
8. What does HSEL indicate in AHB?
9. What is the function of HADDR?
10. Explain HSIZE signal and its importance.

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 11. What is the role of HBURST?
12. How does HMASTER signal help in multi-master systems?
13. What is pipeline transfer in AHB?
14. How is a write transfer performed in AHB?
15. How is a read transfer performed in AHB?
16. Can AHB perform back-to-back read/write operations?
17. How does AHB support burst transfer?
18. How is data alignment handled in AHB?
19. What is the difference between single, incrementing, and wrapping burst transfers?
20. How does byte-enable work in AHB?
21. Explain HRESP signal in detail.
22. What are the SPLIT and RETRY responses in AHB?
23. What happens if a slave takes too long to respond?
24. How are error conditions indicated to the master?
25. What is the role of HREADYOUT from a slave?
26. How is exclusive access handled in AHB5?
27. What is the HEXOKAY signal used for?
28. What happens if two masters request the bus at the same time?
29. How does AHB handle multiple slaves?
30. Explain arbitration in AHB.
31. What are the different arbitration schemes used?
32. What is the difference between locked and unlocked transfers?
33. Explain endianness support in AHB.
34. What is byte-invariant vs word-invariant big-endian?
35. How does AHB handle split transactions?
36. How is burst transfer efficiency improved in AHB?
37. What is the purpose of separate read and write data buses?
38. Lower and upper boundary wrap calculation by giving starting address addr = 0x24, length = 8, transfer
size = 32bits?

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 AXI
(ADVANCED EXTENSIBLE INTERFACE)

3 Introduction

AXI, the third generation of AMBA interface AMBA 3 specification, is targeted at high-performance, high
clock frequency system designs and suitable for high speed sub-micrometer interconnect :
 Separate address/control and data phases.
 Support for unaligned data transfers using byte strobes.
 Burst based transactions with only start address issued and issuing of multiple outstanding addresses.
 Easy addition of register stages to provide timing closure.

3.1 Architecture

The AXI protocol is burst-based and uses separate channels:

 Address channel: tells what data will be transferred.
 Data channels: master → slave for writes, slave → master for reads.
 Write response channel: slave confirms write completion.
It allows multiple transactions, out-of-order completion, and sending address before data.
The AXI protocol enables:
 Address information to be issued ahead of the actual data transfer.
 Support for multiple outstanding transactions.
 Support for out-of-order completion of transactions.

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 Each channel has:
– Information signals.
– Valid and ready handshake.
– AXI consists of five different channels
1. Write address channel
2. Write data channel
3. Write response channel
4. Read address channel
5. Read data channel

3.2 Channel Definition

Each of the five independent channels consists of a set of information signals and uses a two-way VALID and
READY handshake mechanism.
 The VALID signal shows that data or control info is ready.
 The READY signal shows the receiver can accept the data.

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  The LAST signal marks the final data transfer in a transaction.

1. Write address channel

The write address channel carries the address and control information from the master to the slave to tell whee
the data should be written.

2. Write data channel

The write data channel carries the actual data from the master to the slave along with byte strobes and a LAST
signal to mark the final data.

3. Write response channel

The write response channel sends a response from the slave back to the master to show if the write was
successful or if there was an error.

4. Read address channel

The read address channel carries the address and control information from the master to the slave to tell where
the data should be read from.

5. Read data channel

The read data channel sends the requested data and response information from the slave back to the master,
including a LAST signal for the final data.

3.3 Signal Description

SIGNAL SOURCE DESCRIPTION

ACLK Clock source Global clock signal. All signals
are sampled on the rising edge of
the global clock.
ARESETn Reset source Global reset signal. This signal is
active LOW.

Write address channel signals

SIGNAL SOURCE DESCRIPTION

AWID[3:0] Master ID tag for the write address
AWADDRS[31:0] Master Starting address for the write
burst.
AWLEN[3:0] Master Number of data transfers in the
burst.
AWSIZE[2:0] Master Size of each data transfer.
AWBURST[1:0] Master Type of burst(how address
change).
AWLOCK[1:0] Master Indicates locked or atomic

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 transfer.
AWCACHE[3:0] Master Cache and buffer attributes.
AWPROT[2:0] Master Protection level(privileged,
secure, instruction/data).
AWVALID Master Master says address/control info
is valid.
1 = address and control
information available
0 = address and control
information not available.
AWREADY Slave Slave says it’s ready to accept
the address.
1 = Slave ready.
0 = Slave not ready.

Write data channel signals

SIGNAL SOURCE DESCRIPTION

WID[3:0] Master Write data ID(same as AWID)
WDATA[31:0] Master Actual write data.
WSTRB[3:0] Master Byte enable – shows which bytes
are valid.
WLAST Master Marks the last data in valid.
WVALID Master Master says data is valid.
1 = write data and strobes
available.
0 = write data and strobes not
available.
WREADY Slave Slave says it’s ready to receive
data.
1 = slave ready.
0 = slave not ready.

Write response channel signals

SIGNAL SOURCE DESCRIPTION

BID [3:0] Slave Response ID (same as AWID of
the write).
BRESP [1:0] Slave Write status (OKAY, EXOKAY,
SLVERR, DECERR).
BVALID Slave Slave says response is valid.

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 BREADY Master Master ready to accept the
response.

Read address channel signals

SIGNAL SOURCE DESCRIPTION

ARID [3:0] Master Read address ID tag.
ARADDR [31:0] Master Starting address for the read
burst.
ARLEN [3:0] Master Number of transfers in the burst.
ARSIZE [2:0] Master Size of each data transfer.
ARBURST [1:0] Master Type of burst (how next
addresses are calculated).
ARLOCK [1:0] Master Lock/atomic transfer info.
ARCACHE [3:0] Master Cache/buffer attributes.
ARPROT [2:0] Master Protection level (privilege,
security, data/instruction).
ARVALID Master Master says address/control info
is valid.
1 = address and control
information valid.
0 = address and control
information not valid.
ARREADY Slave Slave ready to accept address
and control.
1 = Slave ready.
0 = Slave not ready.

Read data channel signals

SIGNAL SOURCE DESCRIPTION

RID [3:0] Slave Read data ID (same as ARID).
RDATA [31:0] Slave Actual read data.
RRESP [1:0] Slave Read status (OKAY, EXOKAY,
SLVERR, DECERR)
RLAST Slave Marks the last data in a read
burst.
RVALID Slave Slave says data is valid.
RREADY Master Master ready to receive data.

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3.4 Channel Handshake

In the AXI protocol, the channel handshake is the process used to transfer data or control information between
the master and slave safely and efficiently.

Handshake process

 All five channels use the VLAID/READY handshake for data and control transfer.
 VALID (from source) shows data is ready.
 READY (from destination) shows it can accept data.
 Data transfers only when both are HIGH.
 No direct (combinational) connection is allowed between input and output signals on master or slave.

 The source sets VALID high when data is ready.

 The data stays stable until the destination sets READY high.
 Transfer occurs when both VALID and READY are high.

 The destination sets READY HIGH before data is valid.

 This means it can accept the data as soon as VALID goes HIGH.
 Transfer happens when both READY and VALID are HIGH.

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  If VALID and READY are HIGH in the same cycle, the transfer happens immediately.

The individual AXI protocol channel handshake mechanisms are described in:

TRANSACTION CHANNEL HANDSHAKE PAIR

Write address channel AWVALID, AWREADY
Write data channel WVALID, WREADY
Write response channel BVALID, BREADY
Read address channel ARVALID, ARREADY
Read data channel RVALID, RREADY

Write address channel

 The master sets AWVALID only when the address and control info are valid and keeps it HIGH until
the slave responds with AWREADY.
 AWREADY default can be HIGH or LOW. High is recommended so the slave can accept addresses
immediately.
 If AWREADY is LOW, the transfer takes at least two cycles.

Write data channel

 The master sets WVALID only when write data is valid and keeps it HIGH until the slave asserts
WREADY.
 WREADY can default to HIGH if the slave can always accept data is one cycle.
 WLAST is asserted by the master for the final data transfer in a burst.
 When WVALID is LOW, WSTRB [3:0] can be any value, but should be LOW or unchanged.

Write response channel

 The slave sets BVALID only when the write response I valid and keeps it HIGH until the master asserts
BREADY.
 BREADY can default to HIGH if the master can always accept the response in one cycle.

Read address channel

 The master sets ARVALID only when the read address is valid and keeps it HIGH until the slave asserts
ARREADY.
 ARREADY can default to HIGH or LOW; HIGH is recommended for single-cycle acceptance.
 If ARREADY is LOW, the transfer takes at least two cycles.

Read data channel

 The slave sets RVALID only when read data is valid and keeps it HIGH until the master asserts
RREADY.
 RREADY can default to high if the master can always accept data immediately.
 RLAST is asserted by the slave for the final data transfer in a burst.

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Relationships between Channels
 Write data can arrive before, with, or after the write address, depending on channel stages.
 Interconnects must align address and write data to ensure it goes to the correct slave.
 Read data must always follow its address.
 Write response must always follow the last write data of its transaction.

3.5 Dependencies between channel handshake signals

 To avoid deadlock, VALID must not depend on the other side’s READY.
 READY can wait for VALID to be asserted.
 The single-headed arrows point to signals that can be asserted before or after the previous signal is
asserted. Double-headed arrows point to signals that must be asserted only after assertion of the previous
signal.

 The slave can wait for ARVALID to be asserted before it asserts ARREADY.
 The slave must wait for both ARVALID and ARREADY to be asserted before it starts to return read
data by asserting RVALID. (Fig: 3-4)

 The master must assert AWVALID/WVALID without waiting for AWREADY/WREADY.

 The slave can wait for AWVALID or WVALID before asserting AWREADY or WREADY.
 The slave must wait for both WVALID and WREADY before asserting BVALID. (Fig: 3-5).

Addressing Options
 This chapter describes AXI burst types and how to calculate addresses and byte lanes for transfers
within a burst. It contains the following sections:
About addressing options:
 AXI uses burst transfers, with the master sending the first address and control info.
 The slave calculates addresses for the rest of the burst.
 Bursts cannot cross 4 KB boundaries to stay within a single slave and simplify address calculation.

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Burst-length

The AWLEN or ARLEN signal specifies the number of data transfers that occur within each burst.

ARLEN[3:0] Number of data transfers

AWLEN[3:0]
b0000 1
b0001 2
b0010 3
.
.
.
b1101 14
b1110 15
b1111 16

 For wrapping bursts, the length of the burst must be 2, 4, 8, or 16 transfers.

 Every burst must complete the number of transfers set by ARLEN or AWLEN.
 Bursts cannot end early.
 During a write burst, the master can disable strobes but must complete all transfers.
 During a read burst, the master can discard data but must complete all transfers.

Burst Size
How the ARSIZE or AWSIZE signal specifies the maximum number of data bytes to transfer in each beat, or
data transfer, within a burst.

ARSIZE[2:0] Bytes in transfer

AWSIZE[2:0]
b000 1
b001 2
b010 4
b011 8
b100 16
b101 32
b110 64
b111 128

 AXI uses the transfer address to select which byte lanes to use.
 Incrementing/wrapping bursts use different lanes for each beat; fixed bursts use the same lanes.

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  Transfer size cannot exceed the data bus width.

Burst Type
The AXI protocol defines three burst types described in:
1. Fixed burst
2. Incrementing burst
3. Wrapping burst

ARBURST[1:0] Burst type Description Access

AWBURST[1:0]
b00 FIXED Fixed-address burst FIFO-type
b01 INCR Incrementing-address Normal sequential
burst memory
b10 WRAP Incrementing-address Cache line
nurst that wraps to a
lower address at the
wrap boundary
b11 Reserved - -

Fixed Burst
In a fixed burst, the address remains the same for every transfer in the burst. This burst
type is for repeated accesses to the same location such as when loading or emptying a peripheral FIFO.

Incrementing burst
In an incrementing burst, each transfer address increases from the previous one.
The increment amount equals the transfer size (e.g., +4 for 4-byte transfers).

Wrapping burst
A wrapping burst works like an incrementing burst but the address wraps around after reaching a set boundary.
The wrap boundary = transfer size × number of transfers.

Rules:
Start address must be aligned to the transfer size.
Burst length must be 2, 4, 8, or 16.

Burst Address

This section provides some simple formulas for determining the address and byte lanes of transfers within a
burst. The formulas use the following variables:

Start_Address The start address issued by the master.

Number_Bytes The maximum number of bytes in each data transfer.

Data_Bus_Bytes The number of byte lanes in the data bus.

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Aligned_Address The aligned version of the start address.

Burst_Length The total number of data transfers within a burst.

Address_N The address of transfer N within a burst. N is an integer from 2-16.

Wrap_Boundary The lowest address within a wrapping burst.

Lower_Byte_Lane The byte lane of the lowest addressed byte of a transfer.

Upper_Byte_Lane The byte lane of the highest addressed byte of a transfer.

INT(x) The rounded-down integer value of x.

Use these equations to determine addresses of transfers within a burst:

 Start_Address = ADDR
 Number_Bytes = 2SIZE
 Burst_Length = LEN + 1
 Aligned_Address = (INT(Start_Address / Number_Bytes) ) x Number_Bytes.

Use this equation to determine the address of the first transfer in a burst:
 Address_1 = Start_Address.

Use this equation to determine the address of any transfer after the first transfer in a burst:
 Address_N = Aligned_Address + (N – 1) x Number_Bytes.

For wrapping bursts, the Wrap_Boundary variable is extended to account for the wrapping boundary:
 Wrap_Boundary = (INT(Start_Address / (Number_Bytes x Burst_Length))) x (Number_Bytes x
Burst_Length).

If Address_N = Wrap_Boundary + (Number_Bytes x Burst_Length), use this equation:

 Address_N = Wrap_Boundary

Use these equations to determine which byte lanes to use for the first transfer in a burst:
 Lower_Byte_Lane = Start_Address - (INT(Start_Address / Data_Bus_Bytes))
x Data_Bus_Bytes
 Upper_Byte_Lane = Aligned_Address + (Number_Bytes - 1) -
(INT(Start_Address / Data_Bus_Bytes)) x Data_Bus_Bytes.

Use these equations to determine which byte lanes to use for all transfers after the first
transfer in a burst:
 Lower_Byte_Lane = Address_N – (INT(Address_N / Data_Bus_Bytes))
x Data_Bus_Bytes
 Upper_Byte_Lane = Lower_Byte_Lane + Number_Bytes – 1.

Data is transferred on:

 DATA[(8 x Upper_Byte_Lane) + 7 : (8 x Lower_Byte_Lane)].

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3.6 System-level Caches and Protection Units
It contains the following sections:
 Cache support
 Protection unit support

Cache support
 ARCACHE and AWCACHE signals give cache-related info for reads and writes.
 They define if data can be buffered, cached, or allocated in the cache.
Bits meaning:
 [0] Bufferable (B): Transaction can be delayed (mainly for writes).
 [1] Cacheable (C): Data can be merged (writes) or prefetched/reused (reads).
 [2] Read Allocate (RA): Allocate in cache on a read miss (only if C = 1).
 [3] Write Allocate (WA): Allocate in cache on a write miss (only if C = 1).
– The encoding of the ARCACHE [3:0] and AWCACHE[3:0] signals.

ARCACHE[3:0] Transaction attributes

AWCACHE[3:0]
WA RA C B
0 0 0 0 Noncacheable and nonbufferable
0 0 0 1 Bufferable only
0 0 1 0 Cacheable, but do not allocate
0 0 1 1 Cacheable and bufferable, but do not
allocate
0 1 0 0 Reserved
0 1 0 1 Reserved
0 1 1 0 Cacheable write-trough, allocate on reads
only
0 1 1 1 Cacheable write-back, allocate on reads
only
1 0 0 0 Reserved
1 0 0 1 Reserved
1 0 1 0 Cacheable write-through, allocate on
writes only
1 0 1 1 Cacheable write-back, allocate on writes
only
1 1 0 0 Reserved

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 1 1 0 1 Reserved
1 1 1 0 Cacheable write-through, allocate on both
reads and writes
1 1 1 1 Cacheable write-back, allocate on both
reads and writes

 AWCACHE decides who gives the write response.

 If bufferable, a bridge or cache can respond.
 If non-bufferable, the final destination must respond.
 AXI doesn’t define how buffered or cached data is sent to its destination — this is handled by cache or
bridge control logic (e.g., flushing or draining buffers).

Protection Unit Support

AWPROT and ARPROT signals provide three levels of access protection to prevent illegal transactions in
complex systems.

Normal or privileged, ARPROT[0] and AWPROT[0]

LOW indicates a normal access

HIGH indicates a privileged access.

This is used by some masters to indicate their processing mode. A privileged processing mode typically has a
greater level of access within a system.

Secure or Non-secure, ARPROT[1] and AWPROT[1]

LOW indicates a secure access

HIGH indicates a non-secure access.

This is used in systems where a greater degree of differentiation between processing modes is required.

Instruction or Data, ARPROT[2] and AWPROT[2]

LOW indicates a data access.

HIGH indicates an instruction access.

This bit gives an indication if the transaction is an instruction or a data access.

ARPROT[2:0] Protection level

AWPROT[2:0]
[0] 1 = privileged accesse
0 = normal access
[1] 1 = non-secure access

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 0 = secure access
[2] 1 = instruction access
0 = data access

3.7 Atomic Accesses

AXI protocol implements exclusive access and locked access mechanisms. It contains the following sections:
 About atomic accesses
 Exclusive access
 Locked access

About Atomic Access

To enable the implementation of atomic access primitives, the ARLOCK [1:0] or AWLOCK [1:0] signal
provides exclusive access and locked access.

ARLOCK[1:0] Access type

AWLOCK[1:0]
b00 Normal access
b01 Exclusive access
b10 Locked access
b11 Reserved

Exclusive Access
 Exclusive access allows semaphore-like operations without locking the bus, keeping speed and
bandwidth high.
 ARLOCK/AWLOCK select exclusive access, and RRESP/BRESP show success or failure.
 The slave needs extra logic to support it, and AXI includes a fail-safe if the slave doesn’t support
exclusive access.

Exclusive Access Process

The basic process for an exclusive access is:

 A master performs an exclusive read from an address location.
 At some later time, the master attempts to complete the exclusive operation by performing an exclusive
write to the same address location.
The exclusive write access of the master is signalled as:
 Successful if no other master has written to that location between the read and write accesses.
 Failed if another master has written to that location between the read and write accesses. In this case the
address location is not updated.

Exclusive Access from the Perspective of the Master

A master starts exclusive access with an exclusive read, getting EXOKAY if the slave records the address.
Later, it does an exclusive write to the same address:

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  If the address didn’t change, the write succeeds and returns EXOKAY.
 If the address changed, the write fails and returns OKAY (no update).
 If the master skips the write, the slave keeps monitoring until a new exclusive read starts.
 The write must happen only after the read is complete.

Exclusive Access from the Perspective of the Slave

 A slave without exclusive access support ignores ARLOCK/AWLOCK and always returns OKAY.
 A slave with exclusive access needs a monitor unit to track exclusive reads and writes.
 The monitor records the address and ID of an exclusive read and watches for changes.
 If an exclusive write matches the monitored address (no changes), it succeeds and returns EXOKAY.
 If the address was changed or the monitor reset, the write fails and returns OKAY.

Exclusive Access Restrictions

 Exclusive write must match the size and length of its preceding exclusive read.
 The address must be aligned and identical for both read and write.
 ARID (read ID) must match AWID (write ID).
 Control signals for both must be the same.
 Transfer size must be a power of 2 (1–128 bytes), with 128 bytes max.
 ARCACHE/AWCACHE must ensure the slave monitoring exclusivity sees the transaction (not
cacheable).
 Ignoring these rules causes unpredictable behavior.
 The slave must monitor at least the number of bytes in the transaction (up to 128 bytes).

Slaves that do not support Exclusive Accesses

 BRESP [1:0] and RRESP [1:0] signals indicate the result of a transaction.
 OKAY response shows a successful normal access.
 EXOKAY response shows a successful exclusive access.
 Slaves that do not support exclusive access return OKAY for exclusive access attempts.

Locked Access
 ARLOCK [1:0] or AWLOCK [1:0] signals indicate a locked transfer.
 During a locked transfer, only that master can access the slave region.
 The interconnect arbiter enforces the lock.
 A master must have no other outstanding transactions before starting a locked sequence.
 A locked sequence must end with a final transaction that is not locked to remove the lock.
 The final unlocking transaction must complete before any new transactions start.
 All transactions in a locked sequence must use the same ARID or AWID.

The following restrictions are recommended but not mandatory:

 Keep all locked transaction sequences within the same 4KB address region.
 Limit locked transaction sequences to two transactions.

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3.8 Response Signaling

About response signaling

The AXI protocol allows response signalling for both read and write transactions. For read transactions the
response information from the slave is passed alongside the read data itself, however for writes the response
information is conveyed along the write response channel.

The AXI protocol responses are:

 OKAY
 EXOKAY
 SLVERR
 DECERR.

RRESP[1:0] RESPONSE DESCRIPTION

BRESP[1:0]
b00 OKAY Normal access successful or exclusive access failed.
b01 EXOKAY Exclusive access successful.
b10 SLVERR Slave reached but returned an error.
b11 DECERR No slave found at the transaction address.

 In a write transaction, there is one response for the entire burst, not for each data item.
 In a read transaction, the slave can give different responses for each transfer in a burst.
 Even if an error occurs, all data transfers must still complete.
 For example, if 8 reads are requested and an error happens, all 8 transfers still occur with error
responses.
 The burst is not canceled after a single error.
 Masters handling multiple outstanding addresses must be able to manage error responses from earlier
transfers while later ones continue.

Response Types
This section describes the four AXI protocol response types:
 Normal access success
 Exclusive access
 Slave error
 Decode error.

Normal access success:

The OKAY response indicates:
 The success of a normal access
 The failure of an exclusive access
 An exclusive access to a slave that does not support exclusive access.
 OKAY is the response for most transactions.

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Exclusive access
The EXOKAY response indicates the success of an exclusive access.

Slave error

The SLVERR response indicates an unsuccessful transaction. Examples of slave error conditions are:
 FIFO/buffer overrun or under-run condition
 Unsupported transfer size attempted
 Write access attempted to read-only location
 Timeout condition in the slave
 Access attempted to an address where no registers are present
 Access attempted to a disabled or powered-down function.
To simplify system monitoring and debugging, it is recommended that error responses are used only for error
conditions and not for signaling normal, expected events.

Decode error

 A decode error (DECERR) happens when no slave exists for a given address.
 The inter-connect sends the transaction to a default slave, which returns the DECERR response.
 The default slave can log error details to help with debugging.
 Even with a DECERR, all data transfers must still complete as per AXI rules.

3.9 Ordering Model

How the AXI protocol uses transaction ID tags to enable the issuing of multiple outstanding addresses and out-
of-order transaction processing. It contains the following sections:
About the ordering model
 Transfer ID fields
 Read ordering
 Normal write ordering
 Write data interleaving
 Read and Write interaction
 Interconnect use of ID
 Recommended width of ID fields

About Ordering Model

 AXI allows out-of-order transaction completion and multiple outstanding addresses for better
performance.
 These features help achieve high data throughput and system efficiency.
 ID signals manage out-of-order transactions by treating each ID as a separate ordered stream.
 Transactions with the same ID must stay ordered, but different IDs can complete in any order.

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The five transaction IDs are:
 AWID The ID tag for the write address group of signals.
 WID The write ID tag for a write transaction. Along with the write data, the master transfers a WID to
match the AWID of the corresponding address.
 BID The ID tag for the write response. The slave transfers a BID to match the AWID and WID of the
transaction to which it is responding.
 ARID The ID tag for the read address group of signals.
 RID The read ID tag for a read transaction. The slave transfers an RID to match the ARID of the
transaction to which it is responding.
Masters can send multiple addresses without waiting for earlier ones to finish, allowing parallel processing.
Out-of-order completion lets faster transactions finish first, improving performance and reducing latency.

Transfer ID Fields
 ID fields (ARID/AWID) let a master issue multiple independent transactions.
 Different masters or different IDs can complete in any order.
 Same ID (AWID or ARID) transactions must complete in order.
 Reads with the same ARID must return in the order issued — handled by the slave or interconnect.
 No fixed order between reads and writes with the same ID — the master must manage the order if
needed.

Read Ordering
 Same ARID: Read data must return in the same order as issued.
 Different ARIDs: Read data can return in any order or be interleaved.
 Slave: Must return data with RID = ARID and keep order for the same ARID.
 Interconnect: Ensures reads with the same ARID from different slaves complete in order.
 Read reordering depth: Number of pending reads that can be reordered; if all are in order, depth = 1.

Normal Write Ordering

 If a slave doesn’t support write data interleaving, the master must send write data in the same order as
the addresses.
 Most slaves require data and address order to match.
 If the interconnect merges writes from multiple masters, it must keep address order.
 These rules apply even when transactions have different AWID values.

Write Data Interleaving

 Write data interleaving allows a slave to accept interleaved write data with different AWID values.
 The interleaving depth shows how many pending addresses can receive data at once (default = 1).
 The first data for each transaction must arrive in the same order as the addresses.
 Interleaving helps improve performance, especially when mixing fast and slow data sources.
 Masters with only one AWID send data in order, while those with multiple AWIDs can interleave.
 Slaves with interleaving depth > 1 must accept interleaved data continuously and not stall to reorder it.

Read and Write Interaction

 Read and write transactions can complete in any order — no built-in restrictions.
 If a master needs order, it must wait for the earlier transaction to finish before starting the next.
 A read is complete when the last read data is received.
 A write is complete only when the write response (BRESP) is received.

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  For peripherals, masters should wait for earlier transactions to complete before switching between read
and write.
 For memory regions, a master can check addresses — if they don’t overlap, it can issue new transactions
immediately.

Interconnect use of ID fields

 The inter-connect adds extra bits to master ID fields (ARID, AWID, WID) to make them unique.
 Masters don’t need to know each other’s ID values.
 Slave interfaces see wider ID fields than master interfaces.
 For read data, the interconnect uses the extra RID bits to route data to the correct master and removes
them before delivering it.
Recommended Width of ID fields

 Masters: use up to 4-bit transaction ID.

 Interconnect: add up to 4 extra bits for master port numbers.
 Slaves: support 8-bit IDs (can handle ordering), but if the slave processes transactions in order, ID logic
can be added later.

3.10 Data Buses

Describes transfers of varying sizes on the AXI read and write data buses and how the interface uses byte-
invariant endianness to handle mixed-endian transfers.
It contains the following sections:
 About the data buses
 Write strobes
 Narrow transfers
 Byte invariance

About the Data buses

 AXI has separate read and write data buses, so read and write can happen simultaneously.
 Masters’ transfers must be equal to or smaller than the bus width.

Write Strobes

 WSTRB signals indicate which bytes of the write data are valid.
 One strobe per 8 bits of the write data bus.
 A master must ensure that the write strobes are asserted only for byte lanes that can contain valid data as
determined by the control information for the transaction.

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Narrow Transfers
Narrow transfers use only certain byte lanes of the data bus.
In incrementing/wrapping bursts, the lanes change each beat; in fixed bursts, the lanes stay the same.

Byte Invariance

 AXI uses byte-invariant endianness, so each byte always goes to the same data bus wires and memory
address.
 Little-endian components connect directly; big-endian components need conversion.
 Some data structures mix endianness, e.g., little-endian headers with a big-endian payload, so byte-
invariant access is needed.

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  Byte invariance ensures that little-endian access to parts of the header information does not corrupt other
big-endian data within the structure.

3.11 Unaligned Transfers

 AXI allows unaligned transfers, where a burst can start at an address not matching the data width.
 Low-order address lines and byte strobes indicate which bytes are valid.

Examples
Figure 10-1, Figure 10-2 on page 10-4, and Figure 10-3 on page 10-4 show examples of aligned and unaligned
transfers on buses with different widths. Each row in the figures represents a transfer. The shaded cells indicate
bytes that are not transferred, based on the address and control information

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Clock and Reset
Clock and reset requirements
This section gives the requirements for implementing the ACLK and ARESETn signals.

Clock
Each AXI component uses a single clock signal, ACLK. All input signals are sampled on the rising edge of
ACLK. All output signal changes must occur after the rising edge of ACLK.
There must be no combinatorial paths between input and output signals on both master and slave interfaces.

Reset
ARESETn is active LOW; can assert asynchronously, de-assert synchronously.
During reset: masters set ARVALID, AWVALID, WVALID LOW, slaves set RVALID, BVALID LOW; other
signals don’t matter.
A master interface must begin driving ARVALID, AWVALID, or WVALID HIGH only at a rising ACLK edge
after ARESETn is HIGH.

Figure 11-1 shows the first point after reset that ARVALID, AWVALID, or WVALID, can be driven HIGH.

Real-Life Examples of AXI Usage

1. Smartphone & Tablets
 AXI is used in SoCs like ARM-based chips to connect CPU, GPU, memory, and peripherals.
 Example: ARM cortec-A processors in mobile devices use AXI to handle hih-speed data transfers
between cores, caches, and DDR memory.
2. FPGAs (Field-Programmable Gate Arrays)
 In Xilinx or Intel (Altera) FPGAs, AXI connects custom IP blocks, memory controllers, and
peripherals.
 Example: AXI Interconnect links multiple IP cores to shared DDR memory.
[Link] & Communication Systems
 Used in Ethernet controllers, PCIe interfaces, and high-speed data routers to manage fast data
streams.
4. Embedded Systems & Automotive
 Used in automotive SoCs for ADAS (Advanced Driver Assistance Systems), connecting CPUs,
sensors, and memory efficiently.

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 FEATURES APPLICATIONS
Burst-based transactions with only one address SoC designs for high-performance CPUs, GPUs,
DSPs
Supports unaligned data-transfer Memory controllers (DDR, SRAM, Flash
interfaces)
Separate the read and write channels Peripherals requiring high-speed data transfer
Supports optional low-power operation Multi-master systems where several masters share
common memory or peripherals

ADVANTAGES DISADVANTAGES
High performance Complexity
Separate read and write channels Resource usage
Flexible data width Potential for out-of-order data handling issues
Byte-level strobes and unaligned transfers Power consumption

3.12 Interview questions

1. Difference between interleaving and out-of-order?
2. Why IDs are used in channels?
3. How burst transactions is required, explain?
4. What are Unaligned transfers?
5. Explain handshake between Valid and Ready?
6. What is deadlock condition?
7. AXI has different channels, explain it?
8. Why there was no write response for each beat in burst write. But there is a separate read response for
each beat in a read burst?
9. What do you mean by multiple outstanding transactions? Why it useful?
10. If there are multiple outstanding transactions pending, how you will debug the issue?
11. What is the minimum and maximum data bus width supported in AXI?
12. Why don’t we have separate read response channel?
13. Difference between beat, burst, transaction?
14. What are burst types? Difference between Incr and Wrap?
15. Real time example of wrap condition?

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 16. Lower and upper boundary wrap calculation by giving starting addr = 0x24, length = 8, transfer size =
32bits?
17. What is lock signal/exclusive access in AXI with respect to higher level?
18. Write an assertion on handshake signals – ready and valid, ready comes after 5 cycles from the start of
valid high? Difference between AHB and AXI?
19. Explain the Channel concept?
20. How does AXI differ from simpler bus protocols like AHB?
21. Describe the process of arbitration in AXI for accessing shared resources?
22. How does AXI handle data synchronization across multiple clock domains?
23. Describe the AXI protocol's support for multi-layer interconnects?

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 DMA
(DIRECT MEMORY ACCESS)

4 Introduction

In many I/O interfacing applications and certainly in data acquisition systems, it is often necessary to transfer
data to or from an interface at data rates higher than those possible using simple programmed I/O loops.
Microprocessor controlled data transfers within the PC (using the IN (port) and OUT (port) instructions) require
a significant amount of CPU time and are performed at a significantly reduced data rate.
Further to this, the CPU cannot perform any other processing during program controlled I/O operations.

4.1 What is DMA?

 The transfer of data between a fast storage device such as magnetic disk and memory is often limited by
the speed of the CPU.
 Removing the CPU from the path and letting the peripheral device manage the memory buses directly
would improve the speed of transfer this transfer technique is called Direct Memory Access (DMA).

4.2 What is actually DMA?

 When data is ready for transfer, the board directs the system DMA controller to put it into in system
memory as soon ad possible.
 As soon as the CPU is able (which is usually very quickly), it stops interacting with the data acquisition
hardware and the DMA controller moves the data directly into memory.
 The DMA controller gets ready for the next sample by pointing to the next open memory location.
 The previous steps are repeated indefinitely, with data going to each open memory location in a
continuously circulating buffer.
 No interaction between the CPU and the board is needed.

4.3 DMA Signals

 DREQ0-DREQ3-DMA Request: These are four independent, asynchronous input signals to the DMA
channels through peripherals such as floppy disks and the hard disk.

 DACK0-DACK3-DMA Acknowledge: These are output lines to inform the individual peripheral that a
DMA is granted, DREQ and DACK are equivalent to handshake signals in I/O device’s.

 AEN and ADSTB – Additives Enable and Address Length: These are active high output signals that
are used to latch a high-order address byte to generate a 16-bit address.

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4.4 DMA Channels

 The 8237 DMA controller provided by IBM is a peripheral interface circuit for allowing peripheral
devices to directly transfer data to or from main memory.
 It includes four independent channels and may be expanded to any number of channels by cascadinf
additional controller chips.
 In the IBM architecture, two DMA controllers are used. One DMA controller is used for byte transfers,
and the second DMA controller is user for word (16-bit) transfers.

4.5 Different Modes of DMA operation

There are three different modes of DMA operations:

 Continuous DMA
 Cycle stealing
 Inter-leaved DMA

4.6 DMA Operational Modes and Settings

 Single
 A single byte (or word) is transferred. The DMA must release and re-acquire the bus for each
additional byte.
 This is commonly-used by devices that cannot transfer the entire block of data immediately.
 The peripheral will request the DMA each time it is ready for another transfer.

 Block / Demand
 Once the DMA acquires the system bus, an entire block of data is transferred, up to a maximum of 64k.
 If the peripheral needs additional time, it can assert the READY signal to suspend the transfer briefly.

4.7 Types

 Types of DMA
There are four popular types of DMA.
 Single-Ended DMA: In this type, the DMA controller is connected only to one device (usually either
the memory or the I/O device), and it directly controls data transfer.
 Dual-Ended DMA: The DMA controller is connected to both the source and the destination, typically
memory and an I/O device.
 Arbitrated-Ended DMA: In the systems with multiple DMA devices or masters, arbitration is needed
to decide which device gets control of the bus. It is more advanced than Dual-Ended DMA.
 Interleaved DMA: Interleaved DMA are those DMA that read from one memory address and write
from another memory address.

4.8 Working of DMA controller

 A DMA controller allows data transfer without CPU involvement.
 It transfers data directly between memory and peripherals (or memory-to-memory).

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  How DMA works

1. CPU initializes the DMA

CPU programs the DMA with:
 Source address
 Destination address
 Size of data to transfer
 Transfer mode (single burst, block, demand, etc.)
 CPU then send a DMA start command.

2. DMA requests the bus (DMARQ)

 DMA asserts a request signal to the bus (e.g., HRD – Hold request in 8237 DMA).

3. CPU gives the bus control

 CPU completes current instruction – releases bus by sending HLDA (Hold Acknowledge).
 Now DMA becomes the bus master.

4. DMA transfers data directly

DMA performs the transfer:

steps:
1. Read from source
2. Write to destination
3. Increment/decrement pointers
4. Repeat until count=0

5. DMA interrupts CPU after completion

Once done, DMA send interrupt signal to CPU:
 “Transfer Completed”
 CPU resumes execution

4.9 Bus-Master DMA Devices

 Bus-master DMA devices are by far the most common type of DMA devices on windows system.
 A bus-master DMA devices contains all the electronics and logic necessary to take control of, or
“master”, the bus on which it is located and to autonomously transfer data between the device’s buffer
and the host’s system memory.

4.10 System DMA Devices

 System DMA Devices are vestiges of the original IBM PC design.
 These devices rely on a DMA controller chip on the motherboard to perform data transfers.

Real life usage

DMA is used when data needs to be transferred fast without CPU being involved.
 Copying files from USB → RAM
 Audio/Video streaming (e.g., playing songs, movies)
 Network data transfer in Wi-Fi/Ethernet

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  Camera sensor → memory in phones
 PCIe, AHB, AXI systems where data moves without CPU load
 SSD reading/writing data
 Embedded systems: ADC → Memory, UART → Memory, SPI → Memory
Features of DMA
 Direct transfer between memory and peripherals.
 CPU is free during transfer.
 Supports burst transfers.
 Uses DMA controller with channels and priority.
 Interrupt-based completion signaling.
 Supports scatter–gather, circular buffer, auto-reload modes (in advanced DMA).

Applications of DMA
 Memory-to-Memory copy (fast data movement)
 High-speed I/O devices: SPI, I2C, UART, ADC, DAC
 Storage interfaces: SATA, PCIe, USB
 Graphics: Copying frame buffers
 Networking: Ethernet packet transfer
 Sensors: Camera, audio codecs

ADVANTAGES DISADVANTAGES

High speed data transfer without slowing CPU. Adds extra hardware cost (DMA controller).

CPU can handle other tasks. DMA + CPU memory access may cause bus con-
tention.

Reduces CPU cycles – performance improve- More complex system design and debugging.
ment.

Efficient for large data transfers. Requires proper synchronization; otherwise data
corruption can occur.

Lower power usage since CPU is idle. Interrupt overhead if too many small transfers.

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4.11 Interview Questions
1. What is DMA?
2. Why do we need DMA?
3. Where is DMA used in real life?
4. What are the main signals/inputs of a DMA controller?
5. What are the types of DMA transfer modes?
6. What is Scatter-Gather DMA?
7. What is the difference between simple DMA and multi-Channel DMA?
8. What is DMA Arbitration?
9. What is DMA burst transfer?
10. How does DMA request and acknowledge mechanism work?
11. What is Memory-to-Memory vs Memory-to-peripheral transfer?
12. What are the key blocks inside a DMA controller?
13. What is address increment logic in DMA?
14. What is DMA chaining?
15. What is DMA descriptor?
16. What is DMA interrupt functionality?
17. What is DMA errors? What is cyclic stealing?
18. How does DMA work with AXI/AHB bus? What is the difference between DMA and CPU transfer?

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 OFF-CHIP COMMUNICATION PROTOCOL

SPI
(SERIAL PHERIPHERAL INTERFACE)

5 Introduction

 The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named
by Motorola that operates in full duplex mode.
 Devices communicate in master/slave mode where the master device initiates the data frame.
Multiple slave devices are allowed with individual slave select (chip select) lines.
 During a data transfer the master always sends 8 to 16 bits of data o the slave, and the slave
always sends a byte of data to the master.
 Maximum data bit rate is one eighth of the input clock rate.
 One central device (Master), initiates communication with all slaves.
 No address decoding logic required.
 SPI master wishes to send the data to slave or request information from the slave, it activates
the clock signal.
 Master generates information on one line (MOSI) while samples (read) from another line
(MISO).

5.1 SPI pin Description

 SCLK – Serial Clock (output from master)
 MOSI – Master Output, Slave Input (output from master)
 MISO – Master Input, Slave Output (Output from master)
 SS – Slave Select (active low; output from master).

 SCLK: (Serial Clock Input/Output)

 The SPI used clock signal to synchronize the transfer of data across the SPI interface.
 The SCLK is always driven by the master and received by the slave, The clock is programmable
to be active high or active low.
 The SCLK is only active during a data transfer. Any other time, it is either in its inactive state,
or tri-stated.

 MISO: (Master in slave out Input/Output)

 The MISO signal is a unidirectional signal used to transfer serial data from the slave to the
master.
 When a device is a slave, serial data is output on this signal.
 When a slave device is not selected, the slave drives the signal high impedance.

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  MOSI: (Master out Slave in Input/Output)
 The MOSI signal is a unidirectional signal used to transfer serial data from the Master to the
Slave.
 When a device is a master, serial data is output on this signal.
 When a device is a slave, serial data is input on this signal.

 SS/CS: (Slave Select Input)

 The SPI slave select signal is an active low signal that indicates which slave is currently
selected to participate in a data transfer.
 Each slave has its own unique slave select signal input.
 The SSEL must be low before data transactions begin and normally stays low for the duration
of the transaction.
 If the SSEL signal goes high any time during a data transfer, the transfer is considered to be
aborted.
 In this event, the slave returns to idle, and any data that was received is thrown away. There are
no other indications of this exception.
 This signal is not directly driven by the master. It could be driven by a simple general purpose
I/O under software control.
 On the LPC2300 the SSEL pin can be used for different function when the SPI interface is only
used in Master mode.
For example, pin hosting the SSEL function can be configured as an output digital GPIO pin and it is
also used to select one of the SPI slaves.

5.2 Operation
 The SPI bus can operate with a single master device and with one or more slave devices.
SPI bus: single master and single slave

 If a single slave device is used, the SSEL pin may be fixed to logic low if the slave permits it.
 Some slaves require the falling edge (high->low transition) of the slave select to initiate an
action such as the MAX1242 by Maxim, an ADC, that start conversion an said transition.

5.3 Configuration
Two types multiple slave configuration:
1. Typical SPI bus: Master and independent Slaves
1. Daisy-Chained SPI bus: Master and cooperative slaves.

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5.4 Typical SPI Bus
 With multiple slave devices, an independent SSEL signal is required from the master for each
slave device (3).

 In the independent slave configuration, there is an independent slave select line for each slave.
This is the way SPI is normally used.
 Since the MISO pins of the slaves are connected together, they are required to be tri-state pins.

5.5 Daisy-Chained SPI Bus

Daisy-chained SPI bus: Master and cooperative slaves

 Some products with SPI us are designed to be capable being connected in a daisy chain
configuration, the first slave output being connected to the second slave input, etc.
 The SPI port of each slave is designed to send out during the second group of clock pulses an
exact copy of what it received during the first group of clock pulses.
 Such a feature only requires a single SSEL line from the master, rather than a separate SSEL
line for each slave.

Points
 Not have ack mechanism to confirm receipt of data and does not have flow control.
 SPI master, not have knowledge of whether slave exist or not.
 Not particular addressing scheme.
 Not defined any maximum data rate.

5.6 Data Transmission

 A typical hardware setup using two shift registers to form an inter-hip circular buffer.

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  To begin a communication, the master first configures the clock, using a frequency less than or
equal to the maximum frequency the slave device supports.
 Such frequencies are commonly in the range of 1- 7 MHZ.
 The master then pulls the slave select SSEL low for the desired chip.
 During each SPI clock cycle, a full duplex data transmission occurs.
 The master sends a bit on the MOSI line; the slave reads it from that same line.
 The slave sends a bit on the MISO line; the master reads it from that same line.
 Transmission normally involve two shift registers of some given word size, such as eight bits,
one in the master and one in the slave; they are connected in a ring.
 After that register has been shifted out, the master and slave have exchanged values.
 Then each device takes that value and does something with it, such as writing it to memory.
 If there are more data to exchange, the shift registers are loaded with new data and the process
repeats.

5.7 Clock Polarity and Phase

 In addition to setting the clock frequency, the master must also configure the clock polarity and
phase with respect to the data.
 SPI Block guide names these two options as CPOL and CPHA respectively, and most vendors
have adopted that convention.

A timing diagram showing clock polarity and phase

 At CPOL=0, the base value of the clock is zero.

 For CPHA=0, data are read on the clock’s rising edge (low->high transition) and data are
changed on a falling edge (high->low clock transition).
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  For CPHA=1, data are read on the clock’s falling edge and data are changed on a rising edge.
 At CPOL=1, the base value of the clock is one (inversion of CPOL=0)
 For CPHA=0, data are read on clock’s falling edge and data are changed on a rising edge.
 For CPHA=1, data are read on clock’s rising edge and data are changed on a falling edge.

l Mode Numbers
The combinations of polarity and phases are often referred to as modes
MODE CPOL CPHA
0 0 0
1 0 1
2 1 0
3 1 1

5.8 Register Description

SPI has seven registers, from the programmers interface for SPI peripheral has five registers.
The bits in the rest of two TEST registers are intended for functional verification only.
NAME DESCRIPTION ACCESS
S0SPCR SPI Control Register. R/W
This register controls the
operation of the SPI.
S0SPSR SPI Status Register. R0
This register shows the status
of the SPI.
S0SPDR SPI Data Register. R/W
This bi-directional register
provides the transmit and
receive data for the SPI.
S0SPCCR SPI Clock Counter Register. R/W
This register controls the
frequency of a master’s SCK
S0SPINT SPI Interrupt Flag. R/W
This register contains the
interrupt flag for the SPI
interface.

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SPI Control Register
(S0SPCR – 0Xe002 0000)
BIT SYMBOL VALUE DESCRIPTION
1:0 - Reserved, user
software should not
write ones to reserved
bits.
2 Bit-Enable 0 The SPI controller
sends and receives 8
bits of data per
transfer.
The SPI controller
1 sends and receives
the number of bits
selected by bits 11:8
3 CPHA Clock phase control
0 Data is sampled on
the first clock edge of
SCK.
1 Data is sampled on
the second clock edge
of the SCK.
4 CPOL Clock phase control
0 SCK is active high.
1 SCK is active low.
5 MSTR Master mode select.
0 The SPI operates in
salve mode.
6 LSBF LSB First, controls in
which direction each
byte is shifted when
transferred.
0 SPI data is
transferred MSB (bit
7) first.
1 SPI data is
transferred LSB (bit
0) first.
7 SPIE Serial peripheral
interrupt enable.
0 SPI interrupts are
inhibited.
1 A hardware interrupt
is generated each
time the SPIF or
MODF bits are
activated.
11:8 When bit 2 of this

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 register is 1, this field
controls the number
of bits per transfer:
1000 8 bits per transfer
1001 9 bits per transfer
1010 10 bit per transfer
1011 11 bits per transfer
1100 12 bits per transfer
1101 13 bits per transfer
1110 14 bits per transfer
1111 15 bits per transfer
0000 16 bits per transfer
15:12 - Reserved, user
software should not
write ones to reserved
bits.

SPI Data Register

(S0SPDR-0xE002 0008)
 This bi-directional data register provides the transmit and receive data for the SPI.
 Transmit data is provide to the SPI by writing to this register.
 Data received by the SPI can be read from this register.

 There is no buffer between the data register and the internal shift register. A write to the data
register goes directly into the internal shift register.
 Therefore, data should only be written to this register when a transmit is not currently in
progress.
 Read data is buffered.
 When a transfer is complete, the receive data is transferred to a single byte data buffer, where it
is later read.
 A read of the SPI data register returns the value of the read data buffer.

BIT SYMBOL DESCRIPTION

7:0 Data low SPI bi-directional data port.
15:8 Data high If bi 2 of the SPCR is 1 and
bits 11:8 are other than 1000,
some or all of these bits

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 contain the additional
transmit and receive bits.
When less than 16 bits are
selected, the most significant
among these bits read as
zeroes.

SPI Status Register

(S0SPSR-0xE002 0004)
BIT SYMBOL DESCRIPTION
7 SPIF SPI transfer complete flag.
When 1, this bit indicates
when a SPI data transfer is
complete.
When a master, this bit is set
at the end of the last cycle of
the transfer.
When a slave, this bit is set
on the last data sampling edge
of the SCK.
This bit is cleared by first
reading this register then
accessing the SPI data
register.
6 WCOL Write collision. when1, this
bit indicates that a collision
has occurred. This bit is
cleared by reading this
register then accessing the
SPI data register.

l Exception conditions – Write Collision

 As stated previously, there is no write buffer between the SPI block bus interface, and the
internal shift register.
 As a result, data must not be written to the SPI data register when a SPI data transfer is
currently in progress.
 The time frame where data cannot be written to the SPI data register is from when the transfer
starts, until after the status register has been read when the SPIF status is active.
 If the SPI data register is written in this time frame, the write data will be lost, and the write
collision (WCOL) bit in the status register will be activated.

BIT SYMBOL DESCRIPTION

5 ROVR Read overrun. When 1, this it
indicates that a read overrun
has occurred. This bit is
cleared by reading this

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 register.

l Exception conditions – Read Overrun

 A read overrun occurs when the SPI block internal read buffer contains data that has not been
read by the processor, and a new transfer is completed.
 The read buffer containing valid data is indicated by the SPI bit in the status register active.
 When a transfer completed, the SPI block needs to move the received data to the read buffer.
 If the SOIF bit is active (the read buffer is full), the new receive data will be lost, and the read
overrun (ROVR) bit in the status register will be activated.

BIT SYMBOL DESCRIPTION

4 MODF Mode fault. When 1, this bit
indicates that a mode fault
error has occurred. This bit is
cleared by reading this
register, then writing the SPI
control register.

l Exception conditions – Mode Fault

If the SSEL signal goes active, when the SPI block is a master, this indicates another master has
selected the same device to be a slave. This condition is known as a mode fault.
When a mode fault is detected, the mode fault (MODF) bit in the status register will be activated.

BIT SYMBOL DESCRIPTION

3 ABRT Slave abort. When 1, this bit
indicates that a slave abort
has occurred. This bit is
cleared by reading this
register.
2:0 - Reserved, user software
should not write ones to
reserved bits.

l Exception conditions – Slave Abort

 A slave transfer is considered to be aborted, if the SSEL signal goes inactive before the transfer
is complete.
 In the event of a slave abort, the transmit and receive data for the transfer that was in progress
are lost, and the slave abort (ABRT) bit in the status register will be activated.

SPI Interrupt register

(S0SPINT-0xE002 001C)
This register contains the interrupt flag for the SPI interface.

BIT SYMBOL DESCRIPTION

0 SPI Interrupt Flag SPI interrupt flag. Set by the
SPI interface to generate an
interrupt. Cleared by writing
a 1 to this bit.

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 7:1 - Reserved, user software
should not write ones to
reserved bits.

SPI Clock Counter Register

(S0SPCCR-0xE002 000C)
 This register controls the frequency of a master’s SCK.
 The register indicates the number of PCLK cycles that makes up an SPI clock.
 The value of this register must always be an even number. As a result, bit 0 must always be 0.

5.9 Configuration
SPI can be configured as MASTER or SLAVE.

Configuration – Master operation

The following sequence describes how one should process a data transfer with the SPI block when it is
set up to be the master.
This process assumes that any prior data transfer has already completed.
1. Set the SPI Clock counter register to the desired clock rate.
1. Set the SPI Control register to the desired settings.
1. Write the data that transmitted to the SPI data register. This write stats the SPI data transfer.
1. Wait for the SPIF bit in the SPI status register to be set to 1. The SPIF bit will be set after the
last cycle of the SPI data transfer.
1. Read the SPI status register
1. Read the received data from the SPI data register
1. Go to step 3 if more data is required to transmit.
Note: A read or write of the SPI data register is required in order to clear the SPIF status bit.
Therefore, if the optional read of the SPI data register does not take place, a write to this register is
required in order to clear the SPIF status bit.

Configuration – Slave operation

The following sequence describes how one should process a data transfer with the SPI block when it is
set up to be the slave.
This process assumes that any prior data transfer has already completed.
1. Set the SPI control register to the desired settings.
1. Write the data to transmitted to the SPI data register. Note that this can only be done when a
slave SPI transfer is not in progress.
1. Wait for the SPIF bit in the SPI status register to be set to 1. The SPIF bit will be set after the
last sampling clock edge of the SPI data transfer.
1. Read the SPI status register.
1. Read the received data from the SPI data register
1. Go to step 2 if more data is required to transmit.
Note: A read or write of the SPI data register is required in order to clear the SPIF status bit.
Therefore, at least one of the optional reads or writes of the SPI data register must take place, in
order to clear the SPIF status bit.

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Real life Usage

 Consumer Electronics
Used in mobile phones for:
 Flash memory (NOR/NAND)
 Touchscreen controllers (fast sampling)
 Display drivers (AMOLED / TFT)
 Wi-Fi, Bluetooth, and GPS chips often communicate with the main processor via SPI.

 Embedded Systems / Microcontrollers

Connects high-speed peripherals to controllers like Arduino, STM32, ESP32:
 SD cards
 External Flash memories
 High-speed ADCs / DACs
 LCD/TFT/OLED displays
 Audio Codecs

 Industrial & Automation

 High-speed sensors:
 Pressure sensors
 Industrial accelerometers
 High-speed temperature sensors
 Motor controllers, encoders, and robotics use SPI for fast feedback.

 Communication Modules
Used heavily in RF and wireless modules:
 LoRa 433/868 MHz modules
 NRF24L01 wireless transceiver
 BLE modules
SPI provides high-speed configuration and data transfer.

 Storage Devices
 SD cards use SPI mode as an alternative to SDIO.
 External EEPROM and Flash memories communicate over SPI.

 Displays & LEDs

 LED drivers (WS2801, APA102).
 TFT displays (ILI9341, ST7735).
 High frame-rate LCD modules.

ADVANTAGES DISADVANTAGES
Full duplex communication Requires more pins on IC packages than
I2C, even in the “3-wire” variant.
Higher throughput than I2C No hardware flow control
Complete protocol flexibility for the bits No hardware slave acknowledgment (the
transferred master could be “talking” to nothing and not
 Not limited to 8-bit words know it)
 Arbitrary choice of message size,

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 content, and purpose
Extremely simple hardware interfacing Supports only one master device.
 Typically lower power requirements Only handles short distance compared to
than I2C due to less circuitry RS-232, RS-485, or CAN-bus.
 No arbitration or associated failure
modes
 Slaves use the master’s clock, and
don’t need precision oscillators
 Transceivers are not needed.

5.10 Interview Question

1. What does SPI stand’s for?

2. SPI is serial or parallel communication?
3. What is the SPI communication protocol?
4. How many wires are required for SPI communication?
5. What are the 4 logic signals specified by the SPI bus?
6. Is it possible to have multiple masters in SPI?
7. What is the role of the shift register in Master and Slave devices in SPI?
8. Does SPI slave acknowledge the receipt of data?
9. SPI has a higher throughput than I2C – True / False?
10. Is SPI support duplex communication?
11. Why use SPI?
12. SPI is Synchronous or Asynchronous Communication?
13. Does start-stop bit support by SPI?
14. Does pull-up register require in SPI? Does bus arbitration support by SPI?
15. Does the clock stretching support by SPI?
16. What is the difference between SPI and I2C (I2C vs SPI)?
17. What are the advantages and disadvantages of the SPI communication protocol?
18. What will happens if two SPI slaves same time communicate with Master (two Cs pins are
high)?

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 UART
(UNIVRSAL ASYNCHRONOUS RECEIVER TRANSMITTER)

6 Introduction

UART – stands for Universal Asynchronous Receiver Transmitter.

It is a piece of hardware that acts as a bridge between the processor and the serial communication
protocol or port (RS-232).
It performs parallel – to – serial data conversion at the transmitter side and serial – to – parallel data
conversion at the receiver side.
Asynchronous serial communication.

6.1 Why UART?

A serial communication can be done using fewer wires as compared to its parallel counter part.

 It is a cheapest communication device with a single wire for transmitting the data and another
wire for receiving.
 When the high-speed data transfer is not required UART is used.

6.2 Block diagram

Microprocessor / Microcontroller
Sends and receives data to/from the UART.
Communicates using a parallel data bus and control bus.

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Sender UART (Transmit section)
Takes parallel data IN from the processor.
Coverts parallel data info serial data. Sends this serial data to the serial connector (TX line).
Receiver UART
 Takes serial data from the serial connector (RX line).
 Converts serial data into parallel data OUT.
 Sends the parallel data back to the processor.

6.3 Serial Connector (RS-232/USB)

Acts as the physical interface to send / receive data serially.

6.4 Transmitter Section

1. Transmit Hold Register

 Stores the parallel data from CPU temporarily.
 Feeds data to the transmit shift register.

2. Transmit Shift Register

 Converts parallel data – serial data (bit-by-bit shifting).
 Sends the serial data out via TX.

3. Control Logic (TX)

 Controls when to load data.
 Manages start, stop, parity bits.

6.5 Receiver Section

1. Receiver Shift Register

 Receives serial data from RX.
 Coverts serial to parallel.

2. Receiver Hold Register

 Hold the parallel data for the CPU to read.
 Prevents data loss until CPU reads it.

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3. Control Logic (RX)
 Detects start bit, stop bit, parity.
 Controls timing and data loading.
Baud Rate Generator

 Provides timing clock for both transmitter and receiver.

 Makes sure TX and RX work at the same speed.

6.6 UART TxD

 Transmit Holding Register (THR – 8 bits)

 CPU / software writes 1 byte (8 bits) into the THR.
 THR temporarily stores the parallel data.

 FIFO
 If mulitple bytes are written, they are stored in the FIFO.
 Helps smooth transmission without losing data.

 Internal shift register

 Data from THR/FIFO is copied into the shift register
 Coverts parallel data to serial data.

 Bit Shifting process

 Bits are shifted out one bit at a time on each clock pulse.
 The output goes through the TX line.

 UART adds framing bits

Start bit = 0
Data bits = 8 bits
Stop bit = 1

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so the transmission frame looks like:

Start | Data Bits | Stop

0 | 10110001| 1

6.7 UART RxD

1. Incoming serial data (RX input)

Data comes bit-by-bit from the Tx of another device.
Frame includes: Start bit – Data bits – Stop bit.

2. Clock sampling
UART samples the incoming line using a clock.
Detects the start bit (0) to begin reading data.

3. Receiver Buffer Register (8 bits)

After 8 data bits are received, they are moved to this register.
Holds the parallel byte for the CPU/Software to read.

4. FIFO
If multiple bytes arrive, FIFO stores them.
Prevents data loss when CPU is slow to read.

In a simple serial communication, 3 pins are used: TxD, RxD and GND.
At transmission side (i.e. from microcontroller), one can write data into UART Data Register (e.g.
UART0_DR) by using software code.
These 8 bits of data from Data Register is passed to Tx FIFO Buffer. After that, the data is sent out(one
at a time) from Tx Shift Register.
Tx FIFO flag = 1 (Buffer full) TXFIFO flag = 0 (not full – software can write to Data Register).

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 At receiver end, there is RX FIFO Buffer.
RXFIFO Empty flag = 1 (Buffer is Empty) RXFIFO Empty flag = 0 (Buffer has data to be
read).

6.8 How UART Works

1. UART Sends Data in a Frame

A UART frame contains these parts:
Start bit (0)
Data bits (5-9 bits)
Optional Parity bit
Stop bit(s) (1 or 2)

2. Start Bit
 Always 0.
 Tells the receiver: “Data is starting now”.

3. Data Bits
Actual data being sent (example: bits 0-7).
Sent LSB first (least significant bit).

4. Parity bit (optional)

Error-checkong bit.
Can be Even, Odd, or None.

5. Stop bit(s)
Always 1. Indicates the end of the data frame.
Gives time for receiver to reset.

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Frame

 A frame is the unit of transmission in serial communications.

 Start bit: To declare the start of transmission.
 Data bits: 4,5,6,7 or 8 bits of useful data bits.
 Parity bit: To check for transmission errors.
 Stop bit: To declare end of frame.

Parity
 Parity bit is used to check the integrity of a frame and signal if an error occurred during
transmission.
 It is an extra bit added to the end of a frame.
 Even parity: The number of ‘1’ symbols inside a frame must always be even.
 Odd parity: The number of ‘1’ symbols inside a frame must always be odd.

6.9 Transmission and reception

6.10 Configuration
The configuration settings at both ends of Txd and Rxd:
 Full or half-duplex operation
 Data length
 Start/Stop bits
 Transmission speed.

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Real Life Usage

1. Microcontroller communication

 Arduino ↔ Sensors/modules
 STM32 / ESP32 / PIC communication
 Debug consoles during firmware development.
2. Embedded systems
 GPS modules
 GSM/LTE modules (SIM800, A7680C, Quectel, etc.)
 RFID readers
 Motor controllers
 Industrial controllers
3. Consumer electronics
 PC peripherals
 Old mice and modems
 Set-top boxes (debug UART ports)
4. PC / Server / Router Diagnostics
 Routers have hidden UART pins for firmware flashing
 Servers/boards expose UART for boot logs
5. Automotive
 Communication between ECUs and diagnostic tools
 Tuning equipment

6. Robotics
 Inter-module communication (motor drivers, IMUs, LiDAR, etc.)
l Main Features of UART
l Asynchronous communication (no shared clock)
l Full-duplex (TX and RX separate)
l Configurable baud rate (9600, 115200, etc.)
l Simple hardware interface (just TX, RX, GND)
l Framing structure: Start bit, Data bits, Parity bit (optional), Stop bit(s)

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 l Supports parity: none, even, odd
l Point-to-point communication only
l Well supported across almost all microcontrollers and CPUs
Applications of UART
1. Embedded device communication
l Sending commands or sensor data
l Remote debugging
l Logging system events
2. Peripheral interfacing
l Connecting modules (Bluetooth HC-05, GPS NEO-6M, LoRa SX1278)
l Motor controllers (e-bike ECUs, servo boards)
3. Industrial
l Factory automation devices
l PLC modules
l Testing equipment
4. Communication bridges
l UART–USB (FTDI, CH340, CP2102)
l UART–SPI or UART–I2C converters
Advantages and Disadvantages
 Advantages
 Requires minimum wires
 No need from clock or any other timing signal.
 Parity bit ensures basic error checking.
Disadvantages
 Size of the data in the frame is limited.
 Can connect only two devices at a time.
 Speed for data transfer is less compared to parallel.
 Transmitter and receiver must agree to the rules of transmission and appropriate baud rate must
be selected.

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6.11 Interview Questions
1. What does UART stand for?
2. What is UART and how does it work?
3. What is the difference between UART, SPI and I2C?
4. What is the baud rate in UART communication, and how is it determined?
5. How does the UART transmitter and receiver synchronize the data transmission and reception?
6. What is the biffer in UART, and how does it work?
7. How does flow control work in UART, and what are the different types of flow control?
8. What are the advantages of UART over other communication protocols/
9. Can you explain how errors can occur in UART communication, and how they can be corrected
?
10. What is a UART frame, and what does it consist of ?
11. What is the maximum data rate that can be achieved with UART communication, and how can
it be improved ?
12. What are the different types of UART errors, and how can they be detected and corrected ?
13. What is the role of the UART buffer, and how does it help improve communication reliability ?
14. What are the different UART modes, and how are they used in different applications ?
15. What is the difference between UART and SPI communication ?
16. What is the purpose of the UART baud rate, and how is it configured ?
17. What is flow control, and how is it used in UART communication ?
18. What is the purpose of the UART parity bit, and how does it help detect errors ?
19. What is the role of the UART controller, and how does it interact with other components in a
system?

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 I2C
(INTER INTEGRATED CIRCUIT)

7 Introduction

• I2c stands for inter-integrated circuit. It is a well-known bus invented by Philips Semiconductor
in
• 1982.
• It is a synchronous, multi-master, multi-slave, packet switched, single ended 2-wire bus having
data
• rate of about 100 kbps, 400-450 kbps and 3.4 Mbps.
• It combines the best features of SPIs and UARTs.
• With I2C, we can connect multiple slaves to a single master and can have multiple masters
• controlling single, or multiple slaves.
• This is really useful when you want to have more than one micro-controller logging data to a
single
• memory card or displaying text to a single LCD.
• It is widely used for attaching lower-speed peripheral ICs to processors and micro-controllers in
• short-distance, intra-board communication.
• A particular strength of I2C is the capability of it microcontroller to control a network of device
chip
• with just two general-purpose I/O pins and software.
• Many other bus technologies used in similar applications, such as Serial Peripheral Interface Bus,
• require more pins and signals to connect multiple devices.

7.1 Design

I2C uses only two bidirectional open-drain lines :

1. Serial Data Line (SDL)
2. Serial Clock Line (SCL), pulled up the resistors.

 Typical voltages used are +5v or +3.3v, although systems with other voltages are permitted.

Fig: An I2C pull-up resistor connection

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  The I2C bus drivers are “open drain”, meaning that they can pull the corresponding signal line
low, but cannot drive it high.
 Thus, there can be no bus contention where one device is trying to drive the line high while
another tries to pull it low, eliminating the potential for damage to the drivers or excessive
power dissipation in the system.
 Each signal line has a pull-up resistor on it, to restore the signal to high when no device is
asserting it low.

7.2 Interface

Connections are minimized by using a serial data (SDA) line, a serial clock (SCL) line, and a common
ground to carry all communications.

Master Slave
Fig:
I2C

Master to Slave Communication

There are two wires in each I2C device:

 The SDA is the line for the main device and node to send and receive data.
 The SCL is the line that carries the clock signal. The SCL is always generated by the I2C main.
The specification requires minimum periods for the low and high phases of the clock signal.
The bus has two roles for nodes: Master and Slave:
1. Master node: Node that generates the clock and initiates communication with slaves.
2. Slave node: Node that receives the clock and responds when addressed by present.
 The bus is a multi-master bus, which means that any number of master nodes can be present.
 Additionaly, master and slave roles may be changed between messages(after a STOP is sent).
There may be four potential modes of operation for a given bus devices, although most devices only
use a single role and its two modes:
 Master transmit – Master node is sending data to a slave.
 Master receive – Master node is receiving data from a slave.
 Slave transmit – Slave node is sending data to the master.
 Slave receive – Slave node is receiving data from the master.

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7.3 How I2C works
• With I2C, data is transferred in messages. Messages are broken up into frames of data.
• Each message has an address frame that contains the binary address of the slave, and one or
more data frames that contain the data being transmitted.
• The message also contains start and stop conditions, read/write bits, and ACK/NACK bits
between each data frame.

Fig: I2C Message Frame format

Messages are broken up into two types of frame:

 Address frame: The master indicates the slave to which the message is being sent.
 Data frame: These are 8-bit data messages passed from master to slave or vice versa.
Data is placed on the SDA line after SCL goes low, and is sampled after the SCL line goes high.
Start Condition: The SDA line switches from high voltage level to low voltage level before the SCL
line switches from high to low.
Stop Condition: The SDA line switches from low voltage level to high voltage level after the SCL line
switches from low to high.
Address Frame: A 7 or 10 bit sequence unique to each slave that identifies the slave when the master
wants to talk to it.
Data Frame: After the address frame has been sent, data can begin being transmitted.
Read/Write Bit: A single bit specifying whether the master is sending data to the slave or requesting
data from slave.
ACK/NACK Bit: Each frame in a message is followed by an acknowledge/non-acknowledge bit.

7.4 Types of Transactions in I2C

I2C defines basic three types of transactions, each of which begins with a START and ends with a
STOP.
 Single message where a master writes data to a slave .
 Single message where a master reads data from a slave.
 Combined format, where a master issues at least two rads or writes to one or more slaves.

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In a combined transactions, each read or write begins with a START and the slave address.
 The START condition after the first are also called repeated START bits.
 Repeated STARTs are not preceded by STOP conditions, which is how slaves know that the
next message is part of the same transaction.
7.5 Timing Diagram

 Data transfer is initiated with a start bit (S) signaled by SDA being pulled low while SCL stays
high.
 SCL is pulled low, and SDA sets the first data bit level while keeping SCL low.
 The data are sampled (received) when SCL rises for the first bit (B1). For a bit to be valid, SDA
must not change between a rising edge of SCL and the subsequent falling edge.
 This process repeats, SDA transitioning while SCL is low, and the data being read while SCL is
high (B2, ...Bn).
 A stop bit (P) is signaled when SCL rises, followed by SDA rising.

7.6 Clock stretching

 This is also referred to as clock synchronization.
 Purpose: Clock stretching allows a slower device to stop the communication for a short time.
 How it works: The slave device keeps the SCL (clock line) low to pause data transfer.
 Why it is needed: This gives the slave more time to get ready or finish its task before
continuing.
 The master must wait until SCL goes high again before sending more data.
 The I2C standard doesn’t limit how long a device can hold SCL low.

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7.7 Which I2C Node Devices Need Clock Stretching?
Whether or not clock stretching is needed depends on the functions of the node device. Here are two
examples:
 A processing device, such as a microprocessor or a microcontroller, may need additional time to
process an interrupt, receive and manage data, and perform the appropriate function(s).
 A simpler device, such as an EEPROM, does not process data internally, so it does not need
clock stretching to perform any of its functions.

Reserved address in I2C

Binary address Hex address Description

0000 000 0x00 General Call Address (used for
broadcasting commands like
reset).
0000 001 0x01 START Byte Address (used for
clock synchronization).
0000 010 0x02 – Reserved for different bus
0x03 formats (used when integrating
I2C with other protocols).
0000 100 - 0x04 - Reserved for future use.
0000 111 0x07
0000 1xx 0x08 - High-Speed Mode (Hs-mode)
0x0F Controller Codes (used to enter
high-speed mode).
1111 0xx 0x78 - 10-bit Addressing Prefix
0x7B (indicates a 10-bit address is
being sent).
1111 1xx 0x7C - Device ID / Future Reserved
0x7F Addresses.

Real-Life Usage
 Used inside smartphones, laptops, and microcontrollers to connect chips like sensors, memory,
and displays.
 Found in systems like Arduino, Raspberry Pi, and other embedded devices.
 Common in temperature sensors, EEPROMs, RTCs (real-time clocks), and LCD displays

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 FEATURES APPLICATIONS
Uses two wires only – SDA (data) and SCL Sensors: temperature, humidity, pressure sensors.
(clock)
Supports multiple masters and slaves on one bus. Displays: LCD or OLED displays
Can communicate at different speeds (Standard: Memory devices: EEPROM, flash storage.
100 kHz, Fast: 400 kHz, etc.).
Each devices has a unique 7-bit or 10-bit address. Real-time clock (RTC): for keeping time.
Supports clock stretching for synchronization. Microcontroller communication: Between chips in
embedded systems.
Works well for short-distance communication. Audio/video systems and industrial equipment
control.

ADVANTAGES DISADVANTAGES
Only two wires needed, saving pins and space. Limited distance — best for communication
within a few meters.
Simple design and easy to implement. Lower speed compared to SPI or UART.
Allows multiple devices on one bus. Complex addressing if many devices share the
same bus
Supports error checking (ACK/NACK bits). Pull-up resistors required on lines.
Flexible – works with different voltages and Not ideal for high-noise environments (since it’s
speeds. open-drain).

7.8 Interview Questions

1. What is I2C, and how does it work?
2. What are the advantages of using I2C over other communication protocols?
3. How many devices can be connected to an I2C bus?
4. What are some advanced features of I2C , and how are they used?
5. What is the difference between I2C standard mode and fast mode?
6. How is clock synchronization maintained in I2C communication?
7. What are some common applications of I2C?
8. How do I2C devices communicate with each other?
9. How does I2C compare to other communication protocols such as SPI and UART?
10. How is data transferred over the I2C bus, and what is the format of an I2C message?
11. How does I2C support different clock speeds and data rates?
12. How do I2C devices handle errors and retries during communication?

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 13. What are some common issues that can arise when using I2C, and how can they be resolved?
14. How does clock stretching work in I2C communication?
15. What is the maximum number of devices that can be connected to an I2C bus?
16. What is the difference between an I2C master and an I2C slave?
17. What is clock stretching and why is it used in I2C communication?
18. What are the reserved address in I2C ?
19. Explain the 10 BIT Addressing mode in I2C?

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